[ARM] mmp: support ssp in pxa168

Support ssp devices in PXA168. PXA168 could reuse the code of PXA SSP.

Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>

1 files changed, 5 insertions, 5 deletions

diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h
index 712af03fd1af..1a96585336ba 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apbc.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h
@@ -26,8 +26,6 @@
 #define APBC_PXA168_PWM2        APBC_REG(0x010)
 #define APBC_PXA168_PWM3        APBC_REG(0x014)
 #define APBC_PXA168_PWM4        APBC_REG(0x018)
-#define APBC_PXA168_SSP1        APBC_REG(0x01c)
-#define APBC_PXA168_SSP2        APBC_REG(0x020)
 #define APBC_PXA168_RTC         APBC_REG(0x028)
 #define APBC_PXA168_TWSI0       APBC_REG(0x02c)
 #define APBC_PXA168_KPC         APBC_REG(0x030)
@@ -35,14 +33,16 @@
 #define APBC_PXA168_AIB         APBC_REG(0x03c)
 #define APBC_PXA168_SW_JTAG     APBC_REG(0x040)
 #define APBC_PXA168_ONEWIRE     APBC_REG(0x048)
-#define APBC_PXA168_SSP3        APBC_REG(0x04c)
 #define APBC_PXA168_ASFAR       APBC_REG(0x050)
 #define APBC_PXA168_ASSAR       APBC_REG(0x054)
-#define APBC_PXA168_SSP4        APBC_REG(0x058)
-#define APBC_PXA168_SSP5        APBC_REG(0x05c)
 #define APBC_PXA168_TWSI1       APBC_REG(0x06c)
 #define APBC_PXA168_UART3       APBC_REG(0x070)
 #define APBC_PXA168_AC97        APBC_REG(0x084)
+#define APBC_PXA168_SSP1        APBC_REG(0x81c)
+#define APBC_PXA168_SSP2        APBC_REG(0x820)
+#define APBC_PXA168_SSP3        APBC_REG(0x84c)
+#define APBC_PXA168_SSP4        APBC_REG(0x858)
+#define APBC_PXA168_SSP5        APBC_REG(0x85c)
 
 /*
  * APB Clock register offsets for PXA910