Merge branch 'lpc32xx/devel' into next/soc

* lpc32xx/devel: (22 commits)
  ARM: LPC32xx: Move i2s1 dma enabling to clock.c
  ARM: LPC32xx: Move uart6 irda disable to serial.c
  ARM: LPC32xx: Cleanup board init, remove duplicate clock init
  ARM: LPC32xx: Remove spi chip definitions
  ARM: LPC32xx: Remove spi chipselect request from board init
  ARM: LPC32xx: Add dt settings to the at25 node
  ARM: LPC32xx: Build arch dtbs
  ARM: LPC32xx: Fix lpc32xx.dtsi status property: "disable" -> "disabled"
  ARM: LPC32xx: Remove mach specific ARCH_NR_GPIOS, use default
  ARM: LPC32xx: High Speed UART configuration via DT
  ARM: LPC32xx: DT conversion of Standard UARTs
  ARM: LPC32xx: DTS adjustment for using pl18x primecell
  ARM: LPC32xx: Add MMC controller support
  ARM: LPC32xx: Defconfig update
  ARM: LPC32xx: Clock adjustment for key matrix controller
  ARM: LPC32xx: DTS adjustment for key matrix controller
  ARM: LPC32xx: Add dts for EA3250 reference board
  ARM: LPC32xx: Adjust dtsi file for MLC controller configuration
  ARM: LPC32xx: Add DMA configuration to platform data
  ARM: LPC32xx: Remove SLC controller initialization from platform init
  ...

1 files changed, 17 insertions, 4 deletions

diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index f6a3ffec1f4b..e8d315e6db09 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -691,10 +691,21 @@ static struct clk clk_nand = {
         .parent         = &clk_hclk,
         .enable         = local_onoff_enable,
         .enable_reg     = LPC32XX_CLKPWR_NAND_CLK_CTRL,
-        .enable_mask    = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN,
+        .enable_mask    = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN |
+                          LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
         .get_rate       = local_return_parent_rate,
 };
 
+static struct clk clk_nand_mlc = {
+        .parent         = &clk_hclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_NAND_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN |
+                          LPC32XX_CLKPWR_NANDCLK_DMA_INT |
+                          LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC,
+        .get_rate       = local_return_parent_rate,
+};
+
 static struct clk clk_i2s0 = {
         .parent         = &clk_hclk,
         .enable         = local_onoff_enable,
@@ -707,7 +718,8 @@ static struct clk clk_i2s1 = {
         .parent         = &clk_hclk,
         .enable         = local_onoff_enable,
         .enable_reg     = LPC32XX_CLKPWR_I2S_CLK_CTRL,
-        .enable_mask    = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN,
+        .enable_mask    = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN |
+                          LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA,
         .get_rate       = local_return_parent_rate,
 };
 
@@ -1120,8 +1132,9 @@ static struct clk_lookup lookups[] = {
         CLKDEV_INIT("31020300.i2c", NULL, &clk_i2c2),
         CLKDEV_INIT("dev:ssp0", NULL, &clk_ssp0),
         CLKDEV_INIT("dev:ssp1", NULL, &clk_ssp1),
-        CLKDEV_INIT("lpc32xx_keys.0", NULL, &clk_kscan),
-        CLKDEV_INIT("lpc32xx-nand.0", "nand_ck", &clk_nand),
+        CLKDEV_INIT("40050000.key", NULL, &clk_kscan),
+        CLKDEV_INIT("20020000.flash", NULL, &clk_nand),
+        CLKDEV_INIT("200a8000.flash", NULL, &clk_nand_mlc),
         CLKDEV_INIT("40048000.adc", NULL, &clk_adc),
         CLKDEV_INIT(NULL, "i2s0_ck", &clk_i2s0),
         CLKDEV_INIT(NULL, "i2s1_ck", &clk_i2s1),