diff options
author | Ben Dooks <ben-linux@fluff.org> | 2008-08-08 16:10:12 -0400 |
---|---|---|
committer | Ben Dooks <ben-linux@fluff.org> | 2008-08-08 16:10:12 -0400 |
commit | af7a535688a758d15f06a98833e6a143b29af9de (patch) | |
tree | bac5ab210bbbbe276f0e44ed84194d7c8bb16aae /arch/arm/mach-lh7a40x | |
parent | 0c17e4ceedd35c78b1c7413dbd16279a350be6bc (diff) | |
parent | c41107c2d4fd31924533f4dbc4c3428acc2b5894 (diff) |
Merge http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm into for-rmk
Diffstat (limited to 'arch/arm/mach-lh7a40x')
24 files changed, 1136 insertions, 15 deletions
diff --git a/arch/arm/mach-lh7a40x/arch-kev7a400.c b/arch/arm/mach-lh7a40x/arch-kev7a400.c index 2ef7d0097b38..551b97261826 100644 --- a/arch/arm/mach-lh7a40x/arch-kev7a400.c +++ b/arch/arm/mach-lh7a40x/arch-kev7a400.c | |||
@@ -13,7 +13,7 @@ | |||
13 | #include <linux/device.h> | 13 | #include <linux/device.h> |
14 | #include <linux/interrupt.h> | 14 | #include <linux/interrupt.h> |
15 | 15 | ||
16 | #include <asm/hardware.h> | 16 | #include <mach/hardware.h> |
17 | #include <asm/setup.h> | 17 | #include <asm/setup.h> |
18 | #include <asm/mach-types.h> | 18 | #include <asm/mach-types.h> |
19 | #include <asm/mach/arch.h> | 19 | #include <asm/mach/arch.h> |
diff --git a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c index fe64946f9e18..e373fb8e2699 100644 --- a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c +++ b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c | |||
@@ -14,7 +14,7 @@ | |||
14 | #include <linux/interrupt.h> | 14 | #include <linux/interrupt.h> |
15 | #include <linux/irq.h> | 15 | #include <linux/irq.h> |
16 | 16 | ||
17 | #include <asm/hardware.h> | 17 | #include <mach/hardware.h> |
18 | #include <asm/setup.h> | 18 | #include <asm/setup.h> |
19 | #include <asm/mach-types.h> | 19 | #include <asm/mach-types.h> |
20 | #include <asm/mach/arch.h> | 20 | #include <asm/mach/arch.h> |
diff --git a/arch/arm/mach-lh7a40x/clcd.c b/arch/arm/mach-lh7a40x/clcd.c index 1992db4c2523..a2a543258fc3 100644 --- a/arch/arm/mach-lh7a40x/clcd.c +++ b/arch/arm/mach-lh7a40x/clcd.c | |||
@@ -17,14 +17,13 @@ | |||
17 | 17 | ||
18 | //#include <linux/module.h> | 18 | //#include <linux/module.h> |
19 | //#include <linux/time.h> | 19 | //#include <linux/time.h> |
20 | //#include <asm/hardware.h> | ||
21 | 20 | ||
22 | //#include <asm/mach/time.h> | 21 | //#include <asm/mach/time.h> |
23 | #include <asm/irq.h> | 22 | #include <asm/irq.h> |
24 | #include <asm/mach/irq.h> | 23 | #include <asm/mach/irq.h> |
25 | 24 | ||
26 | #include <asm/system.h> | 25 | #include <asm/system.h> |
27 | #include <asm/hardware.h> | 26 | #include <mach/hardware.h> |
28 | #include <linux/amba/bus.h> | 27 | #include <linux/amba/bus.h> |
29 | #include <linux/amba/clcd.h> | 28 | #include <linux/amba/clcd.h> |
30 | 29 | ||
diff --git a/arch/arm/mach-lh7a40x/clocks.c b/arch/arm/mach-lh7a40x/clocks.c index 7530a95c15a6..4fb23ac6b5ac 100644 --- a/arch/arm/mach-lh7a40x/clocks.c +++ b/arch/arm/mach-lh7a40x/clocks.c | |||
@@ -9,8 +9,8 @@ | |||
9 | */ | 9 | */ |
10 | 10 | ||
11 | #include <linux/cpufreq.h> | 11 | #include <linux/cpufreq.h> |
12 | #include <asm/hardware.h> | 12 | #include <mach/hardware.h> |
13 | #include <asm/arch/clocks.h> | 13 | #include <mach/clocks.h> |
14 | #include <linux/err.h> | 14 | #include <linux/err.h> |
15 | 15 | ||
16 | struct module; | 16 | struct module; |
diff --git a/arch/arm/mach-lh7a40x/include/mach/clocks.h b/arch/arm/mach-lh7a40x/include/mach/clocks.h new file mode 100644 index 000000000000..fe2e0255c084 --- /dev/null +++ b/arch/arm/mach-lh7a40x/include/mach/clocks.h | |||
@@ -0,0 +1,18 @@ | |||
1 | /* arch/arm/mach-lh7a40x/include/mach/clocks.h | ||
2 | * | ||
3 | * Copyright (C) 2004 Marc Singer | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or | ||
6 | * modify it under the terms of the GNU General Public License | ||
7 | * version 2 as published by the Free Software Foundation. | ||
8 | * | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_CLOCKS_H | ||
12 | #define __ASM_ARCH_CLOCKS_H | ||
13 | |||
14 | unsigned int fclkfreq_get (void); | ||
15 | unsigned int hclkfreq_get (void); | ||
16 | unsigned int pclkfreq_get (void); | ||
17 | |||
18 | #endif /* _ASM_ARCH_CLOCKS_H */ | ||
diff --git a/arch/arm/mach-lh7a40x/include/mach/constants.h b/arch/arm/mach-lh7a40x/include/mach/constants.h new file mode 100644 index 000000000000..55c6edbc2dfd --- /dev/null +++ b/arch/arm/mach-lh7a40x/include/mach/constants.h | |||
@@ -0,0 +1,91 @@ | |||
1 | /* arch/arm/mach-lh7a40x/include/mach/constants.h | ||
2 | * | ||
3 | * Copyright (C) 2004 Coastal Environmental Systems | ||
4 | * Copyright (C) 2004 Logic Product Development | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License | ||
8 | * version 2 as published by the Free Software Foundation. | ||
9 | * | ||
10 | */ | ||
11 | |||
12 | #ifndef __ASM_ARCH_CONSTANTS_H | ||
13 | #define __ASM_ARCH_CONSTANTS_H | ||
14 | |||
15 | |||
16 | /* Addressing constants */ | ||
17 | |||
18 | /* SoC CPU IO addressing */ | ||
19 | #define IO_PHYS (0x80000000) | ||
20 | #define IO_VIRT (0xf8000000) | ||
21 | #define IO_SIZE (0x0000B000) | ||
22 | |||
23 | #ifdef CONFIG_MACH_KEV7A400 | ||
24 | # define CPLD_PHYS (0x20000000) | ||
25 | # define CPLD_VIRT (0xf2000000) | ||
26 | # define CPLD_SIZE PAGE_SIZE | ||
27 | #endif | ||
28 | |||
29 | #if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) | ||
30 | |||
31 | # define IOBARRIER_PHYS 0x10000000 /* Second bank, fastest timing */ | ||
32 | # define IOBARRIER_VIRT 0xf0000000 | ||
33 | # define IOBARRIER_SIZE PAGE_SIZE | ||
34 | |||
35 | # define CF_PHYS 0x60200000 | ||
36 | # define CF_VIRT 0xf6020000 | ||
37 | # define CF_SIZE (8*1024) | ||
38 | |||
39 | /* The IO mappings for the LPD CPLD are, unfortunately, sparse. */ | ||
40 | # define CPLDX_PHYS(x) (0x70000000 | ((x) << 20)) | ||
41 | # define CPLDX_VIRT(x) (0xf7000000 | ((x) << 16)) | ||
42 | # define CPLD00_PHYS CPLDX_PHYS (0x00) /* Wired LAN */ | ||
43 | # define CPLD00_VIRT CPLDX_VIRT (0x00) | ||
44 | # define CPLD00_SIZE PAGE_SIZE | ||
45 | # define CPLD02_PHYS CPLDX_PHYS (0x02) | ||
46 | # define CPLD02_VIRT CPLDX_VIRT (0x02) | ||
47 | # define CPLD02_SIZE PAGE_SIZE | ||
48 | # define CPLD06_PHYS CPLDX_PHYS (0x06) | ||
49 | # define CPLD06_VIRT CPLDX_VIRT (0x06) | ||
50 | # define CPLD06_SIZE PAGE_SIZE | ||
51 | # define CPLD08_PHYS CPLDX_PHYS (0x08) | ||
52 | # define CPLD08_VIRT CPLDX_VIRT (0x08) | ||
53 | # define CPLD08_SIZE PAGE_SIZE | ||
54 | # define CPLD0A_PHYS CPLDX_PHYS (0x0a) | ||
55 | # define CPLD0A_VIRT CPLDX_VIRT (0x0a) | ||
56 | # define CPLD0A_SIZE PAGE_SIZE | ||
57 | # define CPLD0C_PHYS CPLDX_PHYS (0x0c) | ||
58 | # define CPLD0C_VIRT CPLDX_VIRT (0x0c) | ||
59 | # define CPLD0C_SIZE PAGE_SIZE | ||
60 | # define CPLD0E_PHYS CPLDX_PHYS (0x0e) | ||
61 | # define CPLD0E_VIRT CPLDX_VIRT (0x0e) | ||
62 | # define CPLD0E_SIZE PAGE_SIZE | ||
63 | # define CPLD10_PHYS CPLDX_PHYS (0x10) | ||
64 | # define CPLD10_VIRT CPLDX_VIRT (0x10) | ||
65 | # define CPLD10_SIZE PAGE_SIZE | ||
66 | # define CPLD12_PHYS CPLDX_PHYS (0x12) | ||
67 | # define CPLD12_VIRT CPLDX_VIRT (0x12) | ||
68 | # define CPLD12_SIZE PAGE_SIZE | ||
69 | # define CPLD14_PHYS CPLDX_PHYS (0x14) | ||
70 | # define CPLD14_VIRT CPLDX_VIRT (0x14) | ||
71 | # define CPLD14_SIZE PAGE_SIZE | ||
72 | # define CPLD16_PHYS CPLDX_PHYS (0x16) | ||
73 | # define CPLD16_VIRT CPLDX_VIRT (0x16) | ||
74 | # define CPLD16_SIZE PAGE_SIZE | ||
75 | # define CPLD18_PHYS CPLDX_PHYS (0x18) | ||
76 | # define CPLD18_VIRT CPLDX_VIRT (0x18) | ||
77 | # define CPLD18_SIZE PAGE_SIZE | ||
78 | # define CPLD1A_PHYS CPLDX_PHYS (0x1a) | ||
79 | # define CPLD1A_VIRT CPLDX_VIRT (0x1a) | ||
80 | # define CPLD1A_SIZE PAGE_SIZE | ||
81 | #endif | ||
82 | |||
83 | /* Timing constants */ | ||
84 | |||
85 | #define XTAL_IN 14745600 /* 14.7456 MHz crystal */ | ||
86 | #define PLL_CLOCK (XTAL_IN * 21) /* 309 MHz PLL clock */ | ||
87 | #define MAX_HCLK_KHZ 100000 /* HCLK max limit ~100MHz */ | ||
88 | #define HCLK (99993600) | ||
89 | //#define HCLK (119808000) | ||
90 | |||
91 | #endif /* __ASM_ARCH_CONSTANTS_H */ | ||
diff --git a/arch/arm/mach-lh7a40x/include/mach/debug-macro.S b/arch/arm/mach-lh7a40x/include/mach/debug-macro.S new file mode 100644 index 000000000000..85141ed5383d --- /dev/null +++ b/arch/arm/mach-lh7a40x/include/mach/debug-macro.S | |||
@@ -0,0 +1,39 @@ | |||
1 | /* arch/arm/mach-lh7a40x/include/mach/debug-macro.S | ||
2 | * | ||
3 | * Debugging macro include header | ||
4 | * | ||
5 | * Copyright (C) 1994-1999 Russell King | ||
6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | @ It is not known if this will be appropriate for every 40x | ||
15 | @ board. | ||
16 | |||
17 | .macro addruart,rx | ||
18 | mrc p15, 0, \rx, c1, c0 | ||
19 | tst \rx, #1 @ MMU enabled? | ||
20 | mov \rx, #0x00000700 @ offset from base | ||
21 | orreq \rx, \rx, #0x80000000 @ physical base | ||
22 | orrne \rx, \rx, #0xf8000000 @ virtual base | ||
23 | .endm | ||
24 | |||
25 | .macro senduart,rd,rx | ||
26 | strb \rd, [\rx] @ DATA | ||
27 | .endm | ||
28 | |||
29 | .macro busyuart,rd,rx @ spin while busy | ||
30 | 1001: ldr \rd, [\rx, #0x10] @ STATUS | ||
31 | tst \rd, #1 << 3 @ BUSY (TX FIFO not empty) | ||
32 | bne 1001b @ yes, spin | ||
33 | .endm | ||
34 | |||
35 | .macro waituart,rd,rx @ wait for Tx FIFO room | ||
36 | 1001: ldrb \rd, [\rx, #0x10] @ STATUS | ||
37 | tst \rd, #1 << 5 @ TXFF (TX FIFO full) | ||
38 | bne 1001b @ yes, spin | ||
39 | .endm | ||
diff --git a/arch/arm/mach-lh7a40x/include/mach/dma.h b/arch/arm/mach-lh7a40x/include/mach/dma.h new file mode 100644 index 000000000000..baa3f8dbd04b --- /dev/null +++ b/arch/arm/mach-lh7a40x/include/mach/dma.h | |||
@@ -0,0 +1,86 @@ | |||
1 | /* arch/arm/mach-lh7a40x/include/mach/dma.h | ||
2 | * | ||
3 | * Copyright (C) 2005 Marc Singer | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or | ||
6 | * modify it under the terms of the GNU General Public License | ||
7 | * version 2 as published by the Free Software Foundation. | ||
8 | * | ||
9 | */ | ||
10 | |||
11 | typedef enum { | ||
12 | DMA_M2M0 = 0, | ||
13 | DMA_M2M1 = 1, | ||
14 | DMA_M2P0 = 2, /* Tx */ | ||
15 | DMA_M2P1 = 3, /* Rx */ | ||
16 | DMA_M2P2 = 4, /* Tx */ | ||
17 | DMA_M2P3 = 5, /* Rx */ | ||
18 | DMA_M2P4 = 6, /* Tx - AC97 */ | ||
19 | DMA_M2P5 = 7, /* Rx - AC97 */ | ||
20 | DMA_M2P6 = 8, /* Tx */ | ||
21 | DMA_M2P7 = 9, /* Rx */ | ||
22 | } dma_device_t; | ||
23 | |||
24 | #define DMA_LENGTH_MAX ((64*1024) - 4) /* bytes */ | ||
25 | |||
26 | #define DMAC_GCA __REG(DMAC_PHYS + 0x2b80) | ||
27 | #define DMAC_GIR __REG(DMAC_PHYS + 0x2bc0) | ||
28 | |||
29 | #define DMAC_GIR_MMI1 (1<<11) | ||
30 | #define DMAC_GIR_MMI0 (1<<10) | ||
31 | #define DMAC_GIR_MPI8 (1<<9) | ||
32 | #define DMAC_GIR_MPI9 (1<<8) | ||
33 | #define DMAC_GIR_MPI6 (1<<7) | ||
34 | #define DMAC_GIR_MPI7 (1<<6) | ||
35 | #define DMAC_GIR_MPI4 (1<<5) | ||
36 | #define DMAC_GIR_MPI5 (1<<4) | ||
37 | #define DMAC_GIR_MPI2 (1<<3) | ||
38 | #define DMAC_GIR_MPI3 (1<<2) | ||
39 | #define DMAC_GIR_MPI0 (1<<1) | ||
40 | #define DMAC_GIR_MPI1 (1<<0) | ||
41 | |||
42 | #define DMAC_M2P0 0x0000 | ||
43 | #define DMAC_M2P1 0x0040 | ||
44 | #define DMAC_M2P2 0x0080 | ||
45 | #define DMAC_M2P3 0x00c0 | ||
46 | #define DMAC_M2P4 0x0240 | ||
47 | #define DMAC_M2P5 0x0200 | ||
48 | #define DMAC_M2P6 0x02c0 | ||
49 | #define DMAC_M2P7 0x0280 | ||
50 | #define DMAC_M2P8 0x0340 | ||
51 | #define DMAC_M2P9 0x0300 | ||
52 | #define DMAC_M2M0 0x0100 | ||
53 | #define DMAC_M2M1 0x0140 | ||
54 | |||
55 | #define DMAC_P_PCONTROL(c) __REG(DMAC_PHYS + (c) + 0x00) | ||
56 | #define DMAC_P_PINTERRUPT(c) __REG(DMAC_PHYS + (c) + 0x04) | ||
57 | #define DMAC_P_PPALLOC(c) __REG(DMAC_PHYS + (c) + 0x08) | ||
58 | #define DMAC_P_PSTATUS(c) __REG(DMAC_PHYS + (c) + 0x0c) | ||
59 | #define DMAC_P_REMAIN(c) __REG(DMAC_PHYS + (c) + 0x14) | ||
60 | #define DMAC_P_MAXCNT0(c) __REG(DMAC_PHYS + (c) + 0x20) | ||
61 | #define DMAC_P_BASE0(c) __REG(DMAC_PHYS + (c) + 0x24) | ||
62 | #define DMAC_P_CURRENT0(c) __REG(DMAC_PHYS + (c) + 0x28) | ||
63 | #define DMAC_P_MAXCNT1(c) __REG(DMAC_PHYS + (c) + 0x30) | ||
64 | #define DMAC_P_BASE1(c) __REG(DMAC_PHYS + (c) + 0x34) | ||
65 | #define DMAC_P_CURRENT1(c) __REG(DMAC_PHYS + (c) + 0x38) | ||
66 | |||
67 | #define DMAC_PCONTROL_ENABLE (1<<4) | ||
68 | |||
69 | #define DMAC_PORT_USB 0 | ||
70 | #define DMAC_PORT_SDMMC 1 | ||
71 | #define DMAC_PORT_AC97_1 2 | ||
72 | #define DMAC_PORT_AC97_2 3 | ||
73 | #define DMAC_PORT_AC97_3 4 | ||
74 | #define DMAC_PORT_UART1 6 | ||
75 | #define DMAC_PORT_UART2 7 | ||
76 | #define DMAC_PORT_UART3 8 | ||
77 | |||
78 | #define DMAC_PSTATUS_CURRSTATE_SHIFT 4 | ||
79 | #define DMAC_PSTATUS_CURRSTATE_MASK 0x3 | ||
80 | |||
81 | #define DMAC_PSTATUS_NEXTBUF (1<<6) | ||
82 | #define DMAC_PSTATUS_STALLRINT (1<<0) | ||
83 | |||
84 | #define DMAC_INT_CHE (1<<3) | ||
85 | #define DMAC_INT_NFB (1<<1) | ||
86 | #define DMAC_INT_STALL (1<<0) | ||
diff --git a/arch/arm/mach-lh7a40x/include/mach/entry-macro.S b/arch/arm/mach-lh7a40x/include/mach/entry-macro.S new file mode 100644 index 000000000000..069bb4cefff7 --- /dev/null +++ b/arch/arm/mach-lh7a40x/include/mach/entry-macro.S | |||
@@ -0,0 +1,149 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-lh7a40x/include/mach/entry-macro.S | ||
3 | * | ||
4 | * Low-level IRQ helper macros for LH7A40x platforms | ||
5 | * | ||
6 | * This file is licensed under the terms of the GNU General Public | ||
7 | * License version 2. This program is licensed "as is" without any | ||
8 | * warranty of any kind, whether express or implied. | ||
9 | */ | ||
10 | #include <mach/hardware.h> | ||
11 | #include <mach/irqs.h> | ||
12 | |||
13 | /* In order to allow there to be support for both of the processor | ||
14 | classes at the same time, we make a hack here that isn't very | ||
15 | pretty. At startup, the link pointed to with the | ||
16 | branch_irq_lh7a400 symbol is replaced with a NOP when the CPU is | ||
17 | detected as a lh7a404. | ||
18 | |||
19 | *** FIXME: we should clean this up so that there is only one | ||
20 | implementation for each CPU's design. | ||
21 | |||
22 | */ | ||
23 | |||
24 | #if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404) | ||
25 | |||
26 | .macro disable_fiq | ||
27 | .endm | ||
28 | |||
29 | .macro get_irqnr_preamble, base, tmp | ||
30 | .endm | ||
31 | |||
32 | .macro arch_ret_to_user, tmp1, tmp2 | ||
33 | .endm | ||
34 | |||
35 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
36 | |||
37 | branch_irq_lh7a400: b 1000f | ||
38 | |||
39 | @ Implementation of the LH7A404 get_irqnr_and_base. | ||
40 | |||
41 | mov \irqnr, #0 @ VIC1 irq base | ||
42 | mov \base, #io_p2v(0x80000000) @ APB registers | ||
43 | add \base, \base, #0x8000 | ||
44 | ldr \tmp, [\base, #0x0030] @ VIC1_VECTADDR | ||
45 | tst \tmp, #VA_VECTORED @ Direct vectored | ||
46 | bne 1002f | ||
47 | tst \tmp, #VA_VIC1DEFAULT @ Default vectored VIC1 | ||
48 | ldrne \irqstat, [\base, #0] @ VIC1_IRQSTATUS | ||
49 | bne 1001f | ||
50 | add \base, \base, #(0xa000 - 0x8000) | ||
51 | ldr \tmp, [\base, #0x0030] @ VIC2_VECTADDR | ||
52 | tst \tmp, #VA_VECTORED @ Direct vectored | ||
53 | bne 1002f | ||
54 | ldr \irqstat, [\base, #0] @ VIC2_IRQSTATUS | ||
55 | mov \irqnr, #32 @ VIC2 irq base | ||
56 | |||
57 | 1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry | ||
58 | bcs 1008f @ Bit set; irq found | ||
59 | add \irqnr, \irqnr, #1 | ||
60 | bne 1001b @ Until no bits | ||
61 | b 1009f @ Nothing? Hmm. | ||
62 | 1002: and \irqnr, \tmp, #0x3f @ Mask for valid bits | ||
63 | 1008: movs \irqstat, #1 @ Force !Z | ||
64 | str \tmp, [\base, #0x0030] @ Clear vector | ||
65 | b 1009f | ||
66 | |||
67 | @ Implementation of the LH7A400 get_irqnr_and_base. | ||
68 | |||
69 | 1000: mov \irqnr, #0 | ||
70 | mov \base, #io_p2v(0x80000000) @ APB registers | ||
71 | ldr \irqstat, [\base, #0x500] @ PIC INTSR | ||
72 | |||
73 | 1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry | ||
74 | bcs 1008f @ Bit set; irq found | ||
75 | add \irqnr, \irqnr, #1 | ||
76 | bne 1001b @ Until no bits | ||
77 | b 1009f @ Nothing? Hmm. | ||
78 | 1008: movs \irqstat, #1 @ Force !Z | ||
79 | |||
80 | 1009: | ||
81 | .endm | ||
82 | |||
83 | |||
84 | |||
85 | #elif defined (CONFIG_ARCH_LH7A400) | ||
86 | .macro disable_fiq | ||
87 | .endm | ||
88 | |||
89 | .macro get_irqnr_preamble, base, tmp | ||
90 | .endm | ||
91 | |||
92 | .macro arch_ret_to_user, tmp1, tmp2 | ||
93 | .endm | ||
94 | |||
95 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
96 | mov \irqnr, #0 | ||
97 | mov \base, #io_p2v(0x80000000) @ APB registers | ||
98 | ldr \irqstat, [\base, #0x500] @ PIC INTSR | ||
99 | |||
100 | 1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry | ||
101 | bcs 1008f @ Bit set; irq found | ||
102 | add \irqnr, \irqnr, #1 | ||
103 | bne 1001b @ Until no bits | ||
104 | b 1009f @ Nothing? Hmm. | ||
105 | 1008: movs \irqstat, #1 @ Force !Z | ||
106 | 1009: | ||
107 | .endm | ||
108 | |||
109 | #elif defined(CONFIG_ARCH_LH7A404) | ||
110 | |||
111 | .macro disable_fiq | ||
112 | .endm | ||
113 | |||
114 | .macro get_irqnr_preamble, base, tmp | ||
115 | .endm | ||
116 | |||
117 | .macro arch_ret_to_user, tmp1, tmp2 | ||
118 | .endm | ||
119 | |||
120 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
121 | mov \irqnr, #0 @ VIC1 irq base | ||
122 | mov \base, #io_p2v(0x80000000) @ APB registers | ||
123 | add \base, \base, #0x8000 | ||
124 | ldr \tmp, [\base, #0x0030] @ VIC1_VECTADDR | ||
125 | tst \tmp, #VA_VECTORED @ Direct vectored | ||
126 | bne 1002f | ||
127 | tst \tmp, #VA_VIC1DEFAULT @ Default vectored VIC1 | ||
128 | ldrne \irqstat, [\base, #0] @ VIC1_IRQSTATUS | ||
129 | bne 1001f | ||
130 | add \base, \base, #(0xa000 - 0x8000) | ||
131 | ldr \tmp, [\base, #0x0030] @ VIC2_VECTADDR | ||
132 | tst \tmp, #VA_VECTORED @ Direct vectored | ||
133 | bne 1002f | ||
134 | ldr \irqstat, [\base, #0] @ VIC2_IRQSTATUS | ||
135 | mov \irqnr, #32 @ VIC2 irq base | ||
136 | |||
137 | 1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry | ||
138 | bcs 1008f @ Bit set; irq found | ||
139 | add \irqnr, \irqnr, #1 | ||
140 | bne 1001b @ Until no bits | ||
141 | b 1009f @ Nothing? Hmm. | ||
142 | 1002: and \irqnr, \tmp, #0x3f @ Mask for valid bits | ||
143 | 1008: movs \irqstat, #1 @ Force !Z | ||
144 | str \tmp, [\base, #0x0030] @ Clear vector | ||
145 | 1009: | ||
146 | .endm | ||
147 | #endif | ||
148 | |||
149 | |||
diff --git a/arch/arm/mach-lh7a40x/include/mach/hardware.h b/arch/arm/mach-lh7a40x/include/mach/hardware.h new file mode 100644 index 000000000000..48e827d2fa56 --- /dev/null +++ b/arch/arm/mach-lh7a40x/include/mach/hardware.h | |||
@@ -0,0 +1,62 @@ | |||
1 | /* arch/arm/mach-lh7a40x/include/mach/hardware.h | ||
2 | * | ||
3 | * Copyright (C) 2004 Coastal Environmental Systems | ||
4 | * | ||
5 | * [ Substantially cribbed from arch/arm/mach-pxa/include/mach/hardware.h ] | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or | ||
8 | * modify it under the terms of the GNU General Public License | ||
9 | * version 2 as published by the Free Software Foundation. | ||
10 | * | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_HARDWARE_H | ||
14 | #define __ASM_ARCH_HARDWARE_H | ||
15 | |||
16 | #include <asm/sizes.h> /* Added for the sake of amba-clcd driver */ | ||
17 | |||
18 | #define io_p2v(x) (0xf0000000 | (((x) & 0xfff00000) >> 4) | ((x) & 0x0000ffff)) | ||
19 | #define io_v2p(x) ( (((x) & 0x0fff0000) << 4) | ((x) & 0x0000ffff)) | ||
20 | |||
21 | #ifdef __ASSEMBLY__ | ||
22 | |||
23 | # define __REG(x) io_p2v(x) | ||
24 | # define __PREG(x) io_v2p(x) | ||
25 | |||
26 | #else | ||
27 | |||
28 | # if 0 | ||
29 | # define __REG(x) (*((volatile u32 *)io_p2v(x))) | ||
30 | # else | ||
31 | /* | ||
32 | * This __REG() version gives the same results as the one above, except | ||
33 | * that we are fooling gcc somehow so it generates far better and smaller | ||
34 | * assembly code for access to contigous registers. It's a shame that gcc | ||
35 | * doesn't guess this by itself. | ||
36 | */ | ||
37 | #include <asm/types.h> | ||
38 | typedef struct { volatile u32 offset[4096]; } __regbase; | ||
39 | # define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2] | ||
40 | # define __REG(x) __REGP(io_p2v(x)) | ||
41 | typedef struct { volatile u16 offset[4096]; } __regbase16; | ||
42 | # define __REGP16(x) ((__regbase16 *)((x)&~4095))->offset[((x)&4095)>>1] | ||
43 | # define __REG16(x) __REGP16(io_p2v(x)) | ||
44 | typedef struct { volatile u8 offset[4096]; } __regbase8; | ||
45 | # define __REGP8(x) ((__regbase8 *)((x)&~4095))->offset[(x)&4095] | ||
46 | # define __REG8(x) __REGP8(io_p2v(x)) | ||
47 | #endif | ||
48 | |||
49 | /* Let's kick gcc's ass again... */ | ||
50 | # define __REG2(x,y) \ | ||
51 | ( __builtin_constant_p(y) ? (__REG((x) + (y))) \ | ||
52 | : (*(volatile u32 *)((u32)&__REG(x) + (y))) ) | ||
53 | |||
54 | # define __PREG(x) (io_v2p((u32)&(x))) | ||
55 | |||
56 | #endif | ||
57 | |||
58 | #define MASK_AND_SET(v,m,s) (v) = ((v)&~(m))|(s) | ||
59 | |||
60 | #include "registers.h" | ||
61 | |||
62 | #endif /* _ASM_ARCH_HARDWARE_H */ | ||
diff --git a/arch/arm/mach-lh7a40x/include/mach/io.h b/arch/arm/mach-lh7a40x/include/mach/io.h new file mode 100644 index 000000000000..031d26f9163c --- /dev/null +++ b/arch/arm/mach-lh7a40x/include/mach/io.h | |||
@@ -0,0 +1,22 @@ | |||
1 | /* arch/arm/mach-lh7a40x/include/mach/io.h | ||
2 | * | ||
3 | * Copyright (C) 2004 Coastal Environmental Systems | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or | ||
6 | * modify it under the terms of the GNU General Public License | ||
7 | * version 2 as published by the Free Software Foundation. | ||
8 | * | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_IO_H | ||
12 | #define __ASM_ARCH_IO_H | ||
13 | |||
14 | #include <mach/hardware.h> | ||
15 | |||
16 | #define IO_SPACE_LIMIT 0xffffffff | ||
17 | |||
18 | /* No ISA or PCI bus on this machine. */ | ||
19 | #define __io(a) ((void __iomem *)(a)) | ||
20 | #define __mem_pci(a) (a) | ||
21 | |||
22 | #endif /* __ASM_ARCH_IO_H */ | ||
diff --git a/arch/arm/mach-lh7a40x/include/mach/irqs.h b/arch/arm/mach-lh7a40x/include/mach/irqs.h new file mode 100644 index 000000000000..0f9b83675935 --- /dev/null +++ b/arch/arm/mach-lh7a40x/include/mach/irqs.h | |||
@@ -0,0 +1,200 @@ | |||
1 | /* arch/arm/mach-lh7a40x/include/mach/irqs.h | ||
2 | * | ||
3 | * Copyright (C) 2004 Coastal Environmental Systems | ||
4 | * Copyright (C) 2004 Logic Product Development | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License | ||
8 | * version 2 as published by the Free Software Foundation. | ||
9 | * | ||
10 | */ | ||
11 | |||
12 | /* It is to be seen whether or not we can build a kernel for more than | ||
13 | * one board. For the time being, these macros assume that we cannot. | ||
14 | * Thus, it is OK to ifdef machine/board specific IRQ assignments. | ||
15 | */ | ||
16 | |||
17 | |||
18 | #ifndef __ASM_ARCH_IRQS_H | ||
19 | #define __ASM_ARCH_IRQS_H | ||
20 | |||
21 | |||
22 | #define FIQ_START 80 | ||
23 | |||
24 | #if defined (CONFIG_ARCH_LH7A400) | ||
25 | |||
26 | /* FIQs */ | ||
27 | |||
28 | # define IRQ_GPIO0FIQ 0 /* GPIO External FIQ Interrupt on F0 */ | ||
29 | # define IRQ_BLINT 1 /* Battery Low */ | ||
30 | # define IRQ_WEINT 2 /* Watchdog Timer, WDT overflow */ | ||
31 | # define IRQ_MCINT 3 /* Media Change, MEDCHG pin rising */ | ||
32 | |||
33 | /* IRQs */ | ||
34 | |||
35 | # define IRQ_CSINT 4 /* Audio Codec (ACI) */ | ||
36 | # define IRQ_GPIO1INTR 5 /* GPIO External IRQ Interrupt on F1 */ | ||
37 | # define IRQ_GPIO2INTR 6 /* GPIO External IRQ Interrupt on F2 */ | ||
38 | # define IRQ_GPIO3INTR 7 /* GPIO External IRQ Interrupt on F3 */ | ||
39 | # define IRQ_T1UI 8 /* Timer 1 underflow */ | ||
40 | # define IRQ_T2UI 9 /* Timer 2 underflow */ | ||
41 | # define IRQ_RTCMI 10 | ||
42 | # define IRQ_TINTR 11 /* Clock State Controller 64 Hz tick (CSC) */ | ||
43 | # define IRQ_UART1INTR 12 | ||
44 | # define IRQ_UART2INTR 13 | ||
45 | # define IRQ_LCDINTR 14 | ||
46 | # define IRQ_SSIEOT 15 /* Synchronous Serial Interface (SSI) */ | ||
47 | # define IRQ_UART3INTR 16 | ||
48 | # define IRQ_SCIINTR 17 /* Smart Card Interface (SCI) */ | ||
49 | # define IRQ_AACINTR 18 /* Advanced Audio Codec (AAC) */ | ||
50 | # define IRQ_MMCINTR 19 /* Multimedia Card (MMC) */ | ||
51 | # define IRQ_USBINTR 20 | ||
52 | # define IRQ_DMAINTR 21 | ||
53 | # define IRQ_T3UI 22 /* Timer 3 underflow */ | ||
54 | # define IRQ_GPIO4INTR 23 /* GPIO External IRQ Interrupt on F4 */ | ||
55 | # define IRQ_GPIO5INTR 24 /* GPIO External IRQ Interrupt on F5 */ | ||
56 | # define IRQ_GPIO6INTR 25 /* GPIO External IRQ Interrupt on F6 */ | ||
57 | # define IRQ_GPIO7INTR 26 /* GPIO External IRQ Interrupt on F7 */ | ||
58 | # define IRQ_BMIINTR 27 /* Battery Monitor Interface (BMI) */ | ||
59 | |||
60 | # define NR_IRQ_CPU 28 /* IRQs directly recognized by CPU */ | ||
61 | |||
62 | /* Given IRQ, return GPIO interrupt number 0-7 */ | ||
63 | # define IRQ_TO_GPIO(i) ((i) \ | ||
64 | - (((i) > IRQ_GPIO3INTR) ? IRQ_GPIO4INTR - IRQ_GPIO3INTR - 1 : 0)\ | ||
65 | - (((i) > IRQ_GPIO0INTR) ? IRQ_GPIO1INTR - IRQ_GPIO0INTR - 1 : 0)) | ||
66 | |||
67 | #endif | ||
68 | |||
69 | #if defined (CONFIG_ARCH_LH7A404) | ||
70 | |||
71 | # define IRQ_BROWN 0 /* Brownout */ | ||
72 | # define IRQ_WDTINTR 1 /* Watchdog Timer */ | ||
73 | # define IRQ_COMMRX 2 /* ARM Comm Rx for Debug */ | ||
74 | # define IRQ_COMMTX 3 /* ARM Comm Tx for Debug */ | ||
75 | # define IRQ_T1UI 4 /* Timer 1 underflow */ | ||
76 | # define IRQ_T2UI 5 /* Timer 2 underflow */ | ||
77 | # define IRQ_CSINT 6 /* Codec Interrupt (shared by AAC on 404) */ | ||
78 | # define IRQ_DMAM2P0 7 /* -- DMA Memory to Peripheral */ | ||
79 | # define IRQ_DMAM2P1 8 | ||
80 | # define IRQ_DMAM2P2 9 | ||
81 | # define IRQ_DMAM2P3 10 | ||
82 | # define IRQ_DMAM2P4 11 | ||
83 | # define IRQ_DMAM2P5 12 | ||
84 | # define IRQ_DMAM2P6 13 | ||
85 | # define IRQ_DMAM2P7 14 | ||
86 | # define IRQ_DMAM2P8 15 | ||
87 | # define IRQ_DMAM2P9 16 | ||
88 | # define IRQ_DMAM2M0 17 /* -- DMA Memory to Memory */ | ||
89 | # define IRQ_DMAM2M1 18 | ||
90 | # define IRQ_GPIO0INTR 19 /* -- GPIOF Interrupt */ | ||
91 | # define IRQ_GPIO1INTR 20 | ||
92 | # define IRQ_GPIO2INTR 21 | ||
93 | # define IRQ_GPIO3INTR 22 | ||
94 | # define IRQ_SOFT_V1_23 23 /* -- Unassigned */ | ||
95 | # define IRQ_SOFT_V1_24 24 | ||
96 | # define IRQ_SOFT_V1_25 25 | ||
97 | # define IRQ_SOFT_V1_26 26 | ||
98 | # define IRQ_SOFT_V1_27 27 | ||
99 | # define IRQ_SOFT_V1_28 28 | ||
100 | # define IRQ_SOFT_V1_29 29 | ||
101 | # define IRQ_SOFT_V1_30 30 | ||
102 | # define IRQ_SOFT_V1_31 31 | ||
103 | |||
104 | # define IRQ_BLINT 32 /* Battery Low */ | ||
105 | # define IRQ_BMIINTR 33 /* Battery Monitor */ | ||
106 | # define IRQ_MCINTR 34 /* Media Change */ | ||
107 | # define IRQ_TINTR 35 /* 64Hz Tick */ | ||
108 | # define IRQ_WEINT 36 /* Watchdog Expired */ | ||
109 | # define IRQ_RTCMI 37 /* Real-time Clock Match */ | ||
110 | # define IRQ_UART1INTR 38 /* UART1 Interrupt (including error) */ | ||
111 | # define IRQ_UART1ERR 39 /* UART1 Error */ | ||
112 | # define IRQ_UART2INTR 40 /* UART2 Interrupt (including error) */ | ||
113 | # define IRQ_UART2ERR 41 /* UART2 Error */ | ||
114 | # define IRQ_UART3INTR 42 /* UART3 Interrupt (including error) */ | ||
115 | # define IRQ_UART3ERR 43 /* UART3 Error */ | ||
116 | # define IRQ_SCIINTR 44 /* Smart Card */ | ||
117 | # define IRQ_TSCINTR 45 /* Touchscreen */ | ||
118 | # define IRQ_KMIINTR 46 /* Keyboard/Mouse (PS/2) */ | ||
119 | # define IRQ_GPIO4INTR 47 /* -- GPIOF Interrupt */ | ||
120 | # define IRQ_GPIO5INTR 48 | ||
121 | # define IRQ_GPIO6INTR 49 | ||
122 | # define IRQ_GPIO7INTR 50 | ||
123 | # define IRQ_T3UI 51 /* Timer 3 underflow */ | ||
124 | # define IRQ_LCDINTR 52 /* LCD Controller */ | ||
125 | # define IRQ_SSPINTR 53 /* Synchronous Serial Port */ | ||
126 | # define IRQ_SDINTR 54 /* Secure Digital Port (MMC) */ | ||
127 | # define IRQ_USBINTR 55 /* USB Device Port */ | ||
128 | # define IRQ_USHINTR 56 /* USB Host Port */ | ||
129 | # define IRQ_SOFT_V2_25 57 /* -- Unassigned */ | ||
130 | # define IRQ_SOFT_V2_26 58 | ||
131 | # define IRQ_SOFT_V2_27 59 | ||
132 | # define IRQ_SOFT_V2_28 60 | ||
133 | # define IRQ_SOFT_V2_29 61 | ||
134 | # define IRQ_SOFT_V2_30 62 | ||
135 | # define IRQ_SOFT_V2_31 63 | ||
136 | |||
137 | # define NR_IRQ_CPU 64 /* IRQs directly recognized by CPU */ | ||
138 | |||
139 | /* Given IRQ, return GPIO interrupt number 0-7 */ | ||
140 | # define IRQ_TO_GPIO(i) ((i) \ | ||
141 | - (((i) > IRQ_GPIO3INTR) ? IRQ_GPIO4INTR - IRQ_GPIO3INTR - 1 : 0)\ | ||
142 | - IRQ_GPIO0INTR) | ||
143 | |||
144 | /* Vector Address constants */ | ||
145 | # define VA_VECTORED 0x100 /* Set for vectored interrupt */ | ||
146 | # define VA_VIC1DEFAULT 0x200 /* Set as default VECTADDR for VIC1 */ | ||
147 | # define VA_VIC2DEFAULT 0x400 /* Set as default VECTADDR for VIC2 */ | ||
148 | |||
149 | #endif | ||
150 | |||
151 | /* IRQ aliases */ | ||
152 | |||
153 | #if !defined (IRQ_GPIO0INTR) | ||
154 | # define IRQ_GPIO0INTR IRQ_GPIO0FIQ | ||
155 | #endif | ||
156 | #define IRQ_TICK IRQ_TINTR | ||
157 | #define IRQ_PCC1_RDY IRQ_GPIO6INTR /* PCCard 1 ready */ | ||
158 | #define IRQ_PCC2_RDY IRQ_GPIO7INTR /* PCCard 2 ready */ | ||
159 | #define IRQ_USB IRQ_USBINTR /* USB device */ | ||
160 | |||
161 | #ifdef CONFIG_MACH_KEV7A400 | ||
162 | # define IRQ_TS IRQ_GPIOFIQ /* Touchscreen */ | ||
163 | # define IRQ_CPLD IRQ_GPIO1INTR /* CPLD cascade */ | ||
164 | # define IRQ_PCC1_CD IRQ_GPIO_F2 /* PCCard 1 card detect */ | ||
165 | # define IRQ_PCC2_CD IRQ_GPIO_F3 /* PCCard 2 card detect */ | ||
166 | #endif | ||
167 | |||
168 | #if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) | ||
169 | # define IRQ_CPLD_V28 IRQ_GPIO7INTR /* CPLD cascade through GPIO_PF7 */ | ||
170 | # define IRQ_CPLD_V34 IRQ_GPIO3INTR /* CPLD cascade through GPIO_PF3 */ | ||
171 | #endif | ||
172 | |||
173 | /* System specific IRQs */ | ||
174 | |||
175 | #define IRQ_BOARD_START NR_IRQ_CPU | ||
176 | |||
177 | #ifdef CONFIG_MACH_KEV7A400 | ||
178 | # define IRQ_KEV7A400_CPLD IRQ_BOARD_START | ||
179 | # define NR_IRQ_BOARD 5 | ||
180 | # define IRQ_KEV7A400_MMC_CD IRQ_KEV7A400_CPLD + 0 /* MMC Card Detect */ | ||
181 | # define IRQ_KEV7A400_RI2 IRQ_KEV7A400_CPLD + 1 /* Ring Indicator 2 */ | ||
182 | # define IRQ_KEV7A400_IDE_CF IRQ_KEV7A400_CPLD + 2 /* Compact Flash (?) */ | ||
183 | # define IRQ_KEV7A400_ETH_INT IRQ_KEV7A400_CPLD + 3 /* Ethernet chip */ | ||
184 | # define IRQ_KEV7A400_INT IRQ_KEV7A400_CPLD + 4 | ||
185 | #endif | ||
186 | |||
187 | #if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) | ||
188 | # define IRQ_LPD7A40X_CPLD IRQ_BOARD_START | ||
189 | # define NR_IRQ_BOARD 2 | ||
190 | # define IRQ_LPD7A40X_ETH_INT IRQ_LPD7A40X_CPLD + 0 /* Ethernet chip */ | ||
191 | # define IRQ_LPD7A400_TS IRQ_LPD7A40X_CPLD + 1 /* Touch screen */ | ||
192 | #endif | ||
193 | |||
194 | #if defined (CONFIG_MACH_LPD7A400) | ||
195 | # define IRQ_TOUCH IRQ_LPD7A400_TS | ||
196 | #endif | ||
197 | |||
198 | #define NR_IRQS (NR_IRQ_CPU + NR_IRQ_BOARD) | ||
199 | |||
200 | #endif | ||
diff --git a/arch/arm/mach-lh7a40x/include/mach/memory.h b/arch/arm/mach-lh7a40x/include/mach/memory.h new file mode 100644 index 000000000000..f7107b4c197a --- /dev/null +++ b/arch/arm/mach-lh7a40x/include/mach/memory.h | |||
@@ -0,0 +1,76 @@ | |||
1 | /* arch/arm/mach-lh7a40x/include/mach/memory.h | ||
2 | * | ||
3 | * Copyright (C) 2004 Coastal Environmental Systems | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or | ||
6 | * modify it under the terms of the GNU General Public License | ||
7 | * version 2 as published by the Free Software Foundation. | ||
8 | * | ||
9 | * | ||
10 | * Refer to <file:Documentation/arm/Sharp-LH/SDRAM> for more information. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_MEMORY_H | ||
15 | #define __ASM_ARCH_MEMORY_H | ||
16 | |||
17 | /* | ||
18 | * Physical DRAM offset. | ||
19 | */ | ||
20 | #define PHYS_OFFSET UL(0xc0000000) | ||
21 | |||
22 | /* | ||
23 | * Virtual view <-> DMA view memory address translations | ||
24 | * virt_to_bus: Used to translate the virtual address to an | ||
25 | * address suitable to be passed to set_dma_addr | ||
26 | * bus_to_virt: Used to convert an address for DMA operations | ||
27 | * to an address that the kernel can use. | ||
28 | */ | ||
29 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
30 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
31 | |||
32 | #ifdef CONFIG_DISCONTIGMEM | ||
33 | |||
34 | /* | ||
35 | * Given a kernel address, find the home node of the underlying memory. | ||
36 | */ | ||
37 | |||
38 | # ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE | ||
39 | # define KVADDR_TO_NID(addr) \ | ||
40 | ( ((((unsigned long) (addr) - PAGE_OFFSET) >> 24) & 1)\ | ||
41 | | ((((unsigned long) (addr) - PAGE_OFFSET) >> 25) & ~1)) | ||
42 | # else /* 2 banks per node */ | ||
43 | # define KVADDR_TO_NID(addr) \ | ||
44 | (((unsigned long) (addr) - PAGE_OFFSET) >> 26) | ||
45 | # endif | ||
46 | |||
47 | /* | ||
48 | * Given a page frame number, convert it to a node id. | ||
49 | */ | ||
50 | |||
51 | # ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE | ||
52 | # define PFN_TO_NID(pfn) \ | ||
53 | (((((pfn) - PHYS_PFN_OFFSET) >> (24 - PAGE_SHIFT)) & 1)\ | ||
54 | | ((((pfn) - PHYS_PFN_OFFSET) >> (25 - PAGE_SHIFT)) & ~1)) | ||
55 | # else /* 2 banks per node */ | ||
56 | # define PFN_TO_NID(pfn) \ | ||
57 | (((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT)) | ||
58 | #endif | ||
59 | |||
60 | /* | ||
61 | * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory | ||
62 | * and returns the index corresponding to the appropriate page in the | ||
63 | * node's mem_map. | ||
64 | */ | ||
65 | |||
66 | # ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE | ||
67 | # define LOCAL_MAP_NR(addr) \ | ||
68 | (((unsigned long)(addr) & 0x003fffff) >> PAGE_SHIFT) | ||
69 | # else /* 2 banks per node */ | ||
70 | # define LOCAL_MAP_NR(addr) \ | ||
71 | (((unsigned long)(addr) & 0x01ffffff) >> PAGE_SHIFT) | ||
72 | # endif | ||
73 | |||
74 | #endif | ||
75 | |||
76 | #endif | ||
diff --git a/arch/arm/mach-lh7a40x/include/mach/registers.h b/arch/arm/mach-lh7a40x/include/mach/registers.h new file mode 100644 index 000000000000..ea44396383a7 --- /dev/null +++ b/arch/arm/mach-lh7a40x/include/mach/registers.h | |||
@@ -0,0 +1,224 @@ | |||
1 | /* arch/arm/mach-lh7a40x/include/mach/registers.h | ||
2 | * | ||
3 | * Copyright (C) 2004 Coastal Environmental Systems | ||
4 | * Copyright (C) 2004 Logic Product Development | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License | ||
8 | * version 2 as published by the Free Software Foundation. | ||
9 | * | ||
10 | */ | ||
11 | |||
12 | #include <mach/constants.h> | ||
13 | |||
14 | #ifndef __ASM_ARCH_REGISTERS_H | ||
15 | #define __ASM_ARCH_REGISTERS_H | ||
16 | |||
17 | |||
18 | /* Physical register base addresses */ | ||
19 | |||
20 | #define AC97C_PHYS (0x80000000) /* AC97 Controller */ | ||
21 | #define MMC_PHYS (0x80000100) /* Multimedia Card Controller */ | ||
22 | #define USB_PHYS (0x80000200) /* USB Client */ | ||
23 | #define SCI_PHYS (0x80000300) /* Secure Card Interface */ | ||
24 | #define CSC_PHYS (0x80000400) /* Clock/State Controller */ | ||
25 | #define INTC_PHYS (0x80000500) /* Interrupt Controller */ | ||
26 | #define UART1_PHYS (0x80000600) /* UART1 Controller */ | ||
27 | #define SIR_PHYS (0x80000600) /* IR Controller, same are UART1 */ | ||
28 | #define UART2_PHYS (0x80000700) /* UART2 Controller */ | ||
29 | #define UART3_PHYS (0x80000800) /* UART3 Controller */ | ||
30 | #define DCDC_PHYS (0x80000900) /* DC to DC Controller */ | ||
31 | #define ACI_PHYS (0x80000a00) /* Audio Codec Interface */ | ||
32 | #define SSP_PHYS (0x80000b00) /* Synchronous ... */ | ||
33 | #define TIMER_PHYS (0x80000c00) /* Timer Controller */ | ||
34 | #define RTC_PHYS (0x80000d00) /* Real-time Clock */ | ||
35 | #define GPIO_PHYS (0x80000e00) /* General Purpose IO */ | ||
36 | #define BMI_PHYS (0x80000f00) /* Battery Monitor Interface */ | ||
37 | #define HRTFTC_PHYS (0x80001000) /* High-res TFT Controller (LH7A400) */ | ||
38 | #define ALI_PHYS (0x80001000) /* Advanced LCD Interface (LH7A404) */ | ||
39 | #define WDT_PHYS (0x80001400) /* Watchdog Timer */ | ||
40 | #define SMC_PHYS (0x80002000) /* Static Memory Controller */ | ||
41 | #define SDRC_PHYS (0x80002400) /* SDRAM Controller */ | ||
42 | #define DMAC_PHYS (0x80002800) /* DMA Controller */ | ||
43 | #define CLCDC_PHYS (0x80003000) /* Color LCD Controller */ | ||
44 | |||
45 | /* Physical registers of the LH7A404 */ | ||
46 | |||
47 | #define ADC_PHYS (0x80001300) /* A/D & Touchscreen Controller */ | ||
48 | #define VIC1_PHYS (0x80008000) /* Vectored Interrupt Controller 1 */ | ||
49 | #define USBH_PHYS (0x80009000) /* USB OHCI host controller */ | ||
50 | #define VIC2_PHYS (0x8000a000) /* Vectored Interrupt Controller 2 */ | ||
51 | |||
52 | /*#define KBD_PHYS (0x80000e00) */ | ||
53 | /*#define LCDICP_PHYS (0x80001000) */ | ||
54 | |||
55 | |||
56 | /* Clock/State Controller register */ | ||
57 | |||
58 | #define CSC_PWRSR __REG(CSC_PHYS + 0x00) /* Reset register & ID */ | ||
59 | #define CSC_PWRCNT __REG(CSC_PHYS + 0x04) /* Power control */ | ||
60 | #define CSC_CLKSET __REG(CSC_PHYS + 0x20) /* Clock speed control */ | ||
61 | #define CSC_USBDRESET __REG(CSC_PHYS + 0x4c) /* USB Device resets */ | ||
62 | |||
63 | #define CSC_PWRCNT_USBH_EN (1<<28) /* USB Host power enable */ | ||
64 | #define CSC_PWRCNT_DMAC_M2M1_EN (1<<27) | ||
65 | #define CSC_PWRCNT_DMAC_M2M0_EN (1<<26) | ||
66 | #define CSC_PWRCNT_DMAC_M2P8_EN (1<<25) | ||
67 | #define CSC_PWRCNT_DMAC_M2P9_EN (1<<24) | ||
68 | #define CSC_PWRCNT_DMAC_M2P6_EN (1<<23) | ||
69 | #define CSC_PWRCNT_DMAC_M2P7_EN (1<<22) | ||
70 | #define CSC_PWRCNT_DMAC_M2P4_EN (1<<21) | ||
71 | #define CSC_PWRCNT_DMAC_M2P5_EN (1<<20) | ||
72 | #define CSC_PWRCNT_DMAC_M2P2_EN (1<<19) | ||
73 | #define CSC_PWRCNT_DMAC_M2P3_EN (1<<18) | ||
74 | #define CSC_PWRCNT_DMAC_M2P0_EN (1<<17) | ||
75 | #define CSC_PWRCNT_DMAC_M2P1_EN (1<<16) | ||
76 | |||
77 | #define CSC_PWRSR_CHIPMAN_SHIFT (24) | ||
78 | #define CSC_PWRSR_CHIPMAN_MASK (0xff) | ||
79 | #define CSC_PWRSR_CHIPID_SHIFT (16) | ||
80 | #define CSC_PWRSR_CHIPID_MASK (0xff) | ||
81 | |||
82 | #define CSC_USBDRESET_APBRESETREG (1<<1) | ||
83 | #define CSC_USBDRESET_IORESETREG (1<<0) | ||
84 | |||
85 | /* Interrupt Controller registers */ | ||
86 | |||
87 | #define INTC_INTSR __REG(INTC_PHYS + 0x00) /* Status */ | ||
88 | #define INTC_INTRSR __REG(INTC_PHYS + 0x04) /* Raw Status */ | ||
89 | #define INTC_INTENS __REG(INTC_PHYS + 0x08) /* Enable Set */ | ||
90 | #define INTC_INTENC __REG(INTC_PHYS + 0x0c) /* Enable Clear */ | ||
91 | |||
92 | |||
93 | /* Vectored Interrupted Controller registers */ | ||
94 | |||
95 | #define VIC1_IRQSTATUS __REG(VIC1_PHYS + 0x00) | ||
96 | #define VIC1_FIQSTATUS __REG(VIC1_PHYS + 0x04) | ||
97 | #define VIC1_RAWINTR __REG(VIC1_PHYS + 0x08) | ||
98 | #define VIC1_INTSEL __REG(VIC1_PHYS + 0x0c) | ||
99 | #define VIC1_INTEN __REG(VIC1_PHYS + 0x10) | ||
100 | #define VIC1_INTENCLR __REG(VIC1_PHYS + 0x14) | ||
101 | #define VIC1_SOFTINT __REG(VIC1_PHYS + 0x18) | ||
102 | #define VIC1_SOFTINTCLR __REG(VIC1_PHYS + 0x1c) | ||
103 | #define VIC1_PROTECT __REG(VIC1_PHYS + 0x20) | ||
104 | #define VIC1_VECTADDR __REG(VIC1_PHYS + 0x30) | ||
105 | #define VIC1_NVADDR __REG(VIC1_PHYS + 0x34) | ||
106 | #define VIC1_VAD0 __REG(VIC1_PHYS + 0x100) | ||
107 | #define VIC1_VECTCNTL0 __REG(VIC1_PHYS + 0x200) | ||
108 | #define VIC2_IRQSTATUS __REG(VIC2_PHYS + 0x00) | ||
109 | #define VIC2_FIQSTATUS __REG(VIC2_PHYS + 0x04) | ||
110 | #define VIC2_RAWINTR __REG(VIC2_PHYS + 0x08) | ||
111 | #define VIC2_INTSEL __REG(VIC2_PHYS + 0x0c) | ||
112 | #define VIC2_INTEN __REG(VIC2_PHYS + 0x10) | ||
113 | #define VIC2_INTENCLR __REG(VIC2_PHYS + 0x14) | ||
114 | #define VIC2_SOFTINT __REG(VIC2_PHYS + 0x18) | ||
115 | #define VIC2_SOFTINTCLR __REG(VIC2_PHYS + 0x1c) | ||
116 | #define VIC2_PROTECT __REG(VIC2_PHYS + 0x20) | ||
117 | #define VIC2_VECTADDR __REG(VIC2_PHYS + 0x30) | ||
118 | #define VIC2_NVADDR __REG(VIC2_PHYS + 0x34) | ||
119 | #define VIC2_VAD0 __REG(VIC2_PHYS + 0x100) | ||
120 | #define VIC2_VECTCNTL0 __REG(VIC2_PHYS + 0x200) | ||
121 | |||
122 | #define VIC_CNTL_ENABLE (0x20) | ||
123 | |||
124 | /* USB Host registers (Open HCI compatible) */ | ||
125 | |||
126 | #define USBH_CMDSTATUS __REG(USBH_PHYS + 0x08) | ||
127 | |||
128 | |||
129 | /* GPIO registers */ | ||
130 | |||
131 | #define GPIO_INTTYPE1 __REG(GPIO_PHYS + 0x4c) /* Interrupt Type 1 (Edge) */ | ||
132 | #define GPIO_INTTYPE2 __REG(GPIO_PHYS + 0x50) /* Interrupt Type 2 */ | ||
133 | #define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */ | ||
134 | #define GPIO_GPIOINTEN __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */ | ||
135 | #define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */ | ||
136 | #define GPIO_PINMUX __REG(GPIO_PHYS + 0x2c) | ||
137 | #define GPIO_PADD __REG(GPIO_PHYS + 0x10) | ||
138 | #define GPIO_PAD __REG(GPIO_PHYS + 0x00) | ||
139 | #define GPIO_PCD __REG(GPIO_PHYS + 0x08) | ||
140 | #define GPIO_PCDD __REG(GPIO_PHYS + 0x18) | ||
141 | #define GPIO_PEDD __REG(GPIO_PHYS + 0x24) | ||
142 | #define GPIO_PED __REG(GPIO_PHYS + 0x20) | ||
143 | |||
144 | |||
145 | /* Static Memory Controller registers */ | ||
146 | |||
147 | #define SMC_BCR0 __REG(SMC_PHYS + 0x00) /* Bank 0 Configuration */ | ||
148 | #define SMC_BCR1 __REG(SMC_PHYS + 0x04) /* Bank 1 Configuration */ | ||
149 | #define SMC_BCR2 __REG(SMC_PHYS + 0x08) /* Bank 2 Configuration */ | ||
150 | #define SMC_BCR3 __REG(SMC_PHYS + 0x0C) /* Bank 3 Configuration */ | ||
151 | #define SMC_BCR6 __REG(SMC_PHYS + 0x18) /* Bank 6 Configuration */ | ||
152 | #define SMC_BCR7 __REG(SMC_PHYS + 0x1c) /* Bank 7 Configuration */ | ||
153 | |||
154 | |||
155 | #ifdef CONFIG_MACH_KEV7A400 | ||
156 | # define CPLD_RD_OPT_DIP_SW __REG16(CPLD_PHYS + 0x00) /* Read Option SW */ | ||
157 | # define CPLD_WR_IO_BRD_CTL __REG16(CPLD_PHYS + 0x00) /* Write Control */ | ||
158 | # define CPLD_RD_PB_KEYS __REG16(CPLD_PHYS + 0x02) /* Read Btn Keys */ | ||
159 | # define CPLD_LATCHED_INTS __REG16(CPLD_PHYS + 0x04) /* Read INTR stat. */ | ||
160 | # define CPLD_CL_INT __REG16(CPLD_PHYS + 0x04) /* Clear INTR stat */ | ||
161 | # define CPLD_BOOT_MMC_STATUS __REG16(CPLD_PHYS + 0x06) /* R/O */ | ||
162 | # define CPLD_RD_KPD_ROW_SENSE __REG16(CPLD_PHYS + 0x08) | ||
163 | # define CPLD_WR_PB_INT_MASK __REG16(CPLD_PHYS + 0x08) | ||
164 | # define CPLD_RD_BRD_DISP_SW __REG16(CPLD_PHYS + 0x0a) | ||
165 | # define CPLD_WR_EXT_INT_MASK __REG16(CPLD_PHYS + 0x0a) | ||
166 | # define CPLD_LCD_PWR_CNTL __REG16(CPLD_PHYS + 0x0c) | ||
167 | # define CPLD_SEVEN_SEG __REG16(CPLD_PHYS + 0x0e) /* 7 seg. LED mask */ | ||
168 | |||
169 | #endif | ||
170 | |||
171 | #if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) | ||
172 | |||
173 | # define CPLD_CONTROL __REG16(CPLD02_PHYS) | ||
174 | # define CPLD_SPI_DATA __REG16(CPLD06_PHYS) | ||
175 | # define CPLD_SPI_CONTROL __REG16(CPLD08_PHYS) | ||
176 | # define CPLD_SPI_EEPROM __REG16(CPLD0A_PHYS) | ||
177 | # define CPLD_INTERRUPTS __REG16(CPLD0C_PHYS) /* IRQ mask/status */ | ||
178 | # define CPLD_BOOT_MODE __REG16(CPLD0E_PHYS) | ||
179 | # define CPLD_FLASH __REG16(CPLD10_PHYS) | ||
180 | # define CPLD_POWER_MGMT __REG16(CPLD12_PHYS) | ||
181 | # define CPLD_REVISION __REG16(CPLD14_PHYS) | ||
182 | # define CPLD_GPIO_EXT __REG16(CPLD16_PHYS) | ||
183 | # define CPLD_GPIO_DATA __REG16(CPLD18_PHYS) | ||
184 | # define CPLD_GPIO_DIR __REG16(CPLD1A_PHYS) | ||
185 | |||
186 | #endif | ||
187 | |||
188 | /* Timer registers */ | ||
189 | |||
190 | #define TIMER_LOAD1 __REG(TIMER_PHYS + 0x00) /* Timer 1 initial value */ | ||
191 | #define TIMER_VALUE1 __REG(TIMER_PHYS + 0x04) /* Timer 1 current value */ | ||
192 | #define TIMER_CONTROL1 __REG(TIMER_PHYS + 0x08) /* Timer 1 control word */ | ||
193 | #define TIMER_EOI1 __REG(TIMER_PHYS + 0x0c) /* Timer 1 interrupt clear */ | ||
194 | |||
195 | #define TIMER_LOAD2 __REG(TIMER_PHYS + 0x20) /* Timer 2 initial value */ | ||
196 | #define TIMER_VALUE2 __REG(TIMER_PHYS + 0x24) /* Timer 2 current value */ | ||
197 | #define TIMER_CONTROL2 __REG(TIMER_PHYS + 0x28) /* Timer 2 control word */ | ||
198 | #define TIMER_EOI2 __REG(TIMER_PHYS + 0x2c) /* Timer 2 interrupt clear */ | ||
199 | |||
200 | #define TIMER_BUZZCON __REG(TIMER_PHYS + 0x40) /* Buzzer configuration */ | ||
201 | |||
202 | #define TIMER_LOAD3 __REG(TIMER_PHYS + 0x80) /* Timer 3 initial value */ | ||
203 | #define TIMER_VALUE3 __REG(TIMER_PHYS + 0x84) /* Timer 3 current value */ | ||
204 | #define TIMER_CONTROL3 __REG(TIMER_PHYS + 0x88) /* Timer 3 control word */ | ||
205 | #define TIMER_EOI3 __REG(TIMER_PHYS + 0x8c) /* Timer 3 interrupt clear */ | ||
206 | |||
207 | #define TIMER_C_ENABLE (1<<7) | ||
208 | #define TIMER_C_PERIODIC (1<<6) | ||
209 | #define TIMER_C_FREERUNNING (0) | ||
210 | #define TIMER_C_2KHZ (0x00) /* 1.986 kHz */ | ||
211 | #define TIMER_C_508KHZ (0x08) | ||
212 | |||
213 | /* GPIO registers */ | ||
214 | |||
215 | #define GPIO_PFDD __REG(GPIO_PHYS + 0x34) /* PF direction */ | ||
216 | #define GPIO_INTTYPE1 __REG(GPIO_PHYS + 0x4c) /* IRQ edge or lvl */ | ||
217 | #define GPIO_INTTYPE2 __REG(GPIO_PHYS + 0x50) /* IRQ activ hi/lo */ | ||
218 | #define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIOF end of IRQ */ | ||
219 | #define GPIO_GPIOFINTEN __REG(GPIO_PHYS + 0x58) /* GPIOF IRQ enable */ | ||
220 | #define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIOF IRQ latch */ | ||
221 | #define GPIO_RAWINTSTATUS __REG(GPIO_PHYS + 0x60) /* GPIOF IRQ raw */ | ||
222 | |||
223 | |||
224 | #endif /* _ASM_ARCH_REGISTERS_H */ | ||
diff --git a/arch/arm/mach-lh7a40x/include/mach/ssp.h b/arch/arm/mach-lh7a40x/include/mach/ssp.h new file mode 100644 index 000000000000..132b1c4d5ce6 --- /dev/null +++ b/arch/arm/mach-lh7a40x/include/mach/ssp.h | |||
@@ -0,0 +1,71 @@ | |||
1 | /* ssp.h | ||
2 | $Id$ | ||
3 | |||
4 | written by Marc Singer | ||
5 | 6 Dec 2004 | ||
6 | |||
7 | Copyright (C) 2004 Marc Singer | ||
8 | |||
9 | ----------- | ||
10 | DESCRIPTION | ||
11 | ----------- | ||
12 | |||
13 | This SSP header is available throughout the kernel, for this | ||
14 | machine/architecture, because drivers that use it may be dispersed. | ||
15 | |||
16 | This file was cloned from the 7952x implementation. It would be | ||
17 | better to share them, but we're taking an easier approach for the | ||
18 | time being. | ||
19 | |||
20 | */ | ||
21 | |||
22 | #if !defined (__SSP_H__) | ||
23 | # define __SSP_H__ | ||
24 | |||
25 | /* ----- Includes */ | ||
26 | |||
27 | /* ----- Types */ | ||
28 | |||
29 | struct ssp_driver { | ||
30 | int (*init) (void); | ||
31 | void (*exit) (void); | ||
32 | void (*acquire) (void); | ||
33 | void (*release) (void); | ||
34 | int (*configure) (int device, int mode, int speed, | ||
35 | int frame_size_write, int frame_size_read); | ||
36 | void (*chip_select) (int enable); | ||
37 | void (*set_callbacks) (void* handle, | ||
38 | irqreturn_t (*callback_tx)(void*), | ||
39 | irqreturn_t (*callback_rx)(void*)); | ||
40 | void (*enable) (void); | ||
41 | void (*disable) (void); | ||
42 | // int (*save_state) (void*); | ||
43 | // void (*restore_state) (void*); | ||
44 | int (*read) (void); | ||
45 | int (*write) (u16 data); | ||
46 | int (*write_read) (u16 data); | ||
47 | void (*flush) (void); | ||
48 | void (*write_async) (void* pv, size_t cb); | ||
49 | size_t (*write_pos) (void); | ||
50 | }; | ||
51 | |||
52 | /* These modes are only available on the LH79524 */ | ||
53 | #define SSP_MODE_SPI (1) | ||
54 | #define SSP_MODE_SSI (2) | ||
55 | #define SSP_MODE_MICROWIRE (3) | ||
56 | #define SSP_MODE_I2S (4) | ||
57 | |||
58 | /* CPLD SPI devices */ | ||
59 | #define DEVICE_EEPROM 0 /* Configuration eeprom */ | ||
60 | #define DEVICE_MAC 1 /* MAC eeprom (LPD79524) */ | ||
61 | #define DEVICE_CODEC 2 /* Audio codec */ | ||
62 | #define DEVICE_TOUCH 3 /* Touch screen (LPD79520) */ | ||
63 | |||
64 | /* ----- Globals */ | ||
65 | |||
66 | /* ----- Prototypes */ | ||
67 | |||
68 | //extern struct ssp_driver lh79520_i2s_driver; | ||
69 | extern struct ssp_driver lh7a400_cpld_ssp_driver; | ||
70 | |||
71 | #endif /* __SSP_H__ */ | ||
diff --git a/arch/arm/mach-lh7a40x/include/mach/system.h b/arch/arm/mach-lh7a40x/include/mach/system.h new file mode 100644 index 000000000000..fa46bb1ef07b --- /dev/null +++ b/arch/arm/mach-lh7a40x/include/mach/system.h | |||
@@ -0,0 +1,19 @@ | |||
1 | /* arch/arm/mach-lh7a40x/include/mach/system.h | ||
2 | * | ||
3 | * Copyright (C) 2004 Coastal Environmental Systems | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or | ||
6 | * modify it under the terms of the GNU General Public License | ||
7 | * version 2 as published by the Free Software Foundation. | ||
8 | * | ||
9 | */ | ||
10 | |||
11 | static inline void arch_idle(void) | ||
12 | { | ||
13 | cpu_do_idle (); | ||
14 | } | ||
15 | |||
16 | static inline void arch_reset(char mode) | ||
17 | { | ||
18 | cpu_reset (0); | ||
19 | } | ||
diff --git a/arch/arm/mach-lh7a40x/include/mach/timex.h b/arch/arm/mach-lh7a40x/include/mach/timex.h new file mode 100644 index 000000000000..08028cef1b3b --- /dev/null +++ b/arch/arm/mach-lh7a40x/include/mach/timex.h | |||
@@ -0,0 +1,17 @@ | |||
1 | /* arch/arm/mach-lh7a40x/include/mach/timex.h | ||
2 | * | ||
3 | * Copyright (C) 2004 Coastal Environmental Systems | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or | ||
6 | * modify it under the terms of the GNU General Public License | ||
7 | * version 2 as published by the Free Software Foundation. | ||
8 | * | ||
9 | */ | ||
10 | |||
11 | #include <mach/constants.h> | ||
12 | |||
13 | #define CLOCK_TICK_RATE (PLL_CLOCK/6/16) | ||
14 | |||
15 | /* | ||
16 | #define CLOCK_TICK_RATE 3686400 | ||
17 | */ | ||
diff --git a/arch/arm/mach-lh7a40x/include/mach/uncompress.h b/arch/arm/mach-lh7a40x/include/mach/uncompress.h new file mode 100644 index 000000000000..55b80d479eb4 --- /dev/null +++ b/arch/arm/mach-lh7a40x/include/mach/uncompress.h | |||
@@ -0,0 +1,38 @@ | |||
1 | /* arch/arm/mach-lh7a40x/include/mach/uncompress.h | ||
2 | * | ||
3 | * Copyright (C) 2004 Coastal Environmental Systems | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or | ||
6 | * modify it under the terms of the GNU General Public License | ||
7 | * version 2 as published by the Free Software Foundation. | ||
8 | * | ||
9 | */ | ||
10 | |||
11 | #include <mach/registers.h> | ||
12 | |||
13 | #ifndef UART_R_DATA | ||
14 | # define UART_R_DATA (0x00) | ||
15 | #endif | ||
16 | #ifndef UART_R_STATUS | ||
17 | # define UART_R_STATUS (0x10) | ||
18 | #endif | ||
19 | #define nTxRdy (0x20) /* Not TxReady (literally Tx FIFO full) */ | ||
20 | |||
21 | /* Access UART with physical addresses before MMU is setup */ | ||
22 | #define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS)) | ||
23 | #define UART_DATA (*(volatile unsigned long*) (UART2_PHYS + UART_R_DATA)) | ||
24 | |||
25 | static inline void putc(int ch) | ||
26 | { | ||
27 | while (UART_STATUS & nTxRdy) | ||
28 | barrier(); | ||
29 | UART_DATA = ch; | ||
30 | } | ||
31 | |||
32 | static inline void flush(void) | ||
33 | { | ||
34 | } | ||
35 | |||
36 | /* NULL functions; we don't presently need them */ | ||
37 | #define arch_decomp_setup() | ||
38 | #define arch_decomp_wdog() | ||
diff --git a/arch/arm/mach-lh7a40x/include/mach/vmalloc.h b/arch/arm/mach-lh7a40x/include/mach/vmalloc.h new file mode 100644 index 000000000000..3fbd49490bb9 --- /dev/null +++ b/arch/arm/mach-lh7a40x/include/mach/vmalloc.h | |||
@@ -0,0 +1,10 @@ | |||
1 | /* arch/arm/mach-lh7a40x/include/mach/vmalloc.h | ||
2 | * | ||
3 | * Copyright (C) 2004 Coastal Environmental Systems | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or | ||
6 | * modify it under the terms of the GNU General Public License | ||
7 | * version 2 as published by the Free Software Foundation. | ||
8 | * | ||
9 | */ | ||
10 | #define VMALLOC_END (0xe8000000) | ||
diff --git a/arch/arm/mach-lh7a40x/irq-lh7a400.c b/arch/arm/mach-lh7a40x/irq-lh7a400.c index 9472bbebd8ab..1ad3afcf6b3d 100644 --- a/arch/arm/mach-lh7a40x/irq-lh7a400.c +++ b/arch/arm/mach-lh7a40x/irq-lh7a400.c | |||
@@ -12,10 +12,10 @@ | |||
12 | #include <linux/module.h> | 12 | #include <linux/module.h> |
13 | #include <linux/interrupt.h> | 13 | #include <linux/interrupt.h> |
14 | 14 | ||
15 | #include <asm/hardware.h> | 15 | #include <mach/hardware.h> |
16 | #include <asm/irq.h> | 16 | #include <asm/irq.h> |
17 | #include <asm/mach/irq.h> | 17 | #include <asm/mach/irq.h> |
18 | #include <asm/arch/irqs.h> | 18 | #include <mach/irqs.h> |
19 | 19 | ||
20 | #include "common.h" | 20 | #include "common.h" |
21 | 21 | ||
diff --git a/arch/arm/mach-lh7a40x/irq-lh7a404.c b/arch/arm/mach-lh7a40x/irq-lh7a404.c index 9b28389035e6..12b045b688c6 100644 --- a/arch/arm/mach-lh7a40x/irq-lh7a404.c +++ b/arch/arm/mach-lh7a40x/irq-lh7a404.c | |||
@@ -12,10 +12,10 @@ | |||
12 | #include <linux/module.h> | 12 | #include <linux/module.h> |
13 | #include <linux/interrupt.h> | 13 | #include <linux/interrupt.h> |
14 | 14 | ||
15 | #include <asm/hardware.h> | 15 | #include <mach/hardware.h> |
16 | #include <asm/irq.h> | 16 | #include <asm/irq.h> |
17 | #include <asm/mach/irq.h> | 17 | #include <asm/mach/irq.h> |
18 | #include <asm/arch/irqs.h> | 18 | #include <mach/irqs.h> |
19 | 19 | ||
20 | #include "common.h" | 20 | #include "common.h" |
21 | 21 | ||
diff --git a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c index 66e1ed3961ea..0d5063ebda10 100644 --- a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c +++ b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c | |||
@@ -13,10 +13,10 @@ | |||
13 | #include <linux/module.h> | 13 | #include <linux/module.h> |
14 | #include <linux/interrupt.h> | 14 | #include <linux/interrupt.h> |
15 | 15 | ||
16 | #include <asm/hardware.h> | 16 | #include <mach/hardware.h> |
17 | #include <asm/irq.h> | 17 | #include <asm/irq.h> |
18 | #include <asm/mach/irq.h> | 18 | #include <asm/mach/irq.h> |
19 | #include <asm/arch/irqs.h> | 19 | #include <mach/irqs.h> |
20 | 20 | ||
21 | #include "common.h" | 21 | #include "common.h" |
22 | 22 | ||
diff --git a/arch/arm/mach-lh7a40x/ssp-cpld.c b/arch/arm/mach-lh7a40x/ssp-cpld.c index a10830186dac..51fbef9601b9 100644 --- a/arch/arm/mach-lh7a40x/ssp-cpld.c +++ b/arch/arm/mach-lh7a40x/ssp-cpld.c | |||
@@ -46,9 +46,9 @@ | |||
46 | 46 | ||
47 | #include <asm/io.h> | 47 | #include <asm/io.h> |
48 | #include <asm/irq.h> | 48 | #include <asm/irq.h> |
49 | #include <asm/hardware.h> | 49 | #include <mach/hardware.h> |
50 | 50 | ||
51 | #include <asm/arch/ssp.h> | 51 | #include <mach/ssp.h> |
52 | 52 | ||
53 | //#define TALK | 53 | //#define TALK |
54 | 54 | ||
diff --git a/arch/arm/mach-lh7a40x/time.c b/arch/arm/mach-lh7a40x/time.c index e50e60b33851..7fe9e06cf662 100644 --- a/arch/arm/mach-lh7a40x/time.c +++ b/arch/arm/mach-lh7a40x/time.c | |||
@@ -14,7 +14,7 @@ | |||
14 | #include <linux/irq.h> | 14 | #include <linux/irq.h> |
15 | #include <linux/time.h> | 15 | #include <linux/time.h> |
16 | 16 | ||
17 | #include <asm/hardware.h> | 17 | #include <mach/hardware.h> |
18 | #include <asm/io.h> | 18 | #include <asm/io.h> |
19 | #include <asm/irq.h> | 19 | #include <asm/irq.h> |
20 | #include <asm/leds.h> | 20 | #include <asm/leds.h> |