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authorLennert Buytenhek <buytenh@wantstofly.org>2006-09-18 18:26:25 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-09-25 05:25:53 -0400
commitc852ac80440db9b0a47f48578e9c6303078abbc1 (patch)
tree0c7fc1ca7700b0196a20242ca306003db7e35fb6 /arch/arm/mach-iop33x
parent475549faa161f4e002225f2ef75fdd2a6d83d151 (diff)
[ARM] 3832/1: iop3xx: coding style cleanup
Since the iop32x code isn't iop321-specific, and the iop33x code isn't iop331-specfic, do a s/iop321/iop32x/ and s/iop331/iop33x/, and tidy up the code to conform to the coding style guidelines somewhat better. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-iop33x')
-rw-r--r--arch/arm/mach-iop33x/iq80331.c12
-rw-r--r--arch/arm/mach-iop33x/iq80332.c12
-rw-r--r--arch/arm/mach-iop33x/irq.c95
-rw-r--r--arch/arm/mach-iop33x/uart.c37
4 files changed, 73 insertions, 83 deletions
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
index 6b8475da3df6..97a7b7488264 100644
--- a/arch/arm/mach-iop33x/iq80331.c
+++ b/arch/arm/mach-iop33x/iq80331.c
@@ -61,19 +61,19 @@ iq80331_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
61 61
62 if (slot == 1 && pin == 1) { 62 if (slot == 1 && pin == 1) {
63 /* PCI-X Slot INTA */ 63 /* PCI-X Slot INTA */
64 irq = IRQ_IOP331_XINT1; 64 irq = IRQ_IOP33X_XINT1;
65 } else if (slot == 1 && pin == 2) { 65 } else if (slot == 1 && pin == 2) {
66 /* PCI-X Slot INTB */ 66 /* PCI-X Slot INTB */
67 irq = IRQ_IOP331_XINT2; 67 irq = IRQ_IOP33X_XINT2;
68 } else if (slot == 1 && pin == 3) { 68 } else if (slot == 1 && pin == 3) {
69 /* PCI-X Slot INTC */ 69 /* PCI-X Slot INTC */
70 irq = IRQ_IOP331_XINT3; 70 irq = IRQ_IOP33X_XINT3;
71 } else if (slot == 1 && pin == 4) { 71 } else if (slot == 1 && pin == 4) {
72 /* PCI-X Slot INTD */ 72 /* PCI-X Slot INTD */
73 irq = IRQ_IOP331_XINT0; 73 irq = IRQ_IOP33X_XINT0;
74 } else if (slot == 2) { 74 } else if (slot == 2) {
75 /* GigE */ 75 /* GigE */
76 irq = IRQ_IOP331_XINT2; 76 irq = IRQ_IOP33X_XINT2;
77 } else { 77 } else {
78 printk(KERN_ERR "iq80331_pci_map_irq() called for unknown " 78 printk(KERN_ERR "iq80331_pci_map_irq() called for unknown "
79 "device PCI:%d:%d:%d\n", dev->bus->number, 79 "device PCI:%d:%d:%d\n", dev->bus->number,
@@ -142,7 +142,7 @@ MACHINE_START(IQ80331, "Intel IQ80331")
142 .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc, 142 .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc,
143 .boot_params = 0x00000100, 143 .boot_params = 0x00000100,
144 .map_io = iop3xx_map_io, 144 .map_io = iop3xx_map_io,
145 .init_irq = iop331_init_irq, 145 .init_irq = iop33x_init_irq,
146 .timer = &iq80331_timer, 146 .timer = &iq80331_timer,
147 .init_machine = iq80331_init_machine, 147 .init_machine = iq80331_init_machine,
148MACHINE_END 148MACHINE_END
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
index 150f3fd5de0b..9887bfc1c078 100644
--- a/arch/arm/mach-iop33x/iq80332.c
+++ b/arch/arm/mach-iop33x/iq80332.c
@@ -61,19 +61,19 @@ iq80332_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
61 61
62 if (slot == 4 && pin == 1) { 62 if (slot == 4 && pin == 1) {
63 /* PCI-X Slot INTA */ 63 /* PCI-X Slot INTA */
64 irq = IRQ_IOP331_XINT0; 64 irq = IRQ_IOP33X_XINT0;
65 } else if (slot == 4 && pin == 2) { 65 } else if (slot == 4 && pin == 2) {
66 /* PCI-X Slot INTB */ 66 /* PCI-X Slot INTB */
67 irq = IRQ_IOP331_XINT1; 67 irq = IRQ_IOP33X_XINT1;
68 } else if (slot == 4 && pin == 3) { 68 } else if (slot == 4 && pin == 3) {
69 /* PCI-X Slot INTC */ 69 /* PCI-X Slot INTC */
70 irq = IRQ_IOP331_XINT2; 70 irq = IRQ_IOP33X_XINT2;
71 } else if (slot == 4 && pin == 4) { 71 } else if (slot == 4 && pin == 4) {
72 /* PCI-X Slot INTD */ 72 /* PCI-X Slot INTD */
73 irq = IRQ_IOP331_XINT3; 73 irq = IRQ_IOP33X_XINT3;
74 } else if (slot == 6) { 74 } else if (slot == 6) {
75 /* GigE */ 75 /* GigE */
76 irq = IRQ_IOP331_XINT2; 76 irq = IRQ_IOP33X_XINT2;
77 } else { 77 } else {
78 printk(KERN_ERR "iq80332_pci_map_irq() called for unknown " 78 printk(KERN_ERR "iq80332_pci_map_irq() called for unknown "
79 "device PCI:%d:%d:%d\n", dev->bus->number, 79 "device PCI:%d:%d:%d\n", dev->bus->number,
@@ -142,7 +142,7 @@ MACHINE_START(IQ80332, "Intel IQ80332")
142 .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc, 142 .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc,
143 .boot_params = 0x00000100, 143 .boot_params = 0x00000100,
144 .map_io = iop3xx_map_io, 144 .map_io = iop3xx_map_io,
145 .init_irq = iop331_init_irq, 145 .init_irq = iop33x_init_irq,
146 .timer = &iq80332_timer, 146 .timer = &iq80332_timer,
147 .init_machine = iq80332_init_machine, 147 .init_machine = iq80332_init_machine,
148MACHINE_END 148MACHINE_END
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c
index 3c720551ac12..63304b3d0d76 100644
--- a/arch/arm/mach-iop33x/irq.c
+++ b/arch/arm/mach-iop33x/irq.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-iop33x/irq.c 2 * arch/arm/mach-iop33x/irq.c
3 * 3 *
4 * Generic IOP331 IRQ handling functionality 4 * Generic IOP331 IRQ handling functionality
5 * 5 *
@@ -9,51 +9,44 @@
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 *
13 *
14 */ 12 */
13
15#include <linux/init.h> 14#include <linux/init.h>
16#include <linux/interrupt.h> 15#include <linux/interrupt.h>
17#include <linux/list.h> 16#include <linux/list.h>
18
19#include <asm/mach/irq.h> 17#include <asm/mach/irq.h>
20#include <asm/irq.h> 18#include <asm/irq.h>
21#include <asm/hardware.h> 19#include <asm/hardware.h>
22
23#include <asm/mach-types.h> 20#include <asm/mach-types.h>
24 21
25static u32 iop331_mask0 = 0; 22static u32 iop33x_mask0;
26static u32 iop331_mask1 = 0; 23static u32 iop33x_mask1;
27 24
28static inline void intctl_write0(u32 val) 25static inline void intctl0_write(u32 val)
29{ 26{
30 // INTCTL0
31 iop3xx_cp6_enable(); 27 iop3xx_cp6_enable();
32 asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val)); 28 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
33 iop3xx_cp6_disable(); 29 iop3xx_cp6_disable();
34} 30}
35 31
36static inline void intctl_write1(u32 val) 32static inline void intctl1_write(u32 val)
37{ 33{
38 // INTCTL1
39 iop3xx_cp6_enable(); 34 iop3xx_cp6_enable();
40 asm volatile("mcr p6,0,%0,c1,c0,0"::"r" (val)); 35 asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val));
41 iop3xx_cp6_disable(); 36 iop3xx_cp6_disable();
42} 37}
43 38
44static inline void intstr_write0(u32 val) 39static inline void intstr0_write(u32 val)
45{ 40{
46 // INTSTR0
47 iop3xx_cp6_enable(); 41 iop3xx_cp6_enable();
48 asm volatile("mcr p6,0,%0,c2,c0,0"::"r" (val)); 42 asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val));
49 iop3xx_cp6_disable(); 43 iop3xx_cp6_disable();
50} 44}
51 45
52static inline void intstr_write1(u32 val) 46static inline void intstr1_write(u32 val)
53{ 47{
54 // INTSTR1
55 iop3xx_cp6_enable(); 48 iop3xx_cp6_enable();
56 asm volatile("mcr p6,0,%0,c3,c0,0"::"r" (val)); 49 asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val));
57 iop3xx_cp6_disable(); 50 iop3xx_cp6_disable();
58} 51}
59 52
@@ -72,65 +65,63 @@ static inline void intsize_write(u32 val)
72} 65}
73 66
74static void 67static void
75iop331_irq_mask1 (unsigned int irq) 68iop33x_irq_mask1 (unsigned int irq)
76{ 69{
77 iop331_mask0 &= ~(1 << irq); 70 iop33x_mask0 &= ~(1 << irq);
78 intctl_write0(iop331_mask0); 71 intctl0_write(iop33x_mask0);
79} 72}
80 73
81static void 74static void
82iop331_irq_mask2 (unsigned int irq) 75iop33x_irq_mask2 (unsigned int irq)
83{ 76{
84 iop331_mask1 &= ~(1 << (irq - 32)); 77 iop33x_mask1 &= ~(1 << (irq - 32));
85 intctl_write1(iop331_mask1); 78 intctl1_write(iop33x_mask1);
86} 79}
87 80
88static void 81static void
89iop331_irq_unmask1(unsigned int irq) 82iop33x_irq_unmask1(unsigned int irq)
90{ 83{
91 iop331_mask0 |= (1 << irq); 84 iop33x_mask0 |= 1 << irq;
92 intctl_write0(iop331_mask0); 85 intctl0_write(iop33x_mask0);
93} 86}
94 87
95static void 88static void
96iop331_irq_unmask2(unsigned int irq) 89iop33x_irq_unmask2(unsigned int irq)
97{ 90{
98 iop331_mask1 |= (1 << (irq - 32)); 91 iop33x_mask1 |= (1 << (irq - 32));
99 intctl_write1(iop331_mask1); 92 intctl1_write(iop33x_mask1);
100} 93}
101 94
102struct irq_chip iop331_irqchip1 = { 95struct irq_chip iop33x_irqchip1 = {
103 .name = "IOP-1", 96 .name = "IOP33x-1",
104 .ack = iop331_irq_mask1, 97 .ack = iop33x_irq_mask1,
105 .mask = iop331_irq_mask1, 98 .mask = iop33x_irq_mask1,
106 .unmask = iop331_irq_unmask1, 99 .unmask = iop33x_irq_unmask1,
107}; 100};
108 101
109struct irq_chip iop331_irqchip2 = { 102struct irq_chip iop33x_irqchip2 = {
110 .name = "IOP-2", 103 .name = "IOP33x-2",
111 .ack = iop331_irq_mask2, 104 .ack = iop33x_irq_mask2,
112 .mask = iop331_irq_mask2, 105 .mask = iop33x_irq_mask2,
113 .unmask = iop331_irq_unmask2, 106 .unmask = iop33x_irq_unmask2,
114}; 107};
115 108
116void __init iop331_init_irq(void) 109void __init iop33x_init_irq(void)
117{ 110{
118 unsigned int i; 111 int i;
119 112
120 intctl_write0(0); // disable all interrupts 113 intctl0_write(0);
121 intctl_write1(0); 114 intctl1_write(0);
122 intstr_write0(0); // treat all as IRQ 115 intstr0_write(0);
123 intstr_write1(0); 116 intstr1_write(0);
124 intbase_write(0); 117 intbase_write(0);
125 intsize_write(1); 118 intsize_write(1);
126 if(machine_is_iq80331()) // all interrupts are inputs to chip 119 if (machine_is_iq80331())
127 *IOP3XX_PCIIRSR = 0x0f; 120 *IOP3XX_PCIIRSR = 0x0f;
128 121
129 for(i = 0; i < NR_IRQS; i++) 122 for (i = 0; i < NR_IRQS; i++) {
130 { 123 set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2);
131 set_irq_chip(i, (i < 32) ? &iop331_irqchip1 : &iop331_irqchip2);
132 set_irq_handler(i, do_level_IRQ); 124 set_irq_handler(i, do_level_IRQ);
133 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 125 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
134 } 126 }
135} 127}
136
diff --git a/arch/arm/mach-iop33x/uart.c b/arch/arm/mach-iop33x/uart.c
index d221d4abaa87..ac297cd0276c 100644
--- a/arch/arm/mach-iop33x/uart.c
+++ b/arch/arm/mach-iop33x/uart.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-iop33x/uart.c 2 * arch/arm/mach-iop33x/uart.c
3 * 3 *
4 * Author: Dave Jiang (dave.jiang@intel.com) 4 * Author: Dave Jiang (dave.jiang@intel.com)
5 * Copyright (C) 2004 Intel Corporation. 5 * Copyright (C) 2004 Intel Corporation.
@@ -17,7 +17,6 @@
17#include <linux/serial.h> 17#include <linux/serial.h>
18#include <linux/tty.h> 18#include <linux/tty.h>
19#include <linux/serial_8250.h> 19#include <linux/serial_8250.h>
20
21#include <asm/io.h> 20#include <asm/io.h>
22#include <asm/pgtable.h> 21#include <asm/pgtable.h>
23#include <asm/page.h> 22#include <asm/page.h>
@@ -30,14 +29,14 @@
30#include <asm/mach-types.h> 29#include <asm/mach-types.h>
31#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
32 31
33#define IOP331_UART_XTAL 33334000 32#define IOP33X_UART_XTAL 33334000
34 33
35static struct plat_serial8250_port iop33x_uart0_data[] = { 34static struct plat_serial8250_port iop33x_uart0_data[] = {
36 { 35 {
37 .membase = (char *)IOP331_UART0_VIRT, 36 .membase = (char *)IOP33X_UART0_VIRT,
38 .mapbase = IOP331_UART0_PHYS, 37 .mapbase = IOP33X_UART0_PHYS,
39 .irq = IRQ_IOP331_UART0, 38 .irq = IRQ_IOP33X_UART0,
40 .uartclk = IOP331_UART_XTAL, 39 .uartclk = IOP33X_UART_XTAL,
41 .regshift = 2, 40 .regshift = 2,
42 .iotype = UPIO_MEM, 41 .iotype = UPIO_MEM,
43 .flags = UPF_SKIP_TEST, 42 .flags = UPF_SKIP_TEST,
@@ -47,13 +46,13 @@ static struct plat_serial8250_port iop33x_uart0_data[] = {
47 46
48static struct resource iop33x_uart0_resources[] = { 47static struct resource iop33x_uart0_resources[] = {
49 [0] = { 48 [0] = {
50 .start = IOP331_UART0_PHYS, 49 .start = IOP33X_UART0_PHYS,
51 .end = IOP331_UART0_PHYS + 0x3f, 50 .end = IOP33X_UART0_PHYS + 0x3f,
52 .flags = IORESOURCE_MEM, 51 .flags = IORESOURCE_MEM,
53 }, 52 },
54 [1] = { 53 [1] = {
55 .start = IRQ_IOP331_UART0, 54 .start = IRQ_IOP33X_UART0,
56 .end = IRQ_IOP331_UART0, 55 .end = IRQ_IOP33X_UART0,
57 .flags = IORESOURCE_IRQ, 56 .flags = IORESOURCE_IRQ,
58 }, 57 },
59}; 58};
@@ -71,23 +70,23 @@ struct platform_device iop33x_uart0_device = {
71 70
72static struct resource iop33x_uart1_resources[] = { 71static struct resource iop33x_uart1_resources[] = {
73 [0] = { 72 [0] = {
74 .start = IOP331_UART1_PHYS, 73 .start = IOP33X_UART1_PHYS,
75 .end = IOP331_UART1_PHYS + 0x3f, 74 .end = IOP33X_UART1_PHYS + 0x3f,
76 .flags = IORESOURCE_MEM, 75 .flags = IORESOURCE_MEM,
77 }, 76 },
78 [1] = { 77 [1] = {
79 .start = IRQ_IOP331_UART1, 78 .start = IRQ_IOP33X_UART1,
80 .end = IRQ_IOP331_UART1, 79 .end = IRQ_IOP33X_UART1,
81 .flags = IORESOURCE_IRQ, 80 .flags = IORESOURCE_IRQ,
82 }, 81 },
83}; 82};
84 83
85static struct plat_serial8250_port iop33x_uart1_data[] = { 84static struct plat_serial8250_port iop33x_uart1_data[] = {
86 { 85 {
87 .membase = (char *)IOP331_UART1_VIRT, 86 .membase = (char *)IOP33X_UART1_VIRT,
88 .mapbase = IOP331_UART1_PHYS, 87 .mapbase = IOP33X_UART1_PHYS,
89 .irq = IRQ_IOP331_UART1, 88 .irq = IRQ_IOP33X_UART1,
90 .uartclk = IOP331_UART_XTAL, 89 .uartclk = IOP33X_UART_XTAL,
91 .regshift = 2, 90 .regshift = 2,
92 .iotype = UPIO_MEM, 91 .iotype = UPIO_MEM,
93 .flags = UPF_SKIP_TEST, 92 .flags = UPF_SKIP_TEST,