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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-08-05 11:14:15 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-08-07 04:55:48 -0400
commita09e64fbc0094e3073dbb09c3b4bfe4ab669244b (patch)
tree69689f467179891b498bd7423fcf61925173db31 /arch/arm/mach-iop13xx
parenta1b81a84fff05dbfef45b7012c26e1fee9973e5d (diff)
[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach
This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-iop13xx')
-rw-r--r--arch/arm/mach-iop13xx/include/mach/adma.h537
-rw-r--r--arch/arm/mach-iop13xx/include/mach/debug-macro.S26
-rw-r--r--arch/arm/mach-iop13xx/include/mach/dma.h3
-rw-r--r--arch/arm/mach-iop13xx/include/mach/entry-macro.S45
-rw-r--r--arch/arm/mach-iop13xx/include/mach/hardware.h28
-rw-r--r--arch/arm/mach-iop13xx/include/mach/io.h41
-rw-r--r--arch/arm/mach-iop13xx/include/mach/iop13xx.h526
-rw-r--r--arch/arm/mach-iop13xx/include/mach/iq81340.h28
-rw-r--r--arch/arm/mach-iop13xx/include/mach/irqs.h196
-rw-r--r--arch/arm/mach-iop13xx/include/mach/memory.h64
-rw-r--r--arch/arm/mach-iop13xx/include/mach/msi.h11
-rw-r--r--arch/arm/mach-iop13xx/include/mach/pci.h57
-rw-r--r--arch/arm/mach-iop13xx/include/mach/system.h27
-rw-r--r--arch/arm/mach-iop13xx/include/mach/time.h107
-rw-r--r--arch/arm/mach-iop13xx/include/mach/timex.h3
-rw-r--r--arch/arm/mach-iop13xx/include/mach/uncompress.h23
-rw-r--r--arch/arm/mach-iop13xx/include/mach/vmalloc.h4
-rw-r--r--arch/arm/mach-iop13xx/io.c2
-rw-r--r--arch/arm/mach-iop13xx/iq81340mc.c6
-rw-r--r--arch/arm/mach-iop13xx/iq81340sc.c6
-rw-r--r--arch/arm/mach-iop13xx/irq.c6
-rw-r--r--arch/arm/mach-iop13xx/pci.c4
-rw-r--r--arch/arm/mach-iop13xx/setup.c2
23 files changed, 1739 insertions, 13 deletions
diff --git a/arch/arm/mach-iop13xx/include/mach/adma.h b/arch/arm/mach-iop13xx/include/mach/adma.h
new file mode 100644
index 000000000000..60019c8e6465
--- /dev/null
+++ b/arch/arm/mach-iop13xx/include/mach/adma.h
@@ -0,0 +1,537 @@
1/*
2 * Copyright(c) 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
16 *
17 */
18#ifndef _ADMA_H
19#define _ADMA_H
20#include <linux/types.h>
21#include <linux/io.h>
22#include <mach/hardware.h>
23#include <asm/hardware/iop_adma.h>
24
25#define ADMA_ACCR(chan) (chan->mmr_base + 0x0)
26#define ADMA_ACSR(chan) (chan->mmr_base + 0x4)
27#define ADMA_ADAR(chan) (chan->mmr_base + 0x8)
28#define ADMA_IIPCR(chan) (chan->mmr_base + 0x18)
29#define ADMA_IIPAR(chan) (chan->mmr_base + 0x1c)
30#define ADMA_IIPUAR(chan) (chan->mmr_base + 0x20)
31#define ADMA_ANDAR(chan) (chan->mmr_base + 0x24)
32#define ADMA_ADCR(chan) (chan->mmr_base + 0x28)
33#define ADMA_CARMD(chan) (chan->mmr_base + 0x2c)
34#define ADMA_ABCR(chan) (chan->mmr_base + 0x30)
35#define ADMA_DLADR(chan) (chan->mmr_base + 0x34)
36#define ADMA_DUADR(chan) (chan->mmr_base + 0x38)
37#define ADMA_SLAR(src, chan) (chan->mmr_base + (0x3c + (src << 3)))
38#define ADMA_SUAR(src, chan) (chan->mmr_base + (0x40 + (src << 3)))
39
40struct iop13xx_adma_src {
41 u32 src_addr;
42 union {
43 u32 upper_src_addr;
44 struct {
45 unsigned int pq_upper_src_addr:24;
46 unsigned int pq_dmlt:8;
47 };
48 };
49};
50
51struct iop13xx_adma_desc_ctrl {
52 unsigned int int_en:1;
53 unsigned int xfer_dir:2;
54 unsigned int src_select:4;
55 unsigned int zero_result:1;
56 unsigned int block_fill_en:1;
57 unsigned int crc_gen_en:1;
58 unsigned int crc_xfer_dis:1;
59 unsigned int crc_seed_fetch_dis:1;
60 unsigned int status_write_back_en:1;
61 unsigned int endian_swap_en:1;
62 unsigned int reserved0:2;
63 unsigned int pq_update_xfer_en:1;
64 unsigned int dual_xor_en:1;
65 unsigned int pq_xfer_en:1;
66 unsigned int p_xfer_dis:1;
67 unsigned int reserved1:10;
68 unsigned int relax_order_en:1;
69 unsigned int no_snoop_en:1;
70};
71
72struct iop13xx_adma_byte_count {
73 unsigned int byte_count:24;
74 unsigned int host_if:3;
75 unsigned int reserved:2;
76 unsigned int zero_result_err_q:1;
77 unsigned int zero_result_err:1;
78 unsigned int tx_complete:1;
79};
80
81struct iop13xx_adma_desc_hw {
82 u32 next_desc;
83 union {
84 u32 desc_ctrl;
85 struct iop13xx_adma_desc_ctrl desc_ctrl_field;
86 };
87 union {
88 u32 crc_addr;
89 u32 block_fill_data;
90 u32 q_dest_addr;
91 };
92 union {
93 u32 byte_count;
94 struct iop13xx_adma_byte_count byte_count_field;
95 };
96 union {
97 u32 dest_addr;
98 u32 p_dest_addr;
99 };
100 union {
101 u32 upper_dest_addr;
102 u32 pq_upper_dest_addr;
103 };
104 struct iop13xx_adma_src src[1];
105};
106
107struct iop13xx_adma_desc_dual_xor {
108 u32 next_desc;
109 u32 desc_ctrl;
110 u32 reserved;
111 u32 byte_count;
112 u32 h_dest_addr;
113 u32 h_upper_dest_addr;
114 u32 src0_addr;
115 u32 upper_src0_addr;
116 u32 src1_addr;
117 u32 upper_src1_addr;
118 u32 h_src_addr;
119 u32 h_upper_src_addr;
120 u32 d_src_addr;
121 u32 d_upper_src_addr;
122 u32 d_dest_addr;
123 u32 d_upper_dest_addr;
124};
125
126struct iop13xx_adma_desc_pq_update {
127 u32 next_desc;
128 u32 desc_ctrl;
129 u32 reserved;
130 u32 byte_count;
131 u32 p_dest_addr;
132 u32 p_upper_dest_addr;
133 u32 src0_addr;
134 u32 upper_src0_addr;
135 u32 src1_addr;
136 u32 upper_src1_addr;
137 u32 p_src_addr;
138 u32 p_upper_src_addr;
139 u32 q_src_addr;
140 struct {
141 unsigned int q_upper_src_addr:24;
142 unsigned int q_dmlt:8;
143 };
144 u32 q_dest_addr;
145 u32 q_upper_dest_addr;
146};
147
148static inline int iop_adma_get_max_xor(void)
149{
150 return 16;
151}
152
153static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan)
154{
155 return __raw_readl(ADMA_ADAR(chan));
156}
157
158static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan,
159 u32 next_desc_addr)
160{
161 __raw_writel(next_desc_addr, ADMA_ANDAR(chan));
162}
163
164#define ADMA_STATUS_BUSY (1 << 13)
165
166static inline char iop_chan_is_busy(struct iop_adma_chan *chan)
167{
168 if (__raw_readl(ADMA_ACSR(chan)) &
169 ADMA_STATUS_BUSY)
170 return 1;
171 else
172 return 0;
173}
174
175static inline int
176iop_chan_get_desc_align(struct iop_adma_chan *chan, int num_slots)
177{
178 return 1;
179}
180#define iop_desc_is_aligned(x, y) 1
181
182static inline int
183iop_chan_memcpy_slot_count(size_t len, int *slots_per_op)
184{
185 *slots_per_op = 1;
186 return 1;
187}
188
189#define iop_chan_interrupt_slot_count(s, c) iop_chan_memcpy_slot_count(0, s)
190
191static inline int
192iop_chan_memset_slot_count(size_t len, int *slots_per_op)
193{
194 *slots_per_op = 1;
195 return 1;
196}
197
198static inline int
199iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op)
200{
201 static const char slot_count_table[] = { 1, 2, 2, 2,
202 2, 3, 3, 3,
203 3, 4, 4, 4,
204 4, 5, 5, 5,
205 };
206 *slots_per_op = slot_count_table[src_cnt - 1];
207 return *slots_per_op;
208}
209
210#define ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024)
211#define IOP_ADMA_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
212#define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
213#define IOP_ADMA_XOR_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
214#define iop_chan_zero_sum_slot_count(l, s, o) iop_chan_xor_slot_count(l, s, o)
215
216static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc,
217 struct iop_adma_chan *chan)
218{
219 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
220 return hw_desc->dest_addr;
221}
222
223static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc,
224 struct iop_adma_chan *chan)
225{
226 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
227 return hw_desc->byte_count_field.byte_count;
228}
229
230static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc,
231 struct iop_adma_chan *chan,
232 int src_idx)
233{
234 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
235 return hw_desc->src[src_idx].src_addr;
236}
237
238static inline u32 iop_desc_get_src_count(struct iop_adma_desc_slot *desc,
239 struct iop_adma_chan *chan)
240{
241 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
242 return hw_desc->desc_ctrl_field.src_select + 1;
243}
244
245static inline void
246iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, unsigned long flags)
247{
248 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
249 union {
250 u32 value;
251 struct iop13xx_adma_desc_ctrl field;
252 } u_desc_ctrl;
253
254 u_desc_ctrl.value = 0;
255 u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
256 u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
257 hw_desc->desc_ctrl = u_desc_ctrl.value;
258 hw_desc->crc_addr = 0;
259}
260
261static inline void
262iop_desc_init_memset(struct iop_adma_desc_slot *desc, unsigned long flags)
263{
264 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
265 union {
266 u32 value;
267 struct iop13xx_adma_desc_ctrl field;
268 } u_desc_ctrl;
269
270 u_desc_ctrl.value = 0;
271 u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
272 u_desc_ctrl.field.block_fill_en = 1;
273 u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
274 hw_desc->desc_ctrl = u_desc_ctrl.value;
275 hw_desc->crc_addr = 0;
276}
277
278/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */
279static inline void
280iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt,
281 unsigned long flags)
282{
283 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
284 union {
285 u32 value;
286 struct iop13xx_adma_desc_ctrl field;
287 } u_desc_ctrl;
288
289 u_desc_ctrl.value = 0;
290 u_desc_ctrl.field.src_select = src_cnt - 1;
291 u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
292 u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
293 hw_desc->desc_ctrl = u_desc_ctrl.value;
294 hw_desc->crc_addr = 0;
295
296}
297#define iop_desc_init_null_xor(d, s, i) iop_desc_init_xor(d, s, i)
298
299/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */
300static inline int
301iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt,
302 unsigned long flags)
303{
304 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
305 union {
306 u32 value;
307 struct iop13xx_adma_desc_ctrl field;
308 } u_desc_ctrl;
309
310 u_desc_ctrl.value = 0;
311 u_desc_ctrl.field.src_select = src_cnt - 1;
312 u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
313 u_desc_ctrl.field.zero_result = 1;
314 u_desc_ctrl.field.status_write_back_en = 1;
315 u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
316 hw_desc->desc_ctrl = u_desc_ctrl.value;
317 hw_desc->crc_addr = 0;
318
319 return 1;
320}
321
322static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc,
323 struct iop_adma_chan *chan,
324 u32 byte_count)
325{
326 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
327 hw_desc->byte_count = byte_count;
328}
329
330static inline void
331iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len)
332{
333 int slots_per_op = desc->slots_per_op;
334 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter;
335 int i = 0;
336
337 if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) {
338 hw_desc->byte_count = len;
339 } else {
340 do {
341 iter = iop_hw_desc_slot_idx(hw_desc, i);
342 iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
343 len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
344 i += slots_per_op;
345 } while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT);
346
347 if (len) {
348 iter = iop_hw_desc_slot_idx(hw_desc, i);
349 iter->byte_count = len;
350 }
351 }
352}
353
354
355static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc,
356 struct iop_adma_chan *chan,
357 dma_addr_t addr)
358{
359 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
360 hw_desc->dest_addr = addr;
361 hw_desc->upper_dest_addr = 0;
362}
363
364static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc,
365 dma_addr_t addr)
366{
367 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
368 hw_desc->src[0].src_addr = addr;
369 hw_desc->src[0].upper_src_addr = 0;
370}
371
372static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc,
373 int src_idx, dma_addr_t addr)
374{
375 int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
376 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter;
377 int i = 0;
378
379 do {
380 iter = iop_hw_desc_slot_idx(hw_desc, i);
381 iter->src[src_idx].src_addr = addr;
382 iter->src[src_idx].upper_src_addr = 0;
383 slot_cnt -= slots_per_op;
384 if (slot_cnt) {
385 i += slots_per_op;
386 addr += IOP_ADMA_XOR_MAX_BYTE_COUNT;
387 }
388 } while (slot_cnt);
389}
390
391static inline void
392iop_desc_init_interrupt(struct iop_adma_desc_slot *desc,
393 struct iop_adma_chan *chan)
394{
395 iop_desc_init_memcpy(desc, 1);
396 iop_desc_set_byte_count(desc, chan, 0);
397 iop_desc_set_dest_addr(desc, chan, 0);
398 iop_desc_set_memcpy_src_addr(desc, 0);
399}
400
401#define iop_desc_set_zero_sum_src_addr iop_desc_set_xor_src_addr
402
403static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc,
404 u32 next_desc_addr)
405{
406 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
407 BUG_ON(hw_desc->next_desc);
408 hw_desc->next_desc = next_desc_addr;
409}
410
411static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc)
412{
413 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
414 return hw_desc->next_desc;
415}
416
417static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc)
418{
419 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
420 hw_desc->next_desc = 0;
421}
422
423static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc,
424 u32 val)
425{
426 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
427 hw_desc->block_fill_data = val;
428}
429
430static inline int iop_desc_get_zero_result(struct iop_adma_desc_slot *desc)
431{
432 struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
433 struct iop13xx_adma_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field;
434 struct iop13xx_adma_byte_count byte_count = hw_desc->byte_count_field;
435
436 BUG_ON(!(byte_count.tx_complete && desc_ctrl.zero_result));
437
438 if (desc_ctrl.pq_xfer_en)
439 return byte_count.zero_result_err_q;
440 else
441 return byte_count.zero_result_err;
442}
443
444static inline void iop_chan_append(struct iop_adma_chan *chan)
445{
446 u32 adma_accr;
447
448 adma_accr = __raw_readl(ADMA_ACCR(chan));
449 adma_accr |= 0x2;
450 __raw_writel(adma_accr, ADMA_ACCR(chan));
451}
452
453static inline u32 iop_chan_get_status(struct iop_adma_chan *chan)
454{
455 return __raw_readl(ADMA_ACSR(chan));
456}
457
458static inline void iop_chan_disable(struct iop_adma_chan *chan)
459{
460 u32 adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan));
461 adma_chan_ctrl &= ~0x1;
462 __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan));
463}
464
465static inline void iop_chan_enable(struct iop_adma_chan *chan)
466{
467 u32 adma_chan_ctrl;
468
469 adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan));
470 adma_chan_ctrl |= 0x1;
471 __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan));
472}
473
474static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan)
475{
476 u32 status = __raw_readl(ADMA_ACSR(chan));
477 status &= (1 << 12);
478 __raw_writel(status, ADMA_ACSR(chan));
479}
480
481static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan)
482{
483 u32 status = __raw_readl(ADMA_ACSR(chan));
484 status &= (1 << 11);
485 __raw_writel(status, ADMA_ACSR(chan));
486}
487
488static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan)
489{
490 u32 status = __raw_readl(ADMA_ACSR(chan));
491 status &= (1 << 9) | (1 << 5) | (1 << 4) | (1 << 3);
492 __raw_writel(status, ADMA_ACSR(chan));
493}
494
495static inline int
496iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan)
497{
498 return test_bit(9, &status);
499}
500
501static inline int
502iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan)
503{
504 return test_bit(5, &status);
505}
506
507static inline int
508iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan)
509{
510 return test_bit(4, &status);
511}
512
513static inline int
514iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan)
515{
516 return test_bit(3, &status);
517}
518
519static inline int
520iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan)
521{
522 return 0;
523}
524
525static inline int
526iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan)
527{
528 return 0;
529}
530
531static inline int
532iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan)
533{
534 return 0;
535}
536
537#endif /* _ADMA_H */
diff --git a/arch/arm/mach-iop13xx/include/mach/debug-macro.S b/arch/arm/mach-iop13xx/include/mach/debug-macro.S
new file mode 100644
index 000000000000..9037d2e8557c
--- /dev/null
+++ b/arch/arm/mach-iop13xx/include/mach/debug-macro.S
@@ -0,0 +1,26 @@
1/*
2 * arch/arm/mach-iop13xx/include/mach/debug-macro.S
3 *
4 * Debugging macro include header
5 *
6 * Copyright (C) 1994-1999 Russell King
7 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 .macro addruart, rx
15 mrc p15, 0, \rx, c1, c0
16 tst \rx, #1 @ mmu enabled?
17 moveq \rx, #0xff000000 @ physical
18 orreq \rx, \rx, #0x00d80000
19 movne \rx, #0xfe000000 @ virtual
20 orrne \rx, \rx, #0x00e80000
21 orr \rx, \rx, #0x00002300
22 orr \rx, \rx, #0x00000040
23 .endm
24
25#define UART_SHIFT 2
26#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-iop13xx/include/mach/dma.h b/arch/arm/mach-iop13xx/include/mach/dma.h
new file mode 100644
index 000000000000..d79846fbb394
--- /dev/null
+++ b/arch/arm/mach-iop13xx/include/mach/dma.h
@@ -0,0 +1,3 @@
1#ifndef _IOP13XX_DMA_H
2#define _IOP13XX_DMA_H
3#endif
diff --git a/arch/arm/mach-iop13xx/include/mach/entry-macro.S b/arch/arm/mach-iop13xx/include/mach/entry-macro.S
new file mode 100644
index 000000000000..a624a7870c64
--- /dev/null
+++ b/arch/arm/mach-iop13xx/include/mach/entry-macro.S
@@ -0,0 +1,45 @@
1/*
2 * iop13xx low level irq macros
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19 .macro disable_fiq
20 .endm
21
22 .macro get_irqnr_preamble, base, tmp
23 mrc p15, 0, \tmp, c15, c1, 0
24 orr \tmp, \tmp, #(1 << 6)
25 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
26 .endm
27
28 /*
29 * Note: a 1-cycle window exists where iintvec will return the value
30 * of iintbase, so we explicitly check for "bad zeros"
31 */
32 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
33 mrc p6, 0, \irqnr, c3, c2, 0 @ Read IINTVEC
34 cmp \irqnr, #0
35 mrceq p6, 0, \irqnr, c3, c2, 0 @ Re-read on potentially bad zero
36 adds \irqstat, \irqnr, #1 @ Check for 0xffffffff
37 movne \irqnr, \irqnr, lsr #2 @ Convert to irqnr
38 .endm
39
40 .macro arch_ret_to_user, tmp1, tmp2
41 mrc p15, 0, \tmp1, c15, c1, 0
42 ands \tmp2, \tmp1, #(1 << 6)
43 bicne \tmp1, \tmp1, #(1 << 6)
44 mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
45 .endm
diff --git a/arch/arm/mach-iop13xx/include/mach/hardware.h b/arch/arm/mach-iop13xx/include/mach/hardware.h
new file mode 100644
index 000000000000..8e1d56289846
--- /dev/null
+++ b/arch/arm/mach-iop13xx/include/mach/hardware.h
@@ -0,0 +1,28 @@
1#ifndef __ASM_ARCH_HARDWARE_H
2#define __ASM_ARCH_HARDWARE_H
3#include <asm/types.h>
4
5#define pcibios_assign_all_busses() 1
6
7#ifndef __ASSEMBLY__
8extern unsigned long iop13xx_pcibios_min_io;
9extern unsigned long iop13xx_pcibios_min_mem;
10extern u16 iop13xx_dev_id(void);
11extern void iop13xx_set_atu_mmr_bases(void);
12#endif
13
14#define PCIBIOS_MIN_IO (iop13xx_pcibios_min_io)
15#define PCIBIOS_MIN_MEM (iop13xx_pcibios_min_mem)
16
17/*
18 * Generic chipset bits
19 *
20 */
21#include "iop13xx.h"
22
23/*
24 * Board specific bits
25 */
26#include "iq81340.h"
27
28#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-iop13xx/include/mach/io.h b/arch/arm/mach-iop13xx/include/mach/io.h
new file mode 100644
index 000000000000..a6e0f9e6ddcf
--- /dev/null
+++ b/arch/arm/mach-iop13xx/include/mach/io.h
@@ -0,0 +1,41 @@
1/*
2 * iop13xx custom ioremap implementation
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19#ifndef __ASM_ARM_ARCH_IO_H
20#define __ASM_ARM_ARCH_IO_H
21
22#define IO_SPACE_LIMIT 0xffffffff
23
24#define __io(a) __iop13xx_io(a)
25#define __mem_pci(a) (a)
26#define __mem_isa(a) (a)
27
28extern void __iomem * __iop13xx_io(unsigned long io_addr);
29extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size,
30 unsigned int mtype);
31extern void __iop13xx_iounmap(void __iomem *addr);
32
33extern u32 iop13xx_atue_mem_base;
34extern u32 iop13xx_atux_mem_base;
35extern size_t iop13xx_atue_mem_size;
36extern size_t iop13xx_atux_mem_size;
37
38#define __arch_ioremap(a, s, f) __iop13xx_ioremap(a, s, f)
39#define __arch_iounmap(a) __iop13xx_iounmap(a)
40
41#endif
diff --git a/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
new file mode 100644
index 000000000000..52b7fab7ef60
--- /dev/null
+++ b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
@@ -0,0 +1,526 @@
1#ifndef _IOP13XX_HW_H_
2#define _IOP13XX_HW_H_
3
4#ifndef __ASSEMBLY__
5/* The ATU offsets can change based on the strapping */
6extern u32 iop13xx_atux_pmmr_offset;
7extern u32 iop13xx_atue_pmmr_offset;
8void iop13xx_init_irq(void);
9void iop13xx_map_io(void);
10void iop13xx_platform_init(void);
11void iop13xx_add_tpmi_devices(void);
12void iop13xx_init_irq(void);
13
14/* CPUID CP6 R0 Page 0 */
15static inline int iop13xx_cpu_id(void)
16{
17 int id;
18 asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id));
19 return id;
20}
21
22/* WDTCR CP6 R7 Page 9 */
23static inline u32 read_wdtcr(void)
24{
25 u32 val;
26 asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
27 return val;
28}
29static inline void write_wdtcr(u32 val)
30{
31 asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
32}
33
34/* WDTSR CP6 R8 Page 9 */
35static inline u32 read_wdtsr(void)
36{
37 u32 val;
38 asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
39 return val;
40}
41static inline void write_wdtsr(u32 val)
42{
43 asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
44}
45
46/* RCSR - Reset Cause Status Register */
47static inline u32 read_rcsr(void)
48{
49 u32 val;
50 asm volatile("mrc p6, 0, %0, c0, c1, 0":"=r" (val));
51 return val;
52}
53
54extern unsigned long get_iop_tick_rate(void);
55#endif
56
57/*
58 * IOP13XX I/O and Mem space regions for PCI autoconfiguration
59 */
60#define IOP13XX_MAX_RAM_SIZE 0x80000000UL /* 2GB */
61#define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE
62
63/* PCI MAP
64 * bus range cpu phys cpu virt note
65 * 0x0000.0000 + 2GB (n/a) (n/a) inbound, 1:1 mapping with Physical RAM
66 * 0x8000.0000 + 928M 0x1.8000.0000 (ioremap) PCIX outbound memory window
67 * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window
68 *
69 * IO MAP
70 * 0x1000 + 64K 0x0.fffb.1000 0xfec6.1000 PCIX outbound i/o window
71 * 0x1000 + 64K 0x0.fffd.1000 0xfed7.1000 PCIE outbound i/o window
72 */
73#define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL
74#define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL
75#define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL
76#define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */
77#define IOP13XX_PCIX_IO_BUS_OFFSET 0x1000UL
78#define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\
79 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
80#define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\
81 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
82#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
83 (IOP13XX_PCIX_LOWER_IO_PA\
84 - IOP13XX_PCIX_LOWER_IO_VA))
85
86#define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL
87#define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL
88#define IOP13XX_PCIX_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
89#define IOP13XX_PCIX_LOWER_MEM_PA (IOP13XX_PCIX_MEM_PHYS_OFFSET +\
90 IOP13XX_PCIX_LOWER_MEM_BA)
91#define IOP13XX_PCIX_UPPER_MEM_PA (IOP13XX_PCIX_LOWER_MEM_PA +\
92 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
93#define IOP13XX_PCIX_UPPER_MEM_BA (IOP13XX_PCIX_LOWER_MEM_BA +\
94 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
95
96#define IOP13XX_PCIX_MEM_COOKIE 0x80000000UL
97#define IOP13XX_PCIX_LOWER_MEM_RA IOP13XX_PCIX_MEM_COOKIE
98#define IOP13XX_PCIX_UPPER_MEM_RA (IOP13XX_PCIX_LOWER_MEM_RA +\
99 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
100#define IOP13XX_PCIX_MEM_OFFSET (IOP13XX_PCIX_MEM_COOKIE -\
101 IOP13XX_PCIX_LOWER_MEM_BA)
102
103/* PCI-E ranges */
104#define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL
105#define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL
106#define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL
107#define IOP13XX_PCIE_LOWER_IO_BA 0x0UL /* OIOTVR */
108#define IOP13XX_PCIE_IO_BUS_OFFSET 0x1000UL
109#define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\
110 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
111#define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\
112 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
113#define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\
114 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
115#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
116 (IOP13XX_PCIE_LOWER_IO_PA\
117 - IOP13XX_PCIE_LOWER_IO_VA))
118
119#define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL
120#define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL
121#define IOP13XX_PCIE_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
122#define IOP13XX_PCIE_LOWER_MEM_PA (IOP13XX_PCIE_MEM_PHYS_OFFSET +\
123 IOP13XX_PCIE_LOWER_MEM_BA)
124#define IOP13XX_PCIE_UPPER_MEM_PA (IOP13XX_PCIE_LOWER_MEM_PA +\
125 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
126#define IOP13XX_PCIE_UPPER_MEM_BA (IOP13XX_PCIE_LOWER_MEM_BA +\
127 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
128
129/* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */
130#define IOP13XX_PCIE_MEM_COOKIE 0xc0000000UL
131#define IOP13XX_PCIE_LOWER_MEM_RA IOP13XX_PCIE_MEM_COOKIE
132#define IOP13XX_PCIE_UPPER_MEM_RA (IOP13XX_PCIE_LOWER_MEM_RA +\
133 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
134#define IOP13XX_PCIE_MEM_OFFSET (IOP13XX_PCIE_MEM_COOKIE -\
135 IOP13XX_PCIE_LOWER_MEM_BA)
136
137/* PBI Ranges */
138#define IOP13XX_PBI_LOWER_MEM_PA 0xf0000000UL
139#define IOP13XX_PBI_MEM_WINDOW_SIZE 0x04000000UL
140#define IOP13XX_PBI_MEM_COOKIE 0xfa000000UL
141#define IOP13XX_PBI_LOWER_MEM_RA IOP13XX_PBI_MEM_COOKIE
142#define IOP13XX_PBI_UPPER_MEM_RA (IOP13XX_PBI_LOWER_MEM_RA +\
143 IOP13XX_PBI_MEM_WINDOW_SIZE - 1)
144
145/*
146 * IOP13XX chipset registers
147 */
148#define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */
149#define IOP13XX_PMMR_VIRT_MEM_BASE 0xfee80000UL /* PMMR phys. address */
150#define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000
151#define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\
152 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
153#define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\
154 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
155#define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (u32) ((u32) addr +\
156 (IOP13XX_PMMR_PHYS_MEM_BASE\
157 - IOP13XX_PMMR_VIRT_MEM_BASE))
158#define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
159 (IOP13XX_PMMR_PHYS_MEM_BASE\
160 - IOP13XX_PMMR_VIRT_MEM_BASE))
161#define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
162#define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
163#define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
164#define IOP13XX_REG_ADDR32_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
165#define IOP13XX_REG_ADDR16_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
166#define IOP13XX_REG_ADDR8_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
167#define IOP13XX_PMMR_SIZE 0x00080000
168
169/*=================== Defines for Platform Devices =====================*/
170#define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300)
171#define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340)
172#define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300)
173#define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340)
174
175#define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
176#define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
177#define IOP13XX_I2C2_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540)
178#define IOP13XX_I2C0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500)
179#define IOP13XX_I2C1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520)
180#define IOP13XX_I2C2_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540)
181
182/* ATU selection flags */
183/* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */
184#define IOP13XX_INIT_ATU_DEFAULT (0)
185#define IOP13XX_INIT_ATU_ATUX (1 << 0)
186#define IOP13XX_INIT_ATU_ATUE (1 << 1)
187#define IOP13XX_INIT_ATU_NONE (1 << 2)
188
189/* UART selection flags */
190/* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */
191#define IOP13XX_INIT_UART_DEFAULT (0)
192#define IOP13XX_INIT_UART_0 (1 << 0)
193#define IOP13XX_INIT_UART_1 (1 << 1)
194
195/* I2C selection flags */
196/* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */
197#define IOP13XX_INIT_I2C_DEFAULT (0)
198#define IOP13XX_INIT_I2C_0 (1 << 0)
199#define IOP13XX_INIT_I2C_1 (1 << 1)
200#define IOP13XX_INIT_I2C_2 (1 << 2)
201
202/* ADMA selection flags */
203/* INIT_ADMA_DEFAULT = Rely on CONFIG_IOP13XX_ADMA* */
204#define IOP13XX_INIT_ADMA_DEFAULT (0)
205#define IOP13XX_INIT_ADMA_0 (1 << 0)
206#define IOP13XX_INIT_ADMA_1 (1 << 1)
207#define IOP13XX_INIT_ADMA_2 (1 << 2)
208
209/* Platform devices */
210#define IQ81340_NUM_UART 2
211#define IQ81340_NUM_I2C 3
212#define IQ81340_NUM_PHYS_MAP_FLASH 1
213#define IQ81340_NUM_ADMA 3
214#define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART + \
215 IQ81340_NUM_I2C + \
216 IQ81340_NUM_PHYS_MAP_FLASH + \
217 IQ81340_NUM_ADMA)
218
219/*========================== PMMR offsets for key registers ============*/
220#define IOP13XX_ATU0_PMMR_OFFSET 0x00048000
221#define IOP13XX_ATU1_PMMR_OFFSET 0x0004c000
222#define IOP13XX_ATU2_PMMR_OFFSET 0x0004d000
223#define IOP13XX_ADMA0_PMMR_OFFSET 0x00000000
224#define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200
225#define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400
226#define IOP13XX_PBI_PMMR_OFFSET 0x00001580
227#define IOP13XX_MU_PMMR_OFFSET 0x00004000
228#define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188
229#define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188)
230
231#define IOP13XX_ESSR0_IFACE_MASK 0x00004000 /* Interface PCI-X / PCI-E */
232#define IOP13XX_CONTROLLER_ONLY (1 << 14)
233#define IOP13XX_INTERFACE_SEL_PCIX (1 << 15)
234
235#define IOP13XX_PMON_PMMR_OFFSET 0x0001A000
236#define IOP13XX_PMON_BASE (IOP13XX_PMMR_VIRT_MEM_BASE +\
237 IOP13XX_PMON_PMMR_OFFSET)
238#define IOP13XX_PMON_PHYSBASE (IOP13XX_PMMR_PHYS_MEM_BASE +\
239 IOP13XX_PMON_PMMR_OFFSET)
240
241#define IOP13XX_PMON_CMD0 (IOP13XX_PMON_BASE + 0x0)
242#define IOP13XX_PMON_EVR0 (IOP13XX_PMON_BASE + 0x4)
243#define IOP13XX_PMON_STS0 (IOP13XX_PMON_BASE + 0x8)
244#define IOP13XX_PMON_DATA0 (IOP13XX_PMON_BASE + 0xC)
245
246#define IOP13XX_PMON_CMD3 (IOP13XX_PMON_BASE + 0x30)
247#define IOP13XX_PMON_EVR3 (IOP13XX_PMON_BASE + 0x34)
248#define IOP13XX_PMON_STS3 (IOP13XX_PMON_BASE + 0x38)
249#define IOP13XX_PMON_DATA3 (IOP13XX_PMON_BASE + 0x3C)
250
251#define IOP13XX_PMON_CMD7 (IOP13XX_PMON_BASE + 0x70)
252#define IOP13XX_PMON_EVR7 (IOP13XX_PMON_BASE + 0x74)
253#define IOP13XX_PMON_STS7 (IOP13XX_PMON_BASE + 0x78)
254#define IOP13XX_PMON_DATA7 (IOP13XX_PMON_BASE + 0x7C)
255
256#define IOP13XX_PMONEN (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040)
257#define IOP13XX_PMONSTAT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044)
258
259/*================================ATU===================================*/
260#define IOP13XX_ATUX_OFFSET(ofs) IOP13XX_REG_ADDR32(\
261 iop13xx_atux_pmmr_offset + (ofs))
262
263#define IOP13XX_ATUX_DID IOP13XX_REG_ADDR16(\
264 iop13xx_atux_pmmr_offset + 0x2)
265
266#define IOP13XX_ATUX_ATUCMD IOP13XX_REG_ADDR16(\
267 iop13xx_atux_pmmr_offset + 0x4)
268#define IOP13XX_ATUX_ATUSR IOP13XX_REG_ADDR16(\
269 iop13xx_atux_pmmr_offset + 0x6)
270
271#define IOP13XX_ATUX_IABAR0 IOP13XX_ATUX_OFFSET(0x10)
272#define IOP13XX_ATUX_IAUBAR0 IOP13XX_ATUX_OFFSET(0x14)
273#define IOP13XX_ATUX_IABAR1 IOP13XX_ATUX_OFFSET(0x18)
274#define IOP13XX_ATUX_IAUBAR1 IOP13XX_ATUX_OFFSET(0x1c)
275#define IOP13XX_ATUX_IABAR2 IOP13XX_ATUX_OFFSET(0x20)
276#define IOP13XX_ATUX_IAUBAR2 IOP13XX_ATUX_OFFSET(0x24)
277#define IOP13XX_ATUX_IALR0 IOP13XX_ATUX_OFFSET(0x40)
278#define IOP13XX_ATUX_IATVR0 IOP13XX_ATUX_OFFSET(0x44)
279#define IOP13XX_ATUX_IAUTVR0 IOP13XX_ATUX_OFFSET(0x48)
280#define IOP13XX_ATUX_IALR1 IOP13XX_ATUX_OFFSET(0x4c)
281#define IOP13XX_ATUX_IATVR1 IOP13XX_ATUX_OFFSET(0x50)
282#define IOP13XX_ATUX_IAUTVR1 IOP13XX_ATUX_OFFSET(0x54)
283#define IOP13XX_ATUX_IALR2 IOP13XX_ATUX_OFFSET(0x58)
284#define IOP13XX_ATUX_IATVR2 IOP13XX_ATUX_OFFSET(0x5c)
285#define IOP13XX_ATUX_IAUTVR2 IOP13XX_ATUX_OFFSET(0x60)
286#define IOP13XX_ATUX_ATUCR IOP13XX_ATUX_OFFSET(0x70)
287#define IOP13XX_ATUX_PCSR IOP13XX_ATUX_OFFSET(0x74)
288#define IOP13XX_ATUX_ATUISR IOP13XX_ATUX_OFFSET(0x78)
289#define IOP13XX_ATUX_PCIXSR IOP13XX_ATUX_OFFSET(0xD4)
290#define IOP13XX_ATUX_IABAR3 IOP13XX_ATUX_OFFSET(0x200)
291#define IOP13XX_ATUX_IAUBAR3 IOP13XX_ATUX_OFFSET(0x204)
292#define IOP13XX_ATUX_IALR3 IOP13XX_ATUX_OFFSET(0x208)
293#define IOP13XX_ATUX_IATVR3 IOP13XX_ATUX_OFFSET(0x20c)
294#define IOP13XX_ATUX_IAUTVR3 IOP13XX_ATUX_OFFSET(0x210)
295
296#define IOP13XX_ATUX_OIOBAR IOP13XX_ATUX_OFFSET(0x300)
297#define IOP13XX_ATUX_OIOWTVR IOP13XX_ATUX_OFFSET(0x304)
298#define IOP13XX_ATUX_OUMBAR0 IOP13XX_ATUX_OFFSET(0x308)
299#define IOP13XX_ATUX_OUMWTVR0 IOP13XX_ATUX_OFFSET(0x30c)
300#define IOP13XX_ATUX_OUMBAR1 IOP13XX_ATUX_OFFSET(0x310)
301#define IOP13XX_ATUX_OUMWTVR1 IOP13XX_ATUX_OFFSET(0x314)
302#define IOP13XX_ATUX_OUMBAR2 IOP13XX_ATUX_OFFSET(0x318)
303#define IOP13XX_ATUX_OUMWTVR2 IOP13XX_ATUX_OFFSET(0x31c)
304#define IOP13XX_ATUX_OUMBAR3 IOP13XX_ATUX_OFFSET(0x320)
305#define IOP13XX_ATUX_OUMWTVR3 IOP13XX_ATUX_OFFSET(0x324)
306#define IOP13XX_ATUX_OUDMABAR IOP13XX_ATUX_OFFSET(0x328)
307#define IOP13XX_ATUX_OUMSIBAR IOP13XX_ATUX_OFFSET(0x32c)
308#define IOP13XX_ATUX_OCCAR IOP13XX_ATUX_OFFSET(0x330)
309#define IOP13XX_ATUX_OCCDR IOP13XX_ATUX_OFFSET(0x334)
310
311#define IOP13XX_ATUX_ATUCR_OUT_EN (1 << 1)
312#define IOP13XX_ATUX_PCSR_CENTRAL_RES (1 << 25)
313#define IOP13XX_ATUX_PCSR_P_RSTOUT (1 << 21)
314#define IOP13XX_ATUX_PCSR_OUT_Q_BUSY (1 << 15)
315#define IOP13XX_ATUX_PCSR_IN_Q_BUSY (1 << 14)
316#define IOP13XX_ATUX_PCSR_FREQ_OFFSET (16)
317
318#define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18)
319#define IOP13XX_ATUX_STAT_VPD_ADDR (1 << 17)
320#define IOP13XX_ATUX_STAT_INT_PAR_ERR (1 << 16)
321#define IOP13XX_ATUX_STAT_CFG_WRITE (1 << 15)
322#define IOP13XX_ATUX_STAT_ERR_COR (1 << 14)
323#define IOP13XX_ATUX_STAT_TX_SCEM (1 << 13)
324#define IOP13XX_ATUX_STAT_REC_SCEM (1 << 12)
325#define IOP13XX_ATUX_STAT_POWER_TRAN (1 << 11)
326#define IOP13XX_ATUX_STAT_TX_SERR (1 << 10)
327#define IOP13XX_ATUX_STAT_DET_PAR_ERR (1 << 9 )
328#define IOP13XX_ATUX_STAT_BIST (1 << 8 )
329#define IOP13XX_ATUX_STAT_INT_REC_MABORT (1 << 7 )
330#define IOP13XX_ATUX_STAT_REC_SERR (1 << 4 )
331#define IOP13XX_ATUX_STAT_EXT_REC_MABORT (1 << 3 )
332#define IOP13XX_ATUX_STAT_EXT_REC_TABORT (1 << 2 )
333#define IOP13XX_ATUX_STAT_EXT_SIG_TABORT (1 << 1 )
334#define IOP13XX_ATUX_STAT_MASTER_DATA_PAR (1 << 0 )
335
336#define IOP13XX_ATUX_PCIXSR_BUS_NUM (8)
337#define IOP13XX_ATUX_PCIXSR_DEV_NUM (3)
338#define IOP13XX_ATUX_PCIXSR_FUNC_NUM (0)
339
340#define IOP13XX_ATUX_IALR_DISABLE 0x00000001
341#define IOP13XX_ATUX_OUMBAR_ENABLE 0x80000000
342
343#define IOP13XX_ATUE_OFFSET(ofs) IOP13XX_REG_ADDR32(\
344 iop13xx_atue_pmmr_offset + (ofs))
345
346#define IOP13XX_ATUE_DID IOP13XX_REG_ADDR16(\
347 iop13xx_atue_pmmr_offset + 0x2)
348#define IOP13XX_ATUE_ATUCMD IOP13XX_REG_ADDR16(\
349 iop13xx_atue_pmmr_offset + 0x4)
350#define IOP13XX_ATUE_ATUSR IOP13XX_REG_ADDR16(\
351 iop13xx_atue_pmmr_offset + 0x6)
352
353#define IOP13XX_ATUE_IABAR0 IOP13XX_ATUE_OFFSET(0x10)
354#define IOP13XX_ATUE_IAUBAR0 IOP13XX_ATUE_OFFSET(0x14)
355#define IOP13XX_ATUE_IABAR1 IOP13XX_ATUE_OFFSET(0x18)
356#define IOP13XX_ATUE_IAUBAR1 IOP13XX_ATUE_OFFSET(0x1c)
357#define IOP13XX_ATUE_IABAR2 IOP13XX_ATUE_OFFSET(0x20)
358#define IOP13XX_ATUE_IAUBAR2 IOP13XX_ATUE_OFFSET(0x24)
359#define IOP13XX_ATUE_IALR0 IOP13XX_ATUE_OFFSET(0x40)
360#define IOP13XX_ATUE_IATVR0 IOP13XX_ATUE_OFFSET(0x44)
361#define IOP13XX_ATUE_IAUTVR0 IOP13XX_ATUE_OFFSET(0x48)
362#define IOP13XX_ATUE_IALR1 IOP13XX_ATUE_OFFSET(0x4c)
363#define IOP13XX_ATUE_IATVR1 IOP13XX_ATUE_OFFSET(0x50)
364#define IOP13XX_ATUE_IAUTVR1 IOP13XX_ATUE_OFFSET(0x54)
365#define IOP13XX_ATUE_IALR2 IOP13XX_ATUE_OFFSET(0x58)
366#define IOP13XX_ATUE_IATVR2 IOP13XX_ATUE_OFFSET(0x5c)
367#define IOP13XX_ATUE_IAUTVR2 IOP13XX_ATUE_OFFSET(0x60)
368#define IOP13XX_ATUE_PE_LSTS IOP13XX_REG_ADDR16(\
369 iop13xx_atue_pmmr_offset + 0xe2)
370#define IOP13XX_ATUE_OIOWTVR IOP13XX_ATUE_OFFSET(0x304)
371#define IOP13XX_ATUE_OUMBAR0 IOP13XX_ATUE_OFFSET(0x308)
372#define IOP13XX_ATUE_OUMWTVR0 IOP13XX_ATUE_OFFSET(0x30c)
373#define IOP13XX_ATUE_OUMBAR1 IOP13XX_ATUE_OFFSET(0x310)
374#define IOP13XX_ATUE_OUMWTVR1 IOP13XX_ATUE_OFFSET(0x314)
375#define IOP13XX_ATUE_OUMBAR2 IOP13XX_ATUE_OFFSET(0x318)
376#define IOP13XX_ATUE_OUMWTVR2 IOP13XX_ATUE_OFFSET(0x31c)
377#define IOP13XX_ATUE_OUMBAR3 IOP13XX_ATUE_OFFSET(0x320)
378#define IOP13XX_ATUE_OUMWTVR3 IOP13XX_ATUE_OFFSET(0x324)
379
380#define IOP13XX_ATUE_ATUCR IOP13XX_ATUE_OFFSET(0x70)
381#define IOP13XX_ATUE_PCSR IOP13XX_ATUE_OFFSET(0x74)
382#define IOP13XX_ATUE_ATUISR IOP13XX_ATUE_OFFSET(0x78)
383#define IOP13XX_ATUE_OIOBAR IOP13XX_ATUE_OFFSET(0x300)
384#define IOP13XX_ATUE_OCCAR IOP13XX_ATUE_OFFSET(0x32c)
385#define IOP13XX_ATUE_OCCDR IOP13XX_ATUE_OFFSET(0x330)
386
387#define IOP13XX_ATUE_PIE_STS IOP13XX_ATUE_OFFSET(0x384)
388#define IOP13XX_ATUE_PIE_MSK IOP13XX_ATUE_OFFSET(0x388)
389
390#define IOP13XX_ATUE_ATUCR_IVM (1 << 6)
391#define IOP13XX_ATUE_ATUCR_OUT_EN (1 << 1)
392#define IOP13XX_ATUE_OCCAR_BUS_NUM (24)
393#define IOP13XX_ATUE_OCCAR_DEV_NUM (19)
394#define IOP13XX_ATUE_OCCAR_FUNC_NUM (16)
395#define IOP13XX_ATUE_OCCAR_EXT_REG (8)
396#define IOP13XX_ATUE_OCCAR_REG (2)
397
398#define IOP13XX_ATUE_PCSR_BUS_NUM (24)
399#define IOP13XX_ATUE_PCSR_DEV_NUM (19)
400#define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
401#define IOP13XX_ATUE_PCSR_OUT_Q_BUSY (1 << 15)
402#define IOP13XX_ATUE_PCSR_IN_Q_BUSY (1 << 14)
403#define IOP13XX_ATUE_PCSR_END_POINT (1 << 13)
404#define IOP13XX_ATUE_PCSR_LLRB_BUSY (1 << 12)
405
406#define IOP13XX_ATUE_PCSR_BUS_NUM_MASK (0xff)
407#define IOP13XX_ATUE_PCSR_DEV_NUM_MASK (0x1f)
408#define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7)
409
410#define IOP13XX_ATUE_PCSR_CORE_RESET (8)
411#define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
412
413#define IOP13XX_ATUE_LSTS_TRAINING (1 << 11)
414#define IOP13XX_ATUE_STAT_SLOT_PWR_MSG (1 << 28)
415#define IOP13XX_ATUE_STAT_PME (1 << 27)
416#define IOP13XX_ATUE_STAT_HOT_PLUG_MSG (1 << 26)
417#define IOP13XX_ATUE_STAT_IVM (1 << 25)
418#define IOP13XX_ATUE_STAT_BIST (1 << 24)
419#define IOP13XX_ATUE_STAT_CFG_WRITE (1 << 18)
420#define IOP13XX_ATUE_STAT_VPD_ADDR (1 << 17)
421#define IOP13XX_ATUE_STAT_POWER_TRAN (1 << 16)
422#define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13)
423#define IOP13XX_ATUE_STAT_ROOT_SYS_ERR (1 << 12)
424#define IOP13XX_ATUE_STAT_ROOT_ERR_MSG (1 << 11)
425#define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10)
426#define IOP13XX_ATUE_STAT_ERR_COR (1 << 9 )
427#define IOP13XX_ATUE_STAT_ERR_UNCOR (1 << 8 )
428#define IOP13XX_ATUE_STAT_CRS (1 << 7 )
429#define IOP13XX_ATUE_STAT_LNK_DWN (1 << 6 )
430#define IOP13XX_ATUE_STAT_INT_REC_MABORT (1 << 5 )
431#define IOP13XX_ATUE_STAT_DET_PAR_ERR (1 << 4 )
432#define IOP13XX_ATUE_STAT_EXT_REC_MABORT (1 << 3 )
433#define IOP13XX_ATUE_STAT_SIG_TABORT (1 << 2 )
434#define IOP13XX_ATUE_STAT_EXT_REC_TABORT (1 << 1 )
435#define IOP13XX_ATUE_STAT_MASTER_DATA_PAR (1 << 0 )
436
437#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ (1 << 31)
438#define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT (1 << 30)
439#define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP (1 << 29)
440#define IOP13XX_ATUE_ESTAT_TX_PAR_ERR (1 << 28)
441#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ (1 << 20)
442#define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR (1 << 19)
443#define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP (1 << 18)
444#define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17)
445#define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP (1 << 16)
446#define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT (1 << 15)
447#define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT (1 << 14)
448#define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR (1 << 13)
449#define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP (1 << 12)
450#define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR (1 << 4 )
451#define IOP13XX_ATUE_ESTAT_TRAINING_ERR (1 << 0 )
452
453#define IOP13XX_ATUE_IALR_DISABLE (0x00000001)
454#define IOP13XX_ATUE_OUMBAR_ENABLE (0x80000000)
455#define IOP13XX_ATU_OUMBAR_FUNC_NUM (28)
456#define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7)
457/*=======================================================================*/
458
459/*============================MESSAGING UNIT=============================*/
460#define IOP13XX_MU_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_MU_PMMR_OFFSET +\
461 (ofs))
462
463#define IOP13XX_MU_IMR0 IOP13XX_MU_OFFSET(0x10)
464#define IOP13XX_MU_IMR1 IOP13XX_MU_OFFSET(0x14)
465#define IOP13XX_MU_OMR0 IOP13XX_MU_OFFSET(0x18)
466#define IOP13XX_MU_OMR1 IOP13XX_MU_OFFSET(0x1C)
467#define IOP13XX_MU_IDR IOP13XX_MU_OFFSET(0x20)
468#define IOP13XX_MU_IISR IOP13XX_MU_OFFSET(0x24)
469#define IOP13XX_MU_IIMR IOP13XX_MU_OFFSET(0x28)
470#define IOP13XX_MU_ODR IOP13XX_MU_OFFSET(0x2C)
471#define IOP13XX_MU_OISR IOP13XX_MU_OFFSET(0x30)
472#define IOP13XX_MU_OIMR IOP13XX_MU_OFFSET(0x34)
473#define IOP13XX_MU_IRCSR IOP13XX_MU_OFFSET(0x38)
474#define IOP13XX_MU_ORCSR IOP13XX_MU_OFFSET(0x3C)
475#define IOP13XX_MU_MIMR IOP13XX_MU_OFFSET(0x48)
476#define IOP13XX_MU_MUCR IOP13XX_MU_OFFSET(0x50)
477#define IOP13XX_MU_QBAR IOP13XX_MU_OFFSET(0x54)
478#define IOP13XX_MU_MUBAR IOP13XX_MU_OFFSET(0x84)
479
480#define IOP13XX_MU_WINDOW_SIZE (8 * 1024)
481#define IOP13XX_MU_BASE_PHYS (0xff000000)
482#define IOP13XX_MU_BASE_PCI (0xff000000)
483#define IOP13XX_MU_MIMR_PCI (IOP13XX_MU_BASE_PCI + 0x48)
484#define IOP13XX_MU_MIMR_CORE_SELECT (15)
485/*=======================================================================*/
486
487/*==============================ADMA UNITS===============================*/
488#define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9))
489#define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0)
490
491/*==============================XSI BRIDGE===============================*/
492#define IOP13XX_XBG_BECSR IOP13XX_REG_ADDR32(0x178c)
493#define IOP13XX_XBG_BERAR IOP13XX_REG_ADDR32(0x1790)
494#define IOP13XX_XBG_BERUAR IOP13XX_REG_ADDR32(0x1794)
495#define is_atue_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
496 IOP13XX_PMMR_VIRT_TO_PHYS(\
497 IOP13XX_ATUE_OCCDR))\
498 && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
499#define is_atux_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
500 IOP13XX_PMMR_VIRT_TO_PHYS(\
501 IOP13XX_ATUX_OCCDR))\
502 && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
503/*=======================================================================*/
504
505#define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\
506 (ofs))
507
508#define IOP13XX_PBI_CR IOP13XX_PBI_OFFSET(0x0)
509#define IOP13XX_PBI_SR IOP13XX_PBI_OFFSET(0x4)
510#define IOP13XX_PBI_BAR0 IOP13XX_PBI_OFFSET(0x8)
511#define IOP13XX_PBI_LR0 IOP13XX_PBI_OFFSET(0xc)
512#define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10)
513#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14)
514
515#define IOP13XX_PROCESSOR_FREQ IOP13XX_REG_ADDR32(0x2180)
516
517/* Watchdog timer definitions */
518#define IOP_WDTCR_EN_ARM 0x1e1e1e1e
519#define IOP_WDTCR_EN 0xe1e1e1e1
520#define IOP_WDTCR_DIS_ARM 0x1f1f1f1f
521#define IOP_WDTCR_DIS 0xf1f1f1f1
522#define IOP_RCSR_WDT (1 << 5) /* reset caused by watchdog timer */
523#define IOP13XX_WDTSR_WRITE_EN (1 << 31) /* used to speed up reset requests */
524#define IOP13XX_WDTCR_IB_RESET (1 << 0)
525
526#endif /* _IOP13XX_HW_H_ */
diff --git a/arch/arm/mach-iop13xx/include/mach/iq81340.h b/arch/arm/mach-iop13xx/include/mach/iq81340.h
new file mode 100644
index 000000000000..ba2cf931e9ce
--- /dev/null
+++ b/arch/arm/mach-iop13xx/include/mach/iq81340.h
@@ -0,0 +1,28 @@
1#ifndef _IQ81340_H_
2#define _IQ81340_H_
3
4#define IQ81340_PCE_BAR0 IOP13XX_PBI_LOWER_MEM_RA
5#define IQ81340_PCE_BAR1 (IQ81340_PCE_BAR0 + 0x02000000)
6
7#define IQ81340_FLASHBASE IQ81340_PCE_BAR0 /* Flash */
8
9#define IQ81340_PCE_BAR1_OFFSET(a) (IQ81340_PCE_BAR1 + (a))
10
11#define IQ81340_PRD_CODE IQ81340_PCE_BAR1_OFFSET(0)
12#define IQ81340_BRD_STEP IQ81340_PCE_BAR1_OFFSET(0x10000)
13#define IQ81340_CPLD_REV IQ81340_PCE_BAR1_OFFSET(0x20000)
14#define IQ81340_LED IQ81340_PCE_BAR1_OFFSET(0x30000)
15#define IQ81340_LHEX IQ81340_PCE_BAR1_OFFSET(0x40000)
16#define IQ81340_RHEX IQ81340_PCE_BAR1_OFFSET(0x50000)
17#define IQ81340_BUZZER IQ81340_PCE_BAR1_OFFSET(0x60000)
18#define IQ81340_32K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x70000)
19#define IQ81340_256K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x80000)
20#define IQ81340_ROTARY_SW IQ81340_PCE_BAR1_OFFSET(0xd0000)
21#define IQ81340_BATT_STAT IQ81340_PCE_BAR1_OFFSET(0xf0000)
22#define IQ81340_CMP_FLSH IQ81340_PCE_BAR1_OFFSET(0x1000000) /* 16MB */
23
24#define PBI_CF_IDE_BASE (IQ81340_CMP_FLSH)
25#define PBI_CF_BAR_ADDR (IOP13XX_PBI_BAR1)
26
27
28#endif /* _IQ81340_H_ */
diff --git a/arch/arm/mach-iop13xx/include/mach/irqs.h b/arch/arm/mach-iop13xx/include/mach/irqs.h
new file mode 100644
index 000000000000..054e7acb5bfa
--- /dev/null
+++ b/arch/arm/mach-iop13xx/include/mach/irqs.h
@@ -0,0 +1,196 @@
1#ifndef _IOP13XX_IRQS_H_
2#define _IOP13XX_IRQS_H_
3
4#ifndef __ASSEMBLER__
5#include <linux/types.h>
6
7/* INTPND0 CP6 R0 Page 3
8 */
9static inline u32 read_intpnd_0(void)
10{
11 u32 val;
12 asm volatile("mrc p6, 0, %0, c0, c3, 0":"=r" (val));
13 return val;
14}
15
16/* INTPND1 CP6 R1 Page 3
17 */
18static inline u32 read_intpnd_1(void)
19{
20 u32 val;
21 asm volatile("mrc p6, 0, %0, c1, c3, 0":"=r" (val));
22 return val;
23}
24
25/* INTPND2 CP6 R2 Page 3
26 */
27static inline u32 read_intpnd_2(void)
28{
29 u32 val;
30 asm volatile("mrc p6, 0, %0, c2, c3, 0":"=r" (val));
31 return val;
32}
33
34/* INTPND3 CP6 R3 Page 3
35 */
36static inline u32 read_intpnd_3(void)
37{
38 u32 val;
39 asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val));
40 return val;
41}
42#endif
43
44#define INTBASE 0
45#define INTSIZE_4 1
46
47/*
48 * iop34x chipset interrupts
49 */
50#define IOP13XX_IRQ(x) (IOP13XX_IRQ_OFS + (x))
51
52/*
53 * On IRQ or FIQ register
54 */
55#define IRQ_IOP13XX_ADMA0_EOT (0)
56#define IRQ_IOP13XX_ADMA0_EOC (1)
57#define IRQ_IOP13XX_ADMA1_EOT (2)
58#define IRQ_IOP13XX_ADMA1_EOC (3)
59#define IRQ_IOP13XX_ADMA2_EOT (4)
60#define IRQ_IOP13XX_ADMA2_EOC (5)
61#define IRQ_IOP134_WATCHDOG (6)
62#define IRQ_IOP13XX_RSVD_7 (7)
63#define IRQ_IOP13XX_TIMER0 (8)
64#define IRQ_IOP13XX_TIMER1 (9)
65#define IRQ_IOP13XX_I2C_0 (10)
66#define IRQ_IOP13XX_I2C_1 (11)
67#define IRQ_IOP13XX_MSG (12)
68#define IRQ_IOP13XX_MSGIBQ (13)
69#define IRQ_IOP13XX_ATU_IM (14)
70#define IRQ_IOP13XX_ATU_BIST (15)
71#define IRQ_IOP13XX_PPMU (16)
72#define IRQ_IOP13XX_COREPMU (17)
73#define IRQ_IOP13XX_CORECACHE (18)
74#define IRQ_IOP13XX_RSVD_19 (19)
75#define IRQ_IOP13XX_RSVD_20 (20)
76#define IRQ_IOP13XX_RSVD_21 (21)
77#define IRQ_IOP13XX_RSVD_22 (22)
78#define IRQ_IOP13XX_RSVD_23 (23)
79#define IRQ_IOP13XX_XINT0 (24)
80#define IRQ_IOP13XX_XINT1 (25)
81#define IRQ_IOP13XX_XINT2 (26)
82#define IRQ_IOP13XX_XINT3 (27)
83#define IRQ_IOP13XX_XINT4 (28)
84#define IRQ_IOP13XX_XINT5 (29)
85#define IRQ_IOP13XX_XINT6 (30)
86#define IRQ_IOP13XX_XINT7 (31)
87 /* IINTSRC1 bit */
88#define IRQ_IOP13XX_XINT8 (32) /* 0 */
89#define IRQ_IOP13XX_XINT9 (33) /* 1 */
90#define IRQ_IOP13XX_XINT10 (34) /* 2 */
91#define IRQ_IOP13XX_XINT11 (35) /* 3 */
92#define IRQ_IOP13XX_XINT12 (36) /* 4 */
93#define IRQ_IOP13XX_XINT13 (37) /* 5 */
94#define IRQ_IOP13XX_XINT14 (38) /* 6 */
95#define IRQ_IOP13XX_XINT15 (39) /* 7 */
96#define IRQ_IOP13XX_RSVD_40 (40) /* 8 */
97#define IRQ_IOP13XX_RSVD_41 (41) /* 9 */
98#define IRQ_IOP13XX_RSVD_42 (42) /* 10 */
99#define IRQ_IOP13XX_RSVD_43 (43) /* 11 */
100#define IRQ_IOP13XX_RSVD_44 (44) /* 12 */
101#define IRQ_IOP13XX_RSVD_45 (45) /* 13 */
102#define IRQ_IOP13XX_RSVD_46 (46) /* 14 */
103#define IRQ_IOP13XX_RSVD_47 (47) /* 15 */
104#define IRQ_IOP13XX_RSVD_48 (48) /* 16 */
105#define IRQ_IOP13XX_RSVD_49 (49) /* 17 */
106#define IRQ_IOP13XX_RSVD_50 (50) /* 18 */
107#define IRQ_IOP13XX_UART0 (51) /* 19 */
108#define IRQ_IOP13XX_UART1 (52) /* 20 */
109#define IRQ_IOP13XX_PBIE (53) /* 21 */
110#define IRQ_IOP13XX_ATU_CRW (54) /* 22 */
111#define IRQ_IOP13XX_ATU_ERR (55) /* 23 */
112#define IRQ_IOP13XX_MCU_ERR (56) /* 24 */
113#define IRQ_IOP13XX_ADMA0_ERR (57) /* 25 */
114#define IRQ_IOP13XX_ADMA1_ERR (58) /* 26 */
115#define IRQ_IOP13XX_ADMA2_ERR (59) /* 27 */
116#define IRQ_IOP13XX_RSVD_60 (60) /* 28 */
117#define IRQ_IOP13XX_RSVD_61 (61) /* 29 */
118#define IRQ_IOP13XX_MSG_ERR (62) /* 30 */
119#define IRQ_IOP13XX_RSVD_63 (63) /* 31 */
120 /* IINTSRC2 bit */
121#define IRQ_IOP13XX_INTERPROC (64) /* 0 */
122#define IRQ_IOP13XX_RSVD_65 (65) /* 1 */
123#define IRQ_IOP13XX_RSVD_66 (66) /* 2 */
124#define IRQ_IOP13XX_RSVD_67 (67) /* 3 */
125#define IRQ_IOP13XX_RSVD_68 (68) /* 4 */
126#define IRQ_IOP13XX_RSVD_69 (69) /* 5 */
127#define IRQ_IOP13XX_RSVD_70 (70) /* 6 */
128#define IRQ_IOP13XX_RSVD_71 (71) /* 7 */
129#define IRQ_IOP13XX_RSVD_72 (72) /* 8 */
130#define IRQ_IOP13XX_RSVD_73 (73) /* 9 */
131#define IRQ_IOP13XX_RSVD_74 (74) /* 10 */
132#define IRQ_IOP13XX_RSVD_75 (75) /* 11 */
133#define IRQ_IOP13XX_RSVD_76 (76) /* 12 */
134#define IRQ_IOP13XX_RSVD_77 (77) /* 13 */
135#define IRQ_IOP13XX_RSVD_78 (78) /* 14 */
136#define IRQ_IOP13XX_RSVD_79 (79) /* 15 */
137#define IRQ_IOP13XX_RSVD_80 (80) /* 16 */
138#define IRQ_IOP13XX_RSVD_81 (81) /* 17 */
139#define IRQ_IOP13XX_RSVD_82 (82) /* 18 */
140#define IRQ_IOP13XX_RSVD_83 (83) /* 19 */
141#define IRQ_IOP13XX_RSVD_84 (84) /* 20 */
142#define IRQ_IOP13XX_RSVD_85 (85) /* 21 */
143#define IRQ_IOP13XX_RSVD_86 (86) /* 22 */
144#define IRQ_IOP13XX_RSVD_87 (87) /* 23 */
145#define IRQ_IOP13XX_RSVD_88 (88) /* 24 */
146#define IRQ_IOP13XX_RSVD_89 (89) /* 25 */
147#define IRQ_IOP13XX_RSVD_90 (90) /* 26 */
148#define IRQ_IOP13XX_RSVD_91 (91) /* 27 */
149#define IRQ_IOP13XX_RSVD_92 (92) /* 28 */
150#define IRQ_IOP13XX_RSVD_93 (93) /* 29 */
151#define IRQ_IOP13XX_SIB_ERR (94) /* 30 */
152#define IRQ_IOP13XX_SRAM_ERR (95) /* 31 */
153 /* IINTSRC3 bit */
154#define IRQ_IOP13XX_I2C_2 (96) /* 0 */
155#define IRQ_IOP13XX_ATUE_BIST (97) /* 1 */
156#define IRQ_IOP13XX_ATUE_CRW (98) /* 2 */
157#define IRQ_IOP13XX_ATUE_ERR (99) /* 3 */
158#define IRQ_IOP13XX_IMU (100) /* 4 */
159#define IRQ_IOP13XX_RSVD_101 (101) /* 5 */
160#define IRQ_IOP13XX_RSVD_102 (102) /* 6 */
161#define IRQ_IOP13XX_TPMI0_OUT (103) /* 7 */
162#define IRQ_IOP13XX_TPMI1_OUT (104) /* 8 */
163#define IRQ_IOP13XX_TPMI2_OUT (105) /* 9 */
164#define IRQ_IOP13XX_TPMI3_OUT (106) /* 10 */
165#define IRQ_IOP13XX_ATUE_IMA (107) /* 11 */
166#define IRQ_IOP13XX_ATUE_IMB (108) /* 12 */
167#define IRQ_IOP13XX_ATUE_IMC (109) /* 13 */
168#define IRQ_IOP13XX_ATUE_IMD (110) /* 14 */
169#define IRQ_IOP13XX_MU_MSI_TB (111) /* 15 */
170#define IRQ_IOP13XX_RSVD_112 (112) /* 16 */
171#define IRQ_IOP13XX_INBD_MSI (113) /* 17 */
172#define IRQ_IOP13XX_RSVD_114 (114) /* 18 */
173#define IRQ_IOP13XX_RSVD_115 (115) /* 19 */
174#define IRQ_IOP13XX_RSVD_116 (116) /* 20 */
175#define IRQ_IOP13XX_RSVD_117 (117) /* 21 */
176#define IRQ_IOP13XX_RSVD_118 (118) /* 22 */
177#define IRQ_IOP13XX_RSVD_119 (119) /* 23 */
178#define IRQ_IOP13XX_RSVD_120 (120) /* 24 */
179#define IRQ_IOP13XX_RSVD_121 (121) /* 25 */
180#define IRQ_IOP13XX_RSVD_122 (122) /* 26 */
181#define IRQ_IOP13XX_RSVD_123 (123) /* 27 */
182#define IRQ_IOP13XX_RSVD_124 (124) /* 28 */
183#define IRQ_IOP13XX_RSVD_125 (125) /* 29 */
184#define IRQ_IOP13XX_RSVD_126 (126) /* 30 */
185#define IRQ_IOP13XX_HPI (127) /* 31 */
186
187#ifdef CONFIG_PCI_MSI
188#define IRQ_IOP13XX_MSI_0 (IRQ_IOP13XX_HPI + 1)
189#define NR_IOP13XX_IRQS (IRQ_IOP13XX_MSI_0 + 128)
190#else
191#define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1)
192#endif
193
194#define NR_IRQS NR_IOP13XX_IRQS
195
196#endif /* _IOP13XX_IRQ_H_ */
diff --git a/arch/arm/mach-iop13xx/include/mach/memory.h b/arch/arm/mach-iop13xx/include/mach/memory.h
new file mode 100644
index 000000000000..e8b59d8f1bb9
--- /dev/null
+++ b/arch/arm/mach-iop13xx/include/mach/memory.h
@@ -0,0 +1,64 @@
1#ifndef __ASM_ARCH_MEMORY_H
2#define __ASM_ARCH_MEMORY_H
3
4#include <mach/hardware.h>
5
6/*
7 * Physical DRAM offset.
8 */
9#define PHYS_OFFSET UL(0x00000000)
10#define TASK_SIZE UL(0x3f000000)
11#define PAGE_OFFSET UL(0x40000000)
12#define TASK_UNMAPPED_BASE ((TASK_SIZE + 0x01000000) / 3)
13
14#ifndef __ASSEMBLY__
15
16#if defined(CONFIG_ARCH_IOP13XX)
17#define IOP13XX_PMMR_V_START (IOP13XX_PMMR_VIRT_MEM_BASE)
18#define IOP13XX_PMMR_V_END (IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_SIZE)
19#define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE)
20#define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE)
21
22/*
23 * Virtual view <-> PCI DMA view memory address translations
24 * virt_to_bus: Used to translate the virtual address to an
25 * address suitable to be passed to set_dma_addr
26 * bus_to_virt: Used to convert an address for DMA operations
27 * to an address that the kernel can use.
28 */
29
30/* RAM has 1:1 mapping on the PCIe/x Busses */
31#define __virt_to_bus(x) (__virt_to_phys(x))
32#define __bus_to_virt(x) (__phys_to_virt(x))
33
34#define virt_to_lbus(x) \
35(( ((void*)(x) >= (void*)IOP13XX_PMMR_V_START) && \
36((void*)(x) < (void*)IOP13XX_PMMR_V_END) ) ? \
37((x) - IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_PHYS_MEM_BASE) : \
38((x) - PAGE_OFFSET + PHYS_OFFSET))
39
40#define lbus_to_virt(x) \
41(( ((x) >= IOP13XX_PMMR_P_START) && ((x) < IOP13XX_PMMR_P_END) ) ? \
42((x) - IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_VIRT_MEM_BASE ) : \
43((x) - PHYS_OFFSET + PAGE_OFFSET))
44
45/* Device is an lbus device if it is on the platform bus of the IOP13XX */
46#define is_lbus_device(dev) (dev &&\
47 (strncmp(dev->bus->name, "platform", 8) == 0))
48
49#define __arch_page_to_dma(dev, page) \
50({is_lbus_device(dev) ? (dma_addr_t)virt_to_lbus(page_address(page)) : \
51(dma_addr_t)__virt_to_bus(page_address(page));})
52
53#define __arch_dma_to_virt(dev, addr) \
54({is_lbus_device(dev) ? lbus_to_virt(addr) : __bus_to_virt(addr);})
55
56#define __arch_virt_to_dma(dev, addr) \
57({is_lbus_device(dev) ? virt_to_lbus(addr) : __virt_to_bus(addr);})
58
59#endif /* CONFIG_ARCH_IOP13XX */
60#endif /* !ASSEMBLY */
61
62#define PFN_TO_NID(addr) (0)
63
64#endif
diff --git a/arch/arm/mach-iop13xx/include/mach/msi.h b/arch/arm/mach-iop13xx/include/mach/msi.h
new file mode 100644
index 000000000000..b80c5ae17e99
--- /dev/null
+++ b/arch/arm/mach-iop13xx/include/mach/msi.h
@@ -0,0 +1,11 @@
1#ifndef _IOP13XX_MSI_H_
2#define _IOP13XX_MSI_H_
3#ifdef CONFIG_PCI_MSI
4void iop13xx_msi_init(void);
5#else
6static inline void iop13xx_msi_init(void)
7{
8 return;
9}
10#endif
11#endif
diff --git a/arch/arm/mach-iop13xx/include/mach/pci.h b/arch/arm/mach-iop13xx/include/mach/pci.h
new file mode 100644
index 000000000000..17b5515af8b1
--- /dev/null
+++ b/arch/arm/mach-iop13xx/include/mach/pci.h
@@ -0,0 +1,57 @@
1#ifndef _IOP13XX_PCI_H_
2#define _IOP13XX_PCI_H_
3#include <mach/irqs.h>
4#include <asm/io.h>
5
6struct pci_sys_data;
7struct hw_pci;
8int iop13xx_pci_setup(int nr, struct pci_sys_data *sys);
9struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *);
10void iop13xx_atu_select(struct hw_pci *plat_pci);
11void iop13xx_pci_init(void);
12void iop13xx_map_pci_memory(void);
13
14#define IOP_PCI_STATUS_ERROR (PCI_STATUS_PARITY | \
15 PCI_STATUS_SIG_TARGET_ABORT | \
16 PCI_STATUS_REC_TARGET_ABORT | \
17 PCI_STATUS_REC_TARGET_ABORT | \
18 PCI_STATUS_REC_MASTER_ABORT | \
19 PCI_STATUS_SIG_SYSTEM_ERROR | \
20 PCI_STATUS_DETECTED_PARITY)
21
22#define IOP13XX_ATUE_ATUISR_ERROR (IOP13XX_ATUE_STAT_HALT_ON_ERROR | \
23 IOP13XX_ATUE_STAT_ROOT_SYS_ERR | \
24 IOP13XX_ATUE_STAT_PCI_IFACE_ERR | \
25 IOP13XX_ATUE_STAT_ERR_COR | \
26 IOP13XX_ATUE_STAT_ERR_UNCOR | \
27 IOP13XX_ATUE_STAT_CRS | \
28 IOP13XX_ATUE_STAT_DET_PAR_ERR | \
29 IOP13XX_ATUE_STAT_EXT_REC_MABORT | \
30 IOP13XX_ATUE_STAT_SIG_TABORT | \
31 IOP13XX_ATUE_STAT_EXT_REC_TABORT | \
32 IOP13XX_ATUE_STAT_MASTER_DATA_PAR)
33
34#define IOP13XX_ATUX_ATUISR_ERROR (IOP13XX_ATUX_STAT_TX_SCEM | \
35 IOP13XX_ATUX_STAT_REC_SCEM | \
36 IOP13XX_ATUX_STAT_TX_SERR | \
37 IOP13XX_ATUX_STAT_DET_PAR_ERR | \
38 IOP13XX_ATUX_STAT_INT_REC_MABORT | \
39 IOP13XX_ATUX_STAT_REC_SERR | \
40 IOP13XX_ATUX_STAT_EXT_REC_MABORT | \
41 IOP13XX_ATUX_STAT_EXT_REC_TABORT | \
42 IOP13XX_ATUX_STAT_EXT_SIG_TABORT | \
43 IOP13XX_ATUX_STAT_MASTER_DATA_PAR)
44
45/* PCI interrupts
46 */
47#define ATUX_INTA IRQ_IOP13XX_XINT0
48#define ATUX_INTB IRQ_IOP13XX_XINT1
49#define ATUX_INTC IRQ_IOP13XX_XINT2
50#define ATUX_INTD IRQ_IOP13XX_XINT3
51
52#define ATUE_INTA IRQ_IOP13XX_ATUE_IMA
53#define ATUE_INTB IRQ_IOP13XX_ATUE_IMB
54#define ATUE_INTC IRQ_IOP13XX_ATUE_IMC
55#define ATUE_INTD IRQ_IOP13XX_ATUE_IMD
56
57#endif /* _IOP13XX_PCI_H_ */
diff --git a/arch/arm/mach-iop13xx/include/mach/system.h b/arch/arm/mach-iop13xx/include/mach/system.h
new file mode 100644
index 000000000000..c7127f416e1f
--- /dev/null
+++ b/arch/arm/mach-iop13xx/include/mach/system.h
@@ -0,0 +1,27 @@
1/*
2 * arch/arm/mach-iop13xx/include/mach/system.h
3 *
4 * Copyright (C) 2004 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <mach/iop13xx.h>
11static inline void arch_idle(void)
12{
13 cpu_do_idle();
14}
15
16static inline void arch_reset(char mode)
17{
18 /*
19 * Reset the internal bus (warning both cores are reset)
20 */
21 write_wdtcr(IOP_WDTCR_EN_ARM);
22 write_wdtcr(IOP_WDTCR_EN);
23 write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
24 write_wdtcr(0x1000);
25
26 for(;;);
27}
diff --git a/arch/arm/mach-iop13xx/include/mach/time.h b/arch/arm/mach-iop13xx/include/mach/time.h
new file mode 100644
index 000000000000..49213d9d7cad
--- /dev/null
+++ b/arch/arm/mach-iop13xx/include/mach/time.h
@@ -0,0 +1,107 @@
1#ifndef _IOP13XX_TIME_H_
2#define _IOP13XX_TIME_H_
3#define IRQ_IOP_TIMER0 IRQ_IOP13XX_TIMER0
4
5#define IOP_TMR_EN 0x02
6#define IOP_TMR_RELOAD 0x04
7#define IOP_TMR_PRIVILEGED 0x08
8#define IOP_TMR_RATIO_1_1 0x00
9
10#define IOP13XX_XSI_FREQ_RATIO_MASK (3 << 19)
11#define IOP13XX_XSI_FREQ_RATIO_2 (0 << 19)
12#define IOP13XX_XSI_FREQ_RATIO_3 (1 << 19)
13#define IOP13XX_XSI_FREQ_RATIO_4 (2 << 19)
14#define IOP13XX_CORE_FREQ_MASK (7 << 16)
15#define IOP13XX_CORE_FREQ_600 (0 << 16)
16#define IOP13XX_CORE_FREQ_667 (1 << 16)
17#define IOP13XX_CORE_FREQ_800 (2 << 16)
18#define IOP13XX_CORE_FREQ_933 (3 << 16)
19#define IOP13XX_CORE_FREQ_1000 (4 << 16)
20#define IOP13XX_CORE_FREQ_1200 (5 << 16)
21
22void iop_init_time(unsigned long tickrate);
23unsigned long iop_gettimeoffset(void);
24
25static inline unsigned long iop13xx_core_freq(void)
26{
27 unsigned long freq = __raw_readl(IOP13XX_PROCESSOR_FREQ);
28 freq &= IOP13XX_CORE_FREQ_MASK;
29 switch (freq) {
30 case IOP13XX_CORE_FREQ_600:
31 return 600000000;
32 case IOP13XX_CORE_FREQ_667:
33 return 667000000;
34 case IOP13XX_CORE_FREQ_800:
35 return 800000000;
36 case IOP13XX_CORE_FREQ_933:
37 return 933000000;
38 case IOP13XX_CORE_FREQ_1000:
39 return 1000000000;
40 case IOP13XX_CORE_FREQ_1200:
41 return 1200000000;
42 default:
43 printk("%s: warning unknown frequency, defaulting to 800Mhz\n",
44 __FUNCTION__);
45 }
46
47 return 800000000;
48}
49
50static inline unsigned long iop13xx_xsi_bus_ratio(void)
51{
52 unsigned long ratio = __raw_readl(IOP13XX_PROCESSOR_FREQ);
53 ratio &= IOP13XX_XSI_FREQ_RATIO_MASK;
54 switch (ratio) {
55 case IOP13XX_XSI_FREQ_RATIO_2:
56 return 2;
57 case IOP13XX_XSI_FREQ_RATIO_3:
58 return 3;
59 case IOP13XX_XSI_FREQ_RATIO_4:
60 return 4;
61 default:
62 printk("%s: warning unknown ratio, defaulting to 2\n",
63 __FUNCTION__);
64 }
65
66 return 2;
67}
68
69static inline void write_tmr0(u32 val)
70{
71 asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val));
72}
73
74static inline void write_tmr1(u32 val)
75{
76 asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (val));
77}
78
79static inline u32 read_tcr0(void)
80{
81 u32 val;
82 asm volatile("mrc p6, 0, %0, c2, c9, 0" : "=r" (val));
83 return val;
84}
85
86static inline u32 read_tcr1(void)
87{
88 u32 val;
89 asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val));
90 return val;
91}
92
93static inline void write_trr0(u32 val)
94{
95 asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val));
96}
97
98static inline void write_trr1(u32 val)
99{
100 asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (val));
101}
102
103static inline void write_tisr(u32 val)
104{
105 asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (val));
106}
107#endif
diff --git a/arch/arm/mach-iop13xx/include/mach/timex.h b/arch/arm/mach-iop13xx/include/mach/timex.h
new file mode 100644
index 000000000000..5b1f1c8a8270
--- /dev/null
+++ b/arch/arm/mach-iop13xx/include/mach/timex.h
@@ -0,0 +1,3 @@
1#include <mach/hardware.h>
2
3#define CLOCK_TICK_RATE (100 * HZ)
diff --git a/arch/arm/mach-iop13xx/include/mach/uncompress.h b/arch/arm/mach-iop13xx/include/mach/uncompress.h
new file mode 100644
index 000000000000..fa4f80522fad
--- /dev/null
+++ b/arch/arm/mach-iop13xx/include/mach/uncompress.h
@@ -0,0 +1,23 @@
1#include <asm/types.h>
2#include <linux/serial_reg.h>
3#include <mach/hardware.h>
4
5#define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS)
6#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
7
8static inline void putc(char c)
9{
10 while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE)
11 barrier();
12 UART_BASE[UART_TX] = c;
13}
14
15static inline void flush(void)
16{
17}
18
19/*
20 * nothing to do
21 */
22#define arch_decomp_setup()
23#define arch_decomp_wdog()
diff --git a/arch/arm/mach-iop13xx/include/mach/vmalloc.h b/arch/arm/mach-iop13xx/include/mach/vmalloc.h
new file mode 100644
index 000000000000..c53456740345
--- /dev/null
+++ b/arch/arm/mach-iop13xx/include/mach/vmalloc.h
@@ -0,0 +1,4 @@
1#ifndef _VMALLOC_H_
2#define _VMALLOC_H_
3#define VMALLOC_END 0xfa000000UL
4#endif
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
index 44b8c8c14105..26cfa318142c 100644
--- a/arch/arm/mach-iop13xx/io.c
+++ b/arch/arm/mach-iop13xx/io.c
@@ -18,7 +18,7 @@
18 */ 18 */
19#include <linux/kernel.h> 19#include <linux/kernel.h>
20#include <linux/module.h> 20#include <linux/module.h>
21#include <asm/arch/hardware.h> 21#include <mach/hardware.h>
22#include <asm/io.h> 22#include <asm/io.h>
23 23
24void * __iomem __iop13xx_io(unsigned long io_addr) 24void * __iomem __iop13xx_io(unsigned long io_addr)
diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c
index e17457e8e919..5051c03d437c 100644
--- a/arch/arm/mach-iop13xx/iq81340mc.c
+++ b/arch/arm/mach-iop13xx/iq81340mc.c
@@ -18,14 +18,14 @@
18 */ 18 */
19#include <linux/pci.h> 19#include <linux/pci.h>
20 20
21#include <asm/arch/hardware.h> 21#include <mach/hardware.h>
22#include <asm/irq.h> 22#include <asm/irq.h>
23#include <asm/mach/pci.h> 23#include <asm/mach/pci.h>
24#include <asm/mach-types.h> 24#include <asm/mach-types.h>
25#include <asm/mach/arch.h> 25#include <asm/mach/arch.h>
26#include <asm/arch/pci.h> 26#include <mach/pci.h>
27#include <asm/mach/time.h> 27#include <asm/mach/time.h>
28#include <asm/arch/time.h> 28#include <mach/time.h>
29 29
30extern int init_atu; /* Flag to select which ATU(s) to initialize / disable */ 30extern int init_atu; /* Flag to select which ATU(s) to initialize / disable */
31 31
diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c
index 19204d8f8109..bc443073a8e3 100644
--- a/arch/arm/mach-iop13xx/iq81340sc.c
+++ b/arch/arm/mach-iop13xx/iq81340sc.c
@@ -18,14 +18,14 @@
18 */ 18 */
19#include <linux/pci.h> 19#include <linux/pci.h>
20 20
21#include <asm/arch/hardware.h> 21#include <mach/hardware.h>
22#include <asm/irq.h> 22#include <asm/irq.h>
23#include <asm/mach/pci.h> 23#include <asm/mach/pci.h>
24#include <asm/mach-types.h> 24#include <asm/mach-types.h>
25#include <asm/mach/arch.h> 25#include <asm/mach/arch.h>
26#include <asm/arch/pci.h> 26#include <mach/pci.h>
27#include <asm/mach/time.h> 27#include <asm/mach/time.h>
28#include <asm/arch/time.h> 28#include <mach/time.h>
29 29
30extern int init_atu; 30extern int init_atu;
31 31
diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c
index e860a6d22dee..0d099ca87bdf 100644
--- a/arch/arm/mach-iop13xx/irq.c
+++ b/arch/arm/mach-iop13xx/irq.c
@@ -23,9 +23,9 @@
23#include <asm/uaccess.h> 23#include <asm/uaccess.h>
24#include <asm/mach/irq.h> 24#include <asm/mach/irq.h>
25#include <asm/irq.h> 25#include <asm/irq.h>
26#include <asm/arch/hardware.h> 26#include <mach/hardware.h>
27#include <asm/arch/irqs.h> 27#include <mach/irqs.h>
28#include <asm/arch/msi.h> 28#include <mach/msi.h>
29 29
30/* INTCTL0 CP6 R0 Page 4 30/* INTCTL0 CP6 R0 Page 4
31 */ 31 */
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index a0e0147f24f8..673b0db22034 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -21,11 +21,11 @@
21#include <linux/delay.h> 21#include <linux/delay.h>
22#include <linux/jiffies.h> 22#include <linux/jiffies.h>
23#include <asm/irq.h> 23#include <asm/irq.h>
24#include <asm/arch/hardware.h> 24#include <mach/hardware.h>
25#include <asm/sizes.h> 25#include <asm/sizes.h>
26#include <asm/signal.h> 26#include <asm/signal.h>
27#include <asm/mach/pci.h> 27#include <asm/mach/pci.h>
28#include <asm/arch/pci.h> 28#include <mach/pci.h>
29 29
30#define IOP13XX_PCI_DEBUG 0 30#define IOP13XX_PCI_DEBUG 0
31#define PRINTK(x...) ((void)(IOP13XX_PCI_DEBUG && printk(x))) 31#define PRINTK(x...) ((void)(IOP13XX_PCI_DEBUG && printk(x)))
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
index d3fee8a11b62..b17ccc8cb471 100644
--- a/arch/arm/mach-iop13xx/setup.c
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -22,7 +22,7 @@
22#include <linux/mtd/physmap.h> 22#include <linux/mtd/physmap.h>
23#endif 23#endif
24#include <asm/mach/map.h> 24#include <asm/mach/map.h>
25#include <asm/arch/hardware.h> 25#include <mach/hardware.h>
26#include <asm/irq.h> 26#include <asm/irq.h>
27#include <asm/io.h> 27#include <asm/io.h>
28#include <asm/hardware/iop_adma.h> 28#include <asm/hardware/iop_adma.h>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 10:12:59 -0500