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authorOlof Johansson <olof@lixom.net>2012-06-07 14:43:23 -0400
committerOlof Johansson <olof@lixom.net>2012-06-07 14:47:28 -0400
commit97114f3982630d35a8a6367244f185a1c3277ad5 (patch)
treea166bc430c63c63becf351a3fe9f8af5d9305ebb /arch/arm/mach-imx
parentf8f5701bdaf9134b1f90e5044a82c66324d2073f (diff)
parentb0286f20c36d0c1e7537489daddaf574abf403dd (diff)
Merge tag 'imx-clk-common-fixes' of git://git.pengutronix.de/git/imx/linux-2.6 into fixes
From Sascha Hauer: "Some fixes for the fresh i.MX common clock support" Resolved trivial conflict in arch/arm/plat-mxc/include/mach/common.h. * tag 'imx-clk-common-fixes' of git://git.pengutronix.de/git/imx/linux-2.6: ARM: imx6q: prepare and enable init on clks directly instead of clk_get first ARM i.MX: remove now unnecessary argument from mxc_timer_init ARM: i.MX: change timer clock from ipg to perclk ARM i.MX5: fix gpt peripheral clock path Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-imx')
-rw-r--r--arch/arm/mach-imx/clk-imx1.c3
-rw-r--r--arch/arm/mach-imx/clk-imx21.c4
-rw-r--r--arch/arm/mach-imx/clk-imx25.c2
-rw-r--r--arch/arm/mach-imx/clk-imx27.c3
-rw-r--r--arch/arm/mach-imx/clk-imx31.c3
-rw-r--r--arch/arm/mach-imx/clk-imx35.c6
-rw-r--r--arch/arm/mach-imx/clk-imx51-imx53.c12
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c22
8 files changed, 20 insertions, 35 deletions
diff --git a/arch/arm/mach-imx/clk-imx1.c b/arch/arm/mach-imx/clk-imx1.c
index 0f0beb580b73..516ddee1948e 100644
--- a/arch/arm/mach-imx/clk-imx1.c
+++ b/arch/arm/mach-imx/clk-imx1.c
@@ -108,8 +108,7 @@ int __init mx1_clocks_init(unsigned long fref)
108 clk_register_clkdev(clk[clk32], NULL, "mxc_rtc.0"); 108 clk_register_clkdev(clk[clk32], NULL, "mxc_rtc.0");
109 clk_register_clkdev(clk[clko], "clko", NULL); 109 clk_register_clkdev(clk[clko], "clko", NULL);
110 110
111 mxc_timer_init(NULL, MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), 111 mxc_timer_init(MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), MX1_TIM1_INT);
112 MX1_TIM1_INT);
113 112
114 return 0; 113 return 0;
115} 114}
diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
index 4e4f384ee8dd..ea13e61bd5f3 100644
--- a/arch/arm/mach-imx/clk-imx21.c
+++ b/arch/arm/mach-imx/clk-imx21.c
@@ -180,7 +180,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
180 clk_register_clkdev(clk[sdhc1_ipg_gate], "sdhc1", NULL); 180 clk_register_clkdev(clk[sdhc1_ipg_gate], "sdhc1", NULL);
181 clk_register_clkdev(clk[sdhc2_ipg_gate], "sdhc2", NULL); 181 clk_register_clkdev(clk[sdhc2_ipg_gate], "sdhc2", NULL);
182 182
183 mxc_timer_init(NULL, MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), 183 mxc_timer_init(MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), MX21_INT_GPT1);
184 MX21_INT_GPT1); 184
185 return 0; 185 return 0;
186} 186}
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index d9833bb5fd61..fdd8cc87c9fe 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -243,6 +243,6 @@ int __init mx25_clocks_init(void)
243 clk_register_clkdev(clk[sdma_ahb], "ahb", "imx35-sdma"); 243 clk_register_clkdev(clk[sdma_ahb], "ahb", "imx35-sdma");
244 clk_register_clkdev(clk[iim_ipg], "iim", NULL); 244 clk_register_clkdev(clk[iim_ipg], "iim", NULL);
245 245
246 mxc_timer_init(NULL, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); 246 mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
247 return 0; 247 return 0;
248} 248}
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index 50a7ebd8d1b2..295cbd7c08dc 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -263,8 +263,7 @@ int __init mx27_clocks_init(unsigned long fref)
263 clk_register_clkdev(clk[ssi1_baud_gate], "bitrate" , "imx-ssi.0"); 263 clk_register_clkdev(clk[ssi1_baud_gate], "bitrate" , "imx-ssi.0");
264 clk_register_clkdev(clk[ssi2_baud_gate], "bitrate" , "imx-ssi.1"); 264 clk_register_clkdev(clk[ssi2_baud_gate], "bitrate" , "imx-ssi.1");
265 265
266 mxc_timer_init(NULL, MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), 266 mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
267 MX27_INT_GPT1);
268 267
269 clk_prepare_enable(clk[emi_ahb_gate]); 268 clk_prepare_enable(clk[emi_ahb_gate]);
270 269
diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c
index a854b9cae5ea..c9a06d800f8e 100644
--- a/arch/arm/mach-imx/clk-imx31.c
+++ b/arch/arm/mach-imx/clk-imx31.c
@@ -175,8 +175,7 @@ int __init mx31_clocks_init(unsigned long fref)
175 mx31_revision(); 175 mx31_revision();
176 clk_disable_unprepare(clk[iim_gate]); 176 clk_disable_unprepare(clk[iim_gate]);
177 177
178 mxc_timer_init(NULL, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR), 178 mxc_timer_init(MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR), MX31_INT_GPT);
179 MX31_INT_GPT);
180 179
181 return 0; 180 return 0;
182} 181}
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index a9e60bf7dd75..920a8cc42726 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -267,11 +267,9 @@ int __init mx35_clocks_init()
267 imx_print_silicon_rev("i.MX35", mx35_revision()); 267 imx_print_silicon_rev("i.MX35", mx35_revision());
268 268
269#ifdef CONFIG_MXC_USE_EPIT 269#ifdef CONFIG_MXC_USE_EPIT
270 epit_timer_init(&epit1_clk, 270 epit_timer_init(MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1);
271 MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1);
272#else 271#else
273 mxc_timer_init(NULL, MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), 272 mxc_timer_init(MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT);
274 MX35_INT_GPT);
275#endif 273#endif
276 274
277 return 0; 275 return 0;
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index fcd94f3b0f0e..a2200c77bf70 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -104,12 +104,12 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
104 periph_apm_sel, ARRAY_SIZE(periph_apm_sel)); 104 periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
105 clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1, 105 clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
106 main_bus_sel, ARRAY_SIZE(main_bus_sel)); 106 main_bus_sel, ARRAY_SIZE(main_bus_sel));
107 clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCDR, 1, 1, 107 clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
108 per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel)); 108 per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
109 clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2); 109 clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
110 clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3); 110 clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
111 clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3); 111 clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
112 clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCDR, 1, 0, 112 clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
113 per_root_sel, ARRAY_SIZE(per_root_sel)); 113 per_root_sel, ARRAY_SIZE(per_root_sel));
114 clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3); 114 clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
115 clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28); 115 clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
@@ -172,7 +172,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
172 clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "ipg", MXC_CCM_CCGR2, 12); 172 clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "ipg", MXC_CCM_CCGR2, 12);
173 clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14); 173 clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
174 clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "ipg", MXC_CCM_CCGR2, 16); 174 clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "ipg", MXC_CCM_CCGR2, 16);
175 clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", MXC_CCM_CCGR2, 18); 175 clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per_root", MXC_CCM_CCGR2, 18);
176 clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24); 176 clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
177 clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26); 177 clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
178 clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28); 178 clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
@@ -366,8 +366,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
366 clk_set_rate(clk[esdhc_b_podf], 166250000); 366 clk_set_rate(clk[esdhc_b_podf], 166250000);
367 367
368 /* System timer */ 368 /* System timer */
369 mxc_timer_init(NULL, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), 369 mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT);
370 MX51_INT_GPT);
371 370
372 clk_prepare_enable(clk[iim_gate]); 371 clk_prepare_enable(clk[iim_gate]);
373 imx_print_silicon_rev("i.MX51", mx51_revision()); 372 imx_print_silicon_rev("i.MX51", mx51_revision());
@@ -452,8 +451,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
452 clk_set_rate(clk[esdhc_b_podf], 200000000); 451 clk_set_rate(clk[esdhc_b_podf], 200000000);
453 452
454 /* System timer */ 453 /* System timer */
455 mxc_timer_init(NULL, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), 454 mxc_timer_init(MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), MX53_INT_GPT);
456 MX53_INT_GPT);
457 455
458 clk_prepare_enable(clk[iim_gate]); 456 clk_prepare_enable(clk[iim_gate]);
459 imx_print_silicon_rev("i.MX53", mx53_revision()); 457 imx_print_silicon_rev("i.MX53", mx53_revision());
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index cab02d0a15d6..17dc66a085a5 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -122,10 +122,6 @@ static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5
122 "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0", 122 "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
123 "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio", }; 123 "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio", };
124 124
125static const char * const clks_init_on[] __initconst = {
126 "mmdc_ch0_axi", "mmdc_ch1_axi", "usboh3",
127};
128
129enum mx6q_clks { 125enum mx6q_clks {
130 dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m, 126 dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
131 pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m, 127 pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m,
@@ -161,11 +157,14 @@ enum mx6q_clks {
161 157
162static struct clk *clk[clk_max]; 158static struct clk *clk[clk_max];
163 159
160static enum mx6q_clks const clks_init_on[] __initconst = {
161 mmdc_ch0_axi, mmdc_ch1_axi,
162};
163
164int __init mx6q_clocks_init(void) 164int __init mx6q_clocks_init(void)
165{ 165{
166 struct device_node *np; 166 struct device_node *np;
167 void __iomem *base; 167 void __iomem *base;
168 struct clk *c;
169 int i, irq; 168 int i, irq;
170 169
171 clk[dummy] = imx_clk_fixed("dummy", 0); 170 clk[dummy] = imx_clk_fixed("dummy", 0);
@@ -424,21 +423,14 @@ int __init mx6q_clocks_init(void)
424 clk_register_clkdev(clk[ahb], "ahb", NULL); 423 clk_register_clkdev(clk[ahb], "ahb", NULL);
425 clk_register_clkdev(clk[cko1], "cko1", NULL); 424 clk_register_clkdev(clk[cko1], "cko1", NULL);
426 425
427 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) { 426 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
428 c = clk_get_sys(clks_init_on[i], NULL); 427 clk_prepare_enable(clk[clks_init_on[i]]);
429 if (IS_ERR(c)) {
430 pr_err("%s: failed to get clk %s", __func__,
431 clks_init_on[i]);
432 return PTR_ERR(c);
433 }
434 clk_prepare_enable(c);
435 }
436 428
437 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"); 429 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
438 base = of_iomap(np, 0); 430 base = of_iomap(np, 0);
439 WARN_ON(!base); 431 WARN_ON(!base);
440 irq = irq_of_parse_and_map(np, 0); 432 irq = irq_of_parse_and_map(np, 0);
441 mxc_timer_init(NULL, base, irq); 433 mxc_timer_init(base, irq);
442 434
443 return 0; 435 return 0;
444} 436}