Merge tag 'dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull arm-soc device tree conversions (part 2) from Olof Johansson:
 "These continue the device tree work from part 1, this set is for the
  tegra, mxs and imx platforms, all of which have dependencies on clock
  or pinctrl changes submitted earlier."

Fix up trivial conflicts due to nearby changes in
drivers/{gpio/gpio,i2c/busses/i2c}-mxs.c

* tag 'dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (73 commits)
  ARM: dt: tegra: invert status=disable vs status=okay
  ARM: dt: tegra: consistent basic property ordering
  ARM: dt: tegra: sort nodes based on bus order
  ARM: dt: tegra: remove duplicate device_type property
  ARM: dt: tegra: consistenly use lower-case for hex constants
  ARM: dt: tegra: format regs properties consistently
  ARM: dt: tegra: gpio comment cleanup
  ARM: dt: tegra: remove unnecessary unit addresses
  ARM: dt: tegra: whitespace cleanup
  ARM: dt: tegra cardhu: fix typo in SDHCI node name
  ARM: dt: tegra: cardhu: register core regulator tps62361
  ARM: dt: tegra30.dtsi: Add SMMU node
  ARM: dt: tegra20.dtsi: Add GART node
  ARM: dt: tegra30.dtsi: Add Memory Controller(MC) nodes
  ARM: dt: tegra20.dtsi: Add Memory Controller(MC) nodes
  ARM: dt: tegra: Add device tree support for AHB
  ARM: dts: enable audio support for imx28-evk
  ARM: dts: enable i2c device for imx28-evk
  i2c: mxs: add device tree probe support
  ARM: dts: enable mmc for imx28-evk
  ...

7 files changed, 139 insertions, 25 deletions

diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index 3851d8a27875..05541cf4a878 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -42,4 +42,5 @@ dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb
 dtb-$(CONFIG_MACH_IMX53_DT) += imx53-ard.dtb imx53-evk.dtb \
                                imx53-qsb.dtb imx53-smd.dtb
 dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \
-                           imx6q-sabrelite.dtb
+                           imx6q-sabrelite.dtb \
+                           imx6q-sabresd.dtb \
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index b8a382defb23..fcd94f3b0f0e 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -31,6 +31,11 @@ static const char *per_lp_apm_sel[] = { "main_bus", "lp_apm", };
 static const char *per_root_sel[] = { "per_podf", "ipg", };
 static const char *esdhc_c_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
 static const char *esdhc_d_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
+static const char *ssi_apm_sels[] = { "ckih1", "lp_amp", "ckih2", };
+static const char *ssi_clk_sels[] = { "pll1_sw", "pll2_sw", "pll3_sw", "ssi_apm", };
+static const char *ssi3_clk_sels[] = { "ssi1_root_gate", "ssi2_root_gate", };
+static const char *ssi_ext1_com_sels[] = { "ssi_ext1_podf", "ssi1_root_gate", };
+static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", };
 static const char *emi_slow_sel[] = { "main_bus", "ahb", };
 static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
 static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
@@ -71,6 +76,11 @@ enum imx5_clks {
         pll3_sw, ipu_di0_sel, ipu_di1_sel, tve_ext_sel, mx51_mipi, pll4_sw,
         ldb_di1_sel, di_pll4_podf, ldb_di0_sel, ldb_di0_gate, usb_phy1_gate,
         usb_phy2_gate, per_lp_apm, per_pred1, per_pred2, per_podf, per_root,
+        ssi_apm, ssi1_root_sel, ssi2_root_sel, ssi3_root_sel, ssi_ext1_sel,
+        ssi_ext2_sel, ssi_ext1_com_sel, ssi_ext2_com_sel, ssi1_root_pred,
+        ssi1_root_podf, ssi2_root_pred, ssi2_root_podf, ssi_ext1_pred,
+        ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate,
+        ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
         clk_max
 };
 
@@ -195,6 +205,28 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
         clk[uart5_per_gate] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
         clk[gpc_dvfs] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24);
 
+        clk[ssi_apm] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels));
+        clk[ssi1_root_sel] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
+        clk[ssi2_root_sel] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
+        clk[ssi3_root_sel] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels));
+        clk[ssi_ext1_sel] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
+        clk[ssi_ext2_sel] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
+        clk[ssi_ext1_com_sel] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels));
+        clk[ssi_ext2_com_sel] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels));
+        clk[ssi1_root_pred] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3);
+        clk[ssi1_root_podf] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6);
+        clk[ssi2_root_pred] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3);
+        clk[ssi2_root_podf] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6);
+        clk[ssi_ext1_pred] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3);
+        clk[ssi_ext1_podf] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6);
+        clk[ssi_ext2_pred] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3);
+        clk[ssi_ext2_podf] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6);
+        clk[ssi1_root_gate] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18);
+        clk[ssi2_root_gate] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22);
+        clk[ssi3_root_gate] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
+        clk[ssi_ext1_gate] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
+        clk[ssi_ext2_gate] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
+
         for (i = 0; i < ARRAY_SIZE(clk); i++)
                 if (IS_ERR(clk[i]))
                         pr_err("i.MX5 clk %d: register failed with %ld\n",
@@ -237,6 +269,8 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
         clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
         clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
         clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
+        clk_register_clkdev(clk[ssi_ext1_gate], "ssi_ext1", NULL);
+        clk_register_clkdev(clk[ssi_ext2_gate], "ssi_ext2", NULL);
         clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
         clk_register_clkdev(clk[cpu_podf], "cpu", NULL);
         clk_register_clkdev(clk[iim_gate], "iim", NULL);
@@ -320,6 +354,9 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3");
         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3");
         clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3");
+        clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "83fcc000.ssi");
+        clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "70014000.ssi");
+        clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "83fe8000.ssi");
 
         /* set the usboh3 parent to pll2_sw */
         clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
@@ -406,6 +443,9 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3");
         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3");
         clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3");
+        clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi");
+        clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi");
+        clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi");
 
         /* set SDHC root clock to 200MHZ*/
         clk_set_rate(clk[esdhc_a_podf], 200000000);
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index f40a35da2e5c..cab02d0a15d6 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -155,7 +155,8 @@ enum mx6q_clks {
         gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
         ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
         usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
-        pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, clk_max
+        pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg,
+        ssi2_ipg, ssi3_ipg, clk_max
 };
 
 static struct clk *clk[clk_max];
@@ -367,9 +368,9 @@ int __init mx6q_clocks_init(void)
         clk[sata]         = imx_clk_gate2("sata",          "ipg",               base + 0x7c, 4);
         clk[sdma]         = imx_clk_gate2("sdma",          "ahb",               base + 0x7c, 6);
         clk[spba]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
-        clk[ssi1]         = imx_clk_gate2("ssi1",          "ssi1_podf",         base + 0x7c, 18);
-        clk[ssi2]         = imx_clk_gate2("ssi2",          "ssi2_podf",         base + 0x7c, 20);
-        clk[ssi3]         = imx_clk_gate2("ssi3",          "ssi3_podf",         base + 0x7c, 22);
+        clk[ssi1_ipg]     = imx_clk_gate2("ssi1_ipg",      "ipg",               base + 0x7c, 18);
+        clk[ssi2_ipg]     = imx_clk_gate2("ssi2_ipg",      "ipg",               base + 0x7c, 20);
+        clk[ssi3_ipg]     = imx_clk_gate2("ssi3_ipg",      "ipg",               base + 0x7c, 22);
         clk[uart_ipg]     = imx_clk_gate2("uart_ipg",      "ipg",               base + 0x7c, 24);
         clk[uart_serial]  = imx_clk_gate2("uart_serial",   "uart_serial_podf",  base + 0x7c, 26);
         clk[usboh3]       = imx_clk_gate2("usboh3",        "ipg",               base + 0x80, 0);
@@ -392,17 +393,17 @@ int __init mx6q_clocks_init(void)
         clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
         clk_register_clkdev(clk[twd], NULL, "smp_twd");
         clk_register_clkdev(clk[usboh3], NULL, "usboh3");
-        clk_register_clkdev(clk[uart_serial], "per", "2020000.uart");
-        clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.uart");
-        clk_register_clkdev(clk[uart_serial], "per", "21e8000.uart");
-        clk_register_clkdev(clk[uart_ipg], "ipg", "21e8000.uart");
-        clk_register_clkdev(clk[uart_serial], "per", "21ec000.uart");
-        clk_register_clkdev(clk[uart_ipg], "ipg", "21ec000.uart");
-        clk_register_clkdev(clk[uart_serial], "per", "21f0000.uart");
-        clk_register_clkdev(clk[uart_ipg], "ipg", "21f0000.uart");
-        clk_register_clkdev(clk[uart_serial], "per", "21f4000.uart");
-        clk_register_clkdev(clk[uart_ipg], "ipg", "21f4000.uart");
-        clk_register_clkdev(clk[enet], NULL, "2188000.enet");
+        clk_register_clkdev(clk[uart_serial], "per", "2020000.serial");
+        clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial");
+        clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial");
+        clk_register_clkdev(clk[uart_ipg], "ipg", "21e8000.serial");
+        clk_register_clkdev(clk[uart_serial], "per", "21ec000.serial");
+        clk_register_clkdev(clk[uart_ipg], "ipg", "21ec000.serial");
+        clk_register_clkdev(clk[uart_serial], "per", "21f0000.serial");
+        clk_register_clkdev(clk[uart_ipg], "ipg", "21f0000.serial");
+        clk_register_clkdev(clk[uart_serial], "per", "21f4000.serial");
+        clk_register_clkdev(clk[uart_ipg], "ipg", "21f4000.serial");
+        clk_register_clkdev(clk[enet], NULL, "2188000.ethernet");
         clk_register_clkdev(clk[usdhc1], NULL, "2190000.usdhc");
         clk_register_clkdev(clk[usdhc2], NULL, "2194000.usdhc");
         clk_register_clkdev(clk[usdhc3], NULL, "2198000.usdhc");
@@ -418,6 +419,10 @@ int __init mx6q_clocks_init(void)
         clk_register_clkdev(clk[sdma], NULL, "20ec000.sdma");
         clk_register_clkdev(clk[dummy], NULL, "20bc000.wdog");
         clk_register_clkdev(clk[dummy], NULL, "20c0000.wdog");
+        clk_register_clkdev(clk[ssi1_ipg], NULL, "2028000.ssi");
+        clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
+        clk_register_clkdev(clk[ahb], "ahb", NULL);
+        clk_register_clkdev(clk[cko1], "cko1", NULL);
 
         for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) {
                 c = clk_get_sys(clks_init_on[i], NULL);
diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/imx53-dt.c
index 574eca4b89a5..eb04b6248e48 100644
--- a/arch/arm/mach-imx/imx53-dt.c
+++ b/arch/arm/mach-imx/imx53-dt.c
@@ -10,6 +10,9 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
@@ -81,6 +84,19 @@ static const struct of_device_id imx53_iomuxc_of_match[] __initconst = {
         { /* sentinel */ }
 };
 
+static void __init imx53_qsb_init(void)
+{
+        struct clk *clk;
+
+        clk = clk_get_sys(NULL, "ssi_ext1");
+        if (IS_ERR(clk)) {
+                pr_err("failed to get clk ssi_ext1\n");
+                return;
+        }
+
+        clk_register_clkdev(clk, NULL, "0-000a");
+}
+
 static void __init imx53_dt_init(void)
 {
         struct device_node *node;
@@ -99,6 +115,9 @@ static void __init imx53_dt_init(void)
                 of_node_put(node);
         }
 
+        if (of_machine_is_compatible("fsl,imx53-qsb"))
+                imx53_qsb_init();
+
         of_platform_populate(NULL, of_default_bus_match_table,
                              imx53_auxdata_lookup, NULL);
 }
diff --git a/arch/arm/mach-imx/lluart.c b/arch/arm/mach-imx/lluart.c
index 0213f8dcee81..c40a34c00489 100644
--- a/arch/arm/mach-imx/lluart.c
+++ b/arch/arm/mach-imx/lluart.c
@@ -17,6 +17,12 @@
 #include <mach/hardware.h>
 
 static struct map_desc imx_lluart_desc = {
+#ifdef CONFIG_DEBUG_IMX6Q_UART2
+        .virtual        = MX6Q_IO_P2V(MX6Q_UART2_BASE_ADDR),
+        .pfn            = __phys_to_pfn(MX6Q_UART2_BASE_ADDR),
+        .length         = MX6Q_UART2_SIZE,
+        .type           = MT_DEVICE,
+#endif
 #ifdef CONFIG_DEBUG_IMX6Q_UART4
         .virtual        = MX6Q_IO_P2V(MX6Q_UART4_BASE_ADDR),
         .pfn            = __phys_to_pfn(MX6Q_UART4_BASE_ADDR),
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 3df360a52c17..b47e98b7d539 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -10,6 +10,8 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
+#include <linux/clk.h>
+#include <linux/clkdev.h>
 #include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/io.h>
@@ -64,18 +66,53 @@ soft:
 /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
 static int ksz9021rn_phy_fixup(struct phy_device *phydev)
 {
-        /* min rx data delay */
-        phy_write(phydev, 0x0b, 0x8105);
-        phy_write(phydev, 0x0c, 0x0000);
+        if (IS_ENABLED(CONFIG_PHYLIB)) {
+                /* min rx data delay */
+                phy_write(phydev, 0x0b, 0x8105);
+                phy_write(phydev, 0x0c, 0x0000);
 
-        /* max rx/tx clock delay, min rx/tx control delay */
-        phy_write(phydev, 0x0b, 0x8104);
-        phy_write(phydev, 0x0c, 0xf0f0);
-        phy_write(phydev, 0x0b, 0x104);
+                /* max rx/tx clock delay, min rx/tx control delay */
+                phy_write(phydev, 0x0b, 0x8104);
+                phy_write(phydev, 0x0c, 0xf0f0);
+                phy_write(phydev, 0x0b, 0x104);
+        }
 
         return 0;
 }
 
+static void __init imx6q_sabrelite_cko1_setup(void)
+{
+        struct clk *cko1_sel, *ahb, *cko1;
+        unsigned long rate;
+
+        cko1_sel = clk_get_sys(NULL, "cko1_sel");
+        ahb = clk_get_sys(NULL, "ahb");
+        cko1 = clk_get_sys(NULL, "cko1");
+        if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) {
+                pr_err("cko1 setup failed!\n");
+                goto put_clk;
+        }
+        clk_set_parent(cko1_sel, ahb);
+        rate = clk_round_rate(cko1, 16000000);
+        clk_set_rate(cko1, rate);
+        clk_register_clkdev(cko1, NULL, "0-000a");
+put_clk:
+        if (!IS_ERR(cko1_sel))
+                clk_put(cko1_sel);
+        if (!IS_ERR(ahb))
+                clk_put(ahb);
+        if (!IS_ERR(cko1))
+                clk_put(cko1);
+}
+
+static void __init imx6q_sabrelite_init(void)
+{
+        if (IS_ENABLED(CONFIG_PHYLIB))
+                phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
+                                ksz9021rn_phy_fixup);
+        imx6q_sabrelite_cko1_setup();
+}
+
 static void __init imx6q_init_machine(void)
 {
         /*
@@ -85,8 +122,7 @@ static void __init imx6q_init_machine(void)
         pinctrl_provide_dummies();
 
         if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
-                phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
-                                           ksz9021rn_phy_fixup);
+                imx6q_sabrelite_init();
 
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 
@@ -139,6 +175,7 @@ static struct sys_timer imx6q_timer = {
 static const char *imx6q_dt_compat[] __initdata = {
         "fsl,imx6q-arm2",
         "fsl,imx6q-sabrelite",
+        "fsl,imx6q-sabresd",
         "fsl,imx6q",
         NULL,
 };
diff --git a/arch/arm/mach-imx/mach-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c
index e4b822e9f719..517672ebcbc5 100644
--- a/arch/arm/mach-imx/mach-mx51_babbage.c
+++ b/arch/arm/mach-imx/mach-mx51_babbage.c
@@ -163,6 +163,12 @@ static iomux_v3_cfg_t mx51babbage_pads[] = {
         MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
         MX51_PAD_CSPI1_SS0__GPIO4_24,
         MX51_PAD_CSPI1_SS1__GPIO4_25,
+
+        /* Audio */
+        MX51_PAD_AUD3_BB_TXD__AUD3_TXD,
+        MX51_PAD_AUD3_BB_RXD__AUD3_RXD,
+        MX51_PAD_AUD3_BB_CK__AUD3_TXC,
+        MX51_PAD_AUD3_BB_FS__AUD3_TXFS,
 };
 
 /* Serial ports */