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authorLinus Walleij <linus.walleij@linaro.org>2013-10-08 07:27:11 -0400
committerLinus Walleij <linus.walleij@linaro.org>2013-10-08 07:27:11 -0400
commitbfabb59433fc18ff78d2818e10e212d0f85d56ae (patch)
treedd7cbead179c09c62627a84c16c802d99095ba6e /arch/arm/mach-imx/system.c
parent6a08a92ec45782e5543addf5f8785e2560a078f6 (diff)
parentd0e639c9e06d44e713170031fe05fb60ebe680af (diff)
Merge tag 'v3.12-rc4' into devel
Linux 3.12-rc4
Diffstat (limited to 'arch/arm/mach-imx/system.c')
-rw-r--r--arch/arm/mach-imx/system.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 64ff37ea72b1..80c177c36c5f 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -117,6 +117,17 @@ void __init imx_init_l2cache(void)
117 /* Configure the L2 PREFETCH and POWER registers */ 117 /* Configure the L2 PREFETCH and POWER registers */
118 val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL); 118 val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
119 val |= 0x70800000; 119 val |= 0x70800000;
120 /*
121 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
122 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
123 * But according to ARM PL310 errata: 752271
124 * ID: 752271: Double linefill feature can cause data corruption
125 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
126 * Workaround: The only workaround to this erratum is to disable the
127 * double linefill feature. This is the default behavior.
128 */
129 if (cpu_is_imx6q())
130 val &= ~(1 << 30 | 1 << 23);
120 writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL); 131 writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
121 val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN; 132 val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
122 writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL); 133 writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);