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authorShawn Guo <shawn.guo@linaro.org>2011-12-08 18:51:26 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2012-01-05 07:57:22 -0500
commit0575fb754dbfc32a01f297e778533340a533ec68 (patch)
tree1b416ae6fca7d905003e64c928c7d37032acfd15 /arch/arm/mach-imx/src.c
parentf88b8979d26615ce68772cebc85c3b556571afca (diff)
ARM: 7198/1: arm/imx6: add restart support for imx6q
The restart support was missed from the initial imx6q submission. The mxc_restart() does not work for imx6q. Instead, this patch adds the restart for imx6q. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-imx/src.c')
-rw-r--r--arch/arm/mach-imx/src.c23
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index a8e33681b732..4bde04f99e38 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -19,6 +19,7 @@
19 19
20#define SRC_SCR 0x000 20#define SRC_SCR 0x000
21#define SRC_GPR1 0x020 21#define SRC_GPR1 0x020
22#define BP_SRC_SCR_WARM_RESET_ENABLE 0
22#define BP_SRC_SCR_CORE1_RST 14 23#define BP_SRC_SCR_CORE1_RST 14
23#define BP_SRC_SCR_CORE1_ENABLE 22 24#define BP_SRC_SCR_CORE1_ENABLE 22
24 25
@@ -46,11 +47,33 @@ void imx_set_cpu_jump(int cpu, void *jump_addr)
46 src_base + SRC_GPR1 + cpu * 8); 47 src_base + SRC_GPR1 + cpu * 8);
47} 48}
48 49
50void imx_src_prepare_restart(void)
51{
52 u32 val;
53
54 /* clear enable bits of secondary cores */
55 val = readl_relaxed(src_base + SRC_SCR);
56 val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE);
57 writel_relaxed(val, src_base + SRC_SCR);
58
59 /* clear persistent entry register of primary core */
60 writel_relaxed(0, src_base + SRC_GPR1);
61}
62
49void __init imx_src_init(void) 63void __init imx_src_init(void)
50{ 64{
51 struct device_node *np; 65 struct device_node *np;
66 u32 val;
52 67
53 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-src"); 68 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-src");
54 src_base = of_iomap(np, 0); 69 src_base = of_iomap(np, 0);
55 WARN_ON(!src_base); 70 WARN_ON(!src_base);
71
72 /*
73 * force warm reset sources to generate cold reset
74 * for a more reliable restart
75 */
76 val = readl_relaxed(src_base + SRC_SCR);
77 val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE);
78 writel_relaxed(val, src_base + SRC_SCR);
56} 79}