diff options
author | Arnd Bergmann <arnd@arndb.de> | 2013-02-19 11:22:34 -0500 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2013-02-19 11:22:34 -0500 |
commit | 4a9226a3d192c38493106dcaf5f47f291ede9ed5 (patch) | |
tree | f5791e3147b713e02b69c528644a8a2d41b3ea7f /arch/arm/mach-imx/clk-imx6q.c | |
parent | 7839c281edd9f4744be58ff0b29aabc64aabde31 (diff) | |
parent | e5f9dec8ff5ff3f6254412abed1f68d758f6616b (diff) |
Merge branch 'imx/cpuidle' into late/dt
This resolves one non-obvious merge conflict between the imx cpuidle
patches and the imx DT changes for 3.9.
Conflicts:
arch/arm/mach-imx/mach-imx6q.c
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-imx/clk-imx6q.c')
-rw-r--r-- | arch/arm/mach-imx/clk-imx6q.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 905bec2a08a4..7b025ee528a5 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c | |||
@@ -54,9 +54,18 @@ | |||
54 | #define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26) | 54 | #define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26) |
55 | #define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) | 55 | #define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) |
56 | 56 | ||
57 | #define CGPR 0x64 | ||
58 | #define BM_CGPR_CHICKEN_BIT (0x1 << 17) | ||
59 | |||
57 | static void __iomem *ccm_base; | 60 | static void __iomem *ccm_base; |
58 | 61 | ||
59 | void __init imx6q_clock_map_io(void) { } | 62 | void imx6q_set_chicken_bit(void) |
63 | { | ||
64 | u32 val = readl_relaxed(ccm_base + CGPR); | ||
65 | |||
66 | val |= BM_CGPR_CHICKEN_BIT; | ||
67 | writel_relaxed(val, ccm_base + CGPR); | ||
68 | } | ||
60 | 69 | ||
61 | int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) | 70 | int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) |
62 | { | 71 | { |
@@ -68,6 +77,7 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) | |||
68 | break; | 77 | break; |
69 | case WAIT_UNCLOCKED: | 78 | case WAIT_UNCLOCKED: |
70 | val |= 0x1 << BP_CLPCR_LPM; | 79 | val |= 0x1 << BP_CLPCR_LPM; |
80 | val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM; | ||
71 | break; | 81 | break; |
72 | case STOP_POWER_ON: | 82 | case STOP_POWER_ON: |
73 | val |= 0x2 << BP_CLPCR_LPM; | 83 | val |= 0x2 << BP_CLPCR_LPM; |