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authorAlexander Shiyan <shc_work@mail.ru>2014-06-07 12:09:25 -0400
committerShawn Guo <shawn.guo@freescale.com>2014-07-18 04:10:11 -0400
commitbb9c3398efd109e48932af46c3e1fed10adddc17 (patch)
tree3e01455de63201727c24dbddf9dddb0310fb762a /arch/arm/mach-imx/clk-imx27.c
parentd7f9891500aa23bd5d29c37621be82a90c4e25d9 (diff)
ARM: i.MX27 clk: Separate DT and non-DT init procedure
This patch separates DT and non-DT clock initialization procedure, so we can avoid a lot of unneeded clk_register_clkdev() for DT case. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch/arm/mach-imx/clk-imx27.c')
-rw-r--r--arch/arm/mach-imx/clk-imx27.c39
1 files changed, 24 insertions, 15 deletions
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index 317a662626d6..f5a6a3fd541a 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -89,10 +89,9 @@ enum mx27_clks {
89static struct clk *clk[clk_max]; 89static struct clk *clk[clk_max];
90static struct clk_onecell_data clk_data; 90static struct clk_onecell_data clk_data;
91 91
92int __init mx27_clocks_init(unsigned long fref) 92static void __init _mx27_clocks_init(unsigned long fref)
93{ 93{
94 int i; 94 unsigned i;
95 struct device_node *np;
96 95
97 clk[dummy] = imx_clk_fixed("dummy", 0); 96 clk[dummy] = imx_clk_fixed("dummy", 0);
98 clk[ckih] = imx_clk_fixed("ckih", fref); 97 clk[ckih] = imx_clk_fixed("ckih", fref);
@@ -206,12 +205,16 @@ int __init mx27_clocks_init(unsigned long fref)
206 pr_err("i.MX27 clk %d: register failed with %ld\n", 205 pr_err("i.MX27 clk %d: register failed with %ld\n",
207 i, PTR_ERR(clk[i])); 206 i, PTR_ERR(clk[i]));
208 207
209 np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm"); 208 clk_register_clkdev(clk[cpu_div], NULL, "cpu0");
210 if (np) { 209
211 clk_data.clks = clk; 210 clk_prepare_enable(clk[emi_ahb_gate]);
212 clk_data.clk_num = ARRAY_SIZE(clk); 211
213 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 212 imx_print_silicon_rev("i.MX27", mx27_revision());
214 } 213}
214
215int __init mx27_clocks_init(unsigned long fref)
216{
217 _mx27_clocks_init(fref);
215 218
216 clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0"); 219 clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
217 clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.0"); 220 clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.0");
@@ -274,14 +277,9 @@ int __init mx27_clocks_init(unsigned long fref)
274 clk_register_clkdev(clk[emma_ipg_gate], "emma-ipg", "imx27-camera.0"); 277 clk_register_clkdev(clk[emma_ipg_gate], "emma-ipg", "imx27-camera.0");
275 clk_register_clkdev(clk[emma_ahb_gate], "ahb", "m2m-emmaprp.0"); 278 clk_register_clkdev(clk[emma_ahb_gate], "ahb", "m2m-emmaprp.0");
276 clk_register_clkdev(clk[emma_ipg_gate], "ipg", "m2m-emmaprp.0"); 279 clk_register_clkdev(clk[emma_ipg_gate], "ipg", "m2m-emmaprp.0");
277 clk_register_clkdev(clk[cpu_div], NULL, "cpu0");
278 280
279 mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1); 281 mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
280 282
281 clk_prepare_enable(clk[emi_ahb_gate]);
282
283 imx_print_silicon_rev("i.MX27", mx27_revision());
284
285 return 0; 283 return 0;
286} 284}
287 285
@@ -298,5 +296,16 @@ int __init mx27_clocks_init_dt(void)
298 break; 296 break;
299 } 297 }
300 298
301 return mx27_clocks_init(fref); 299 _mx27_clocks_init(fref);
300
301 np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm");
302 BUG_ON(!np);
303
304 clk_data.clks = clk;
305 clk_data.clk_num = ARRAY_SIZE(clk);
306 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
307
308 mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx1-gpt"));
309
310 return 0;
302} 311}