diff options
author | Alexander Shiyan <shc_work@mail.ru> | 2014-07-05 01:36:08 -0400 |
---|---|---|
committer | Shawn Guo <shawn.guo@freescale.com> | 2014-07-18 04:11:38 -0400 |
commit | 2d130d9d259a7692a910df181bb256f742b5d2e2 (patch) | |
tree | 7a4bf346f6de77a71fcf76ae6c46b676e245d530 /arch/arm/mach-imx/clk-imx27.c | |
parent | e8e3faa0391a81a40a9add37d90bcdfbd9a5b942 (diff) |
ARM: i.MX27 clk: Remove unused definitions
This patch removes definitions which not used anywhere in the driver.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch/arm/mach-imx/clk-imx27.c')
-rw-r--r-- | arch/arm/mach-imx/clk-imx27.c | 25 |
1 files changed, 0 insertions, 25 deletions
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c index ef7001c190a7..fcfb81b881af 100644 --- a/arch/arm/mach-imx/clk-imx27.c +++ b/arch/arm/mach-imx/clk-imx27.c | |||
@@ -18,36 +18,11 @@ static void __iomem *ccm __initdata; | |||
18 | #define CCM_MPCTL1 (ccm + 0x08) | 18 | #define CCM_MPCTL1 (ccm + 0x08) |
19 | #define CCM_SPCTL0 (ccm + 0x0c) | 19 | #define CCM_SPCTL0 (ccm + 0x0c) |
20 | #define CCM_SPCTL1 (ccm + 0x10) | 20 | #define CCM_SPCTL1 (ccm + 0x10) |
21 | #define CCM_OSC26MCTL (ccm + 0x14) | ||
22 | #define CCM_PCDR0 (ccm + 0x18) | 21 | #define CCM_PCDR0 (ccm + 0x18) |
23 | #define CCM_PCDR1 (ccm + 0x1c) | 22 | #define CCM_PCDR1 (ccm + 0x1c) |
24 | #define CCM_PCCR0 (ccm + 0x20) | 23 | #define CCM_PCCR0 (ccm + 0x20) |
25 | #define CCM_PCCR1 (ccm + 0x24) | 24 | #define CCM_PCCR1 (ccm + 0x24) |
26 | #define CCM_CCSR (ccm + 0x28) | 25 | #define CCM_CCSR (ccm + 0x28) |
27 | #define CCM_PMCTL (ccm + 0x2c) | ||
28 | #define CCM_PMCOUNT (ccm + 0x30) | ||
29 | #define CCM_WKGDCTL (ccm + 0x34) | ||
30 | |||
31 | #define CCM_CSCR_UPDATE_DIS (1 << 31) | ||
32 | #define CCM_CSCR_SSI2 (1 << 23) | ||
33 | #define CCM_CSCR_SSI1 (1 << 22) | ||
34 | #define CCM_CSCR_VPU (1 << 21) | ||
35 | #define CCM_CSCR_MSHC (1 << 20) | ||
36 | #define CCM_CSCR_SPLLRES (1 << 19) | ||
37 | #define CCM_CSCR_MPLLRES (1 << 18) | ||
38 | #define CCM_CSCR_SP (1 << 17) | ||
39 | #define CCM_CSCR_MCU (1 << 16) | ||
40 | #define CCM_CSCR_OSC26MDIV (1 << 4) | ||
41 | #define CCM_CSCR_OSC26M (1 << 3) | ||
42 | #define CCM_CSCR_FPM (1 << 2) | ||
43 | #define CCM_CSCR_SPEN (1 << 1) | ||
44 | #define CCM_CSCR_MPEN (1 << 0) | ||
45 | |||
46 | /* i.MX27 TO 2+ */ | ||
47 | #define CCM_CSCR_ARM_SRC (1 << 15) | ||
48 | |||
49 | #define CCM_SPCTL1_LF (1 << 15) | ||
50 | #define CCM_SPCTL1_BRMO (1 << 6) | ||
51 | 26 | ||
52 | static const char *vpu_sel_clks[] = { "spll", "mpll_main2", }; | 27 | static const char *vpu_sel_clks[] = { "spll", "mpll_main2", }; |
53 | static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", }; | 28 | static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", }; |