ARM: imx: enable RBC to support anatop LPM mode

RBC is to control whether some ANATOP sub modules
can enter lpm mode when SOC is into STOP mode, if
RBC is enabled and PMIC_VSTBY_REQ is set, ANATOP
will have below behaviors:

1. Digital LDOs(CORE, SOC and PU) are bypassed;
2. Analog LDOs(1P1, 2P5, 3P0) are disabled;

As the 2P5 is necessary for DRAM IO pre-drive in
STOP mode, so we need to enable weak 2P5 in STOP
mode when 2P5 LDO is disabled.

For RBC settings, there are some rules as below
due to hardware design:

1. All interrupts must be masked during operating
   RBC registers;
2. At least 2 CKIL(32K) cycles is needed after the
   RBC setting is changed.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

1 files changed, 19 insertions, 0 deletions

diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c
index b396b92526d3..8b18b3c3bcf0 100644
--- a/arch/arm/mach-imx/anatop.c
+++ b/arch/arm/mach-imx/anatop.c
@@ -19,17 +19,34 @@
 #define REG_SET         0x4
 #define REG_CLR         0x8
 
+#define ANADIG_REG_2P5          0x130
 #define ANADIG_REG_CORE         0x140
+#define ANADIG_ANA_MISC0        0x150
 #define ANADIG_USB1_CHRG_DETECT 0x1b0
 #define ANADIG_USB2_CHRG_DETECT 0x210
 #define ANADIG_DIGPROG          0x260
 
+#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG    0x40000
 #define BM_ANADIG_REG_CORE_FET_ODRIVE           0x20000000
+#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG    0x1000
 #define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B    0x80000
 #define BM_ANADIG_USB_CHRG_DETECT_EN_B          0x100000
 
 static struct regmap *anatop;
 
+static void imx_anatop_enable_weak2p5(bool enable)
+{
+        u32 reg, val;
+
+        regmap_read(anatop, ANADIG_ANA_MISC0, &val);
+
+        /* can only be enabled when stop_mode_config is clear. */
+        reg = ANADIG_REG_2P5;
+        reg += (enable && (val & BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) == 0) ?
+                REG_SET : REG_CLR;
+        regmap_write(anatop, reg, BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG);
+}
+
 static void imx_anatop_enable_fet_odrive(bool enable)
 {
         regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR),
@@ -38,12 +55,14 @@ static void imx_anatop_enable_fet_odrive(bool enable)
 
 void imx_anatop_pre_suspend(void)
 {
+        imx_anatop_enable_weak2p5(true);
         imx_anatop_enable_fet_odrive(true);
 }
 
 void imx_anatop_post_resume(void)
 {
         imx_anatop_enable_fet_odrive(false);
+        imx_anatop_enable_weak2p5(false);
 }
 
 void imx_anatop_usb_chrg_detect_disable(void)