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authorTomasz Figa <t.figa@samsung.com>2013-06-14 20:02:50 -0400
committerKukjin Kim <kgene.kim@samsung.com>2013-06-14 20:32:49 -0400
commitd238757954f0e0823b4e7dc83c3808f031f84d7d (patch)
treee6322829c06453304e9d703f66c456e510948aff /arch/arm/mach-exynos
parentc2f96de7d0a4b8bb99d5a1ad1056d08d24614ae8 (diff)
ARM: EXYNOS: Remove legacy EINT initialization code
This patch removes legacy EINT initialization code that was used to handle external interrupts when booting with ATAGS, which is not supported any more. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos')
-rw-r--r--arch/arm/mach-exynos/common.c307
1 files changed, 0 insertions, 307 deletions
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index cb07f4a03483..488d9bd68d2c 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -615,310 +615,3 @@ static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
615 615
616 s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no); 616 s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
617} 617}
618
619static void __iomem *exynos_eint_base;
620
621static DEFINE_SPINLOCK(eint_lock);
622
623static unsigned int eint0_15_data[16];
624
625static inline int exynos4_irq_to_gpio(unsigned int irq)
626{
627 if (irq < IRQ_EINT(0))
628 return -EINVAL;
629
630 irq -= IRQ_EINT(0);
631 if (irq < 8)
632 return EXYNOS4_GPX0(irq);
633
634 irq -= 8;
635 if (irq < 8)
636 return EXYNOS4_GPX1(irq);
637
638 irq -= 8;
639 if (irq < 8)
640 return EXYNOS4_GPX2(irq);
641
642 irq -= 8;
643 if (irq < 8)
644 return EXYNOS4_GPX3(irq);
645
646 return -EINVAL;
647}
648
649static inline int exynos5_irq_to_gpio(unsigned int irq)
650{
651 if (irq < IRQ_EINT(0))
652 return -EINVAL;
653
654 irq -= IRQ_EINT(0);
655 if (irq < 8)
656 return EXYNOS5_GPX0(irq);
657
658 irq -= 8;
659 if (irq < 8)
660 return EXYNOS5_GPX1(irq);
661
662 irq -= 8;
663 if (irq < 8)
664 return EXYNOS5_GPX2(irq);
665
666 irq -= 8;
667 if (irq < 8)
668 return EXYNOS5_GPX3(irq);
669
670 return -EINVAL;
671}
672
673static unsigned int exynos4_eint0_15_src_int[16] = {
674 EXYNOS4_IRQ_EINT0,
675 EXYNOS4_IRQ_EINT1,
676 EXYNOS4_IRQ_EINT2,
677 EXYNOS4_IRQ_EINT3,
678 EXYNOS4_IRQ_EINT4,
679 EXYNOS4_IRQ_EINT5,
680 EXYNOS4_IRQ_EINT6,
681 EXYNOS4_IRQ_EINT7,
682 EXYNOS4_IRQ_EINT8,
683 EXYNOS4_IRQ_EINT9,
684 EXYNOS4_IRQ_EINT10,
685 EXYNOS4_IRQ_EINT11,
686 EXYNOS4_IRQ_EINT12,
687 EXYNOS4_IRQ_EINT13,
688 EXYNOS4_IRQ_EINT14,
689 EXYNOS4_IRQ_EINT15,
690};
691
692static unsigned int exynos5_eint0_15_src_int[16] = {
693 EXYNOS5_IRQ_EINT0,
694 EXYNOS5_IRQ_EINT1,
695 EXYNOS5_IRQ_EINT2,
696 EXYNOS5_IRQ_EINT3,
697 EXYNOS5_IRQ_EINT4,
698 EXYNOS5_IRQ_EINT5,
699 EXYNOS5_IRQ_EINT6,
700 EXYNOS5_IRQ_EINT7,
701 EXYNOS5_IRQ_EINT8,
702 EXYNOS5_IRQ_EINT9,
703 EXYNOS5_IRQ_EINT10,
704 EXYNOS5_IRQ_EINT11,
705 EXYNOS5_IRQ_EINT12,
706 EXYNOS5_IRQ_EINT13,
707 EXYNOS5_IRQ_EINT14,
708 EXYNOS5_IRQ_EINT15,
709};
710static inline void exynos_irq_eint_mask(struct irq_data *data)
711{
712 u32 mask;
713
714 spin_lock(&eint_lock);
715 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
716 mask |= EINT_OFFSET_BIT(data->irq);
717 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
718 spin_unlock(&eint_lock);
719}
720
721static void exynos_irq_eint_unmask(struct irq_data *data)
722{
723 u32 mask;
724
725 spin_lock(&eint_lock);
726 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
727 mask &= ~(EINT_OFFSET_BIT(data->irq));
728 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
729 spin_unlock(&eint_lock);
730}
731
732static inline void exynos_irq_eint_ack(struct irq_data *data)
733{
734 __raw_writel(EINT_OFFSET_BIT(data->irq),
735 EINT_PEND(exynos_eint_base, data->irq));
736}
737
738static void exynos_irq_eint_maskack(struct irq_data *data)
739{
740 exynos_irq_eint_mask(data);
741 exynos_irq_eint_ack(data);
742}
743
744static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
745{
746 int offs = EINT_OFFSET(data->irq);
747 int shift;
748 u32 ctrl, mask;
749 u32 newvalue = 0;
750
751 switch (type) {
752 case IRQ_TYPE_EDGE_RISING:
753 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
754 break;
755
756 case IRQ_TYPE_EDGE_FALLING:
757 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
758 break;
759
760 case IRQ_TYPE_EDGE_BOTH:
761 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
762 break;
763
764 case IRQ_TYPE_LEVEL_LOW:
765 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
766 break;
767
768 case IRQ_TYPE_LEVEL_HIGH:
769 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
770 break;
771
772 default:
773 printk(KERN_ERR "No such irq type %d", type);
774 return -EINVAL;
775 }
776
777 shift = (offs & 0x7) * 4;
778 mask = 0x7 << shift;
779
780 spin_lock(&eint_lock);
781 ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
782 ctrl &= ~mask;
783 ctrl |= newvalue << shift;
784 __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
785 spin_unlock(&eint_lock);
786
787 if (soc_is_exynos5250())
788 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
789 else
790 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
791
792 return 0;
793}
794
795static struct irq_chip exynos_irq_eint = {
796 .name = "exynos-eint",
797 .irq_mask = exynos_irq_eint_mask,
798 .irq_unmask = exynos_irq_eint_unmask,
799 .irq_mask_ack = exynos_irq_eint_maskack,
800 .irq_ack = exynos_irq_eint_ack,
801 .irq_set_type = exynos_irq_eint_set_type,
802#ifdef CONFIG_PM
803 .irq_set_wake = s3c_irqext_wake,
804#endif
805};
806
807/*
808 * exynos4_irq_demux_eint
809 *
810 * This function demuxes the IRQ from from EINTs 16 to 31.
811 * It is designed to be inlined into the specific handler
812 * s5p_irq_demux_eintX_Y.
813 *
814 * Each EINT pend/mask registers handle eight of them.
815 */
816static inline void exynos_irq_demux_eint(unsigned int start)
817{
818 unsigned int irq;
819
820 u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
821 u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
822
823 status &= ~mask;
824 status &= 0xff;
825
826 while (status) {
827 irq = fls(status) - 1;
828 generic_handle_irq(irq + start);
829 status &= ~(1 << irq);
830 }
831}
832
833static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
834{
835 struct irq_chip *chip = irq_get_chip(irq);
836 chained_irq_enter(chip, desc);
837 exynos_irq_demux_eint(IRQ_EINT(16));
838 exynos_irq_demux_eint(IRQ_EINT(24));
839 chained_irq_exit(chip, desc);
840}
841
842static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
843{
844 u32 *irq_data = irq_get_handler_data(irq);
845 struct irq_chip *chip = irq_get_chip(irq);
846
847 chained_irq_enter(chip, desc);
848 generic_handle_irq(*irq_data);
849 chained_irq_exit(chip, desc);
850}
851
852static int __init exynos_init_irq_eint(void)
853{
854 int irq;
855
856#ifdef CONFIG_PINCTRL_SAMSUNG
857 /*
858 * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
859 * functionality along with support for external gpio and wakeup
860 * interrupts. If the samsung pinctrl driver is enabled and includes
861 * the wakeup interrupt support, then the setting up external wakeup
862 * interrupts here can be skipped. This check here is temporary to
863 * allow exynos4 platforms that do not use Samsung pinctrl driver to
864 * co-exist with platforms that do. When all of the Samsung Exynos4
865 * platforms switch over to using the pinctrl driver, the wakeup
866 * interrupt support code here can be completely removed.
867 */
868 static const struct of_device_id exynos_pinctrl_ids[] = {
869 { .compatible = "samsung,exynos4210-pinctrl", },
870 { .compatible = "samsung,exynos4x12-pinctrl", },
871 { .compatible = "samsung,exynos5250-pinctrl", },
872 };
873 struct device_node *pctrl_np, *wkup_np;
874 const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
875
876 for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
877 if (of_device_is_available(pctrl_np)) {
878 wkup_np = of_find_compatible_node(pctrl_np, NULL,
879 wkup_compat);
880 if (wkup_np)
881 return -ENODEV;
882 }
883 }
884#endif
885 if (soc_is_exynos5440())
886 return 0;
887
888 if (soc_is_exynos5250())
889 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
890 else
891 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
892
893 if (exynos_eint_base == NULL) {
894 pr_err("unable to ioremap for EINT base address\n");
895 return -ENOMEM;
896 }
897
898 for (irq = 0 ; irq <= 31 ; irq++) {
899 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
900 handle_level_irq);
901 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
902 }
903
904 irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
905
906 for (irq = 0 ; irq <= 15 ; irq++) {
907 eint0_15_data[irq] = IRQ_EINT(irq);
908
909 if (soc_is_exynos5250()) {
910 irq_set_handler_data(exynos5_eint0_15_src_int[irq],
911 &eint0_15_data[irq]);
912 irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
913 exynos_irq_eint0_15);
914 } else {
915 irq_set_handler_data(exynos4_eint0_15_src_int[irq],
916 &eint0_15_data[irq]);
917 irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
918 exynos_irq_eint0_15);
919 }
920 }
921
922 return 0;
923}
924arch_initcall(exynos_init_irq_eint);
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 23:42:53 -0400