spi: s3c64xx: move controller information into driver data

Platform data is used to specify controller hardware specific information
such as the tx/rx fifo level mask and bit offset of rx fifo level. Such
information is not suitable to be supplied from device tree. Instead,
it can be moved into the driver data and removed from platform data.

Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Jaswinder Singh <jaswinder.singh@linaro.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

2 files changed, 9 insertions, 34 deletions

diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index bcb7db453145..10a46a9f0ea7 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -586,17 +586,17 @@ static struct clk exynos4_init_clocks_off[] = {
                 .ctrlbit        = (1 << 13),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.0",
+                .devname        = "exynos4210-spi.0",
                 .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 16),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.1",
+                .devname        = "exynos4210-spi.1",
                 .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 17),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.2",
+                .devname        = "exynos4210-spi.2",
                 .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 18),
         }, {
@@ -1245,7 +1245,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
 static struct clksrc_clk exynos4_clk_sclk_spi0 = {
         .clk    = {
                 .name           = "sclk_spi",
-                .devname        = "s3c64xx-spi.0",
+                .devname        = "exynos4210-spi.0",
                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
                 .ctrlbit        = (1 << 16),
         },
@@ -1257,7 +1257,7 @@ static struct clksrc_clk exynos4_clk_sclk_spi0 = {
 static struct clksrc_clk exynos4_clk_sclk_spi1 = {
         .clk    = {
                 .name           = "sclk_spi",
-                .devname        = "s3c64xx-spi.1",
+                .devname        = "exynos4210-spi.1",
                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
                 .ctrlbit        = (1 << 20),
         },
@@ -1269,7 +1269,7 @@ static struct clksrc_clk exynos4_clk_sclk_spi1 = {
 static struct clksrc_clk exynos4_clk_sclk_spi2 = {
         .clk    = {
                 .name           = "sclk_spi",
-                .devname        = "s3c64xx-spi.2",
+                .devname        = "exynos4210-spi.2",
                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
                 .ctrlbit        = (1 << 24),
         },
@@ -1347,9 +1347,9 @@ static struct clk_lookup exynos4_clk_lookup[] = {
         CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
         CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
         CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
-        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
-        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
-        CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
+        CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
+        CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
+        CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
 };
 
 static int xtal_rate;
diff --git a/arch/arm/mach-exynos/setup-spi.c b/arch/arm/mach-exynos/setup-spi.c
index 833ff40ee0e8..a71ec4db4cf4 100644
--- a/arch/arm/mach-exynos/setup-spi.c
+++ b/arch/arm/mach-exynos/setup-spi.c
@@ -12,17 +12,8 @@
 #include <linux/platform_device.h>
 
 #include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
-        .fifo_lvl_mask  = 0x1ff,
-        .rx_lvl_offset  = 15,
-        .high_speed     = 1,
-        .clk_from_cmu   = true,
-        .tx_st_done     = 25,
-};
-
 int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 {
         s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2));
@@ -34,14 +25,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
-        .fifo_lvl_mask  = 0x7f,
-        .rx_lvl_offset  = 15,
-        .high_speed     = 1,
-        .clk_from_cmu   = true,
-        .tx_st_done     = 25,
-};
-
 int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
 {
         s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2));
@@ -53,14 +36,6 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI2
-struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = {
-        .fifo_lvl_mask  = 0x7f,
-        .rx_lvl_offset  = 15,
-        .high_speed     = 1,
-        .clk_from_cmu   = true,
-        .tx_st_done     = 25,
-};
-
 int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
 {
         s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5));