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authorJonghwan Choi <jhbird.choi@samsung.com>2012-06-26 20:47:35 -0400
committerKukjin Kim <kgene.kim@samsung.com>2012-07-12 03:15:08 -0400
commit7d896aaceb0ac361abf581b3b21de20f52da0ce9 (patch)
tree2fd0f659cea96bfc71eefb83a253b6939cb57d68 /arch/arm/mach-exynos
parent485802a6c524e62b5924849dd727ddbb1497cc71 (diff)
ARM: EXYNOS: Clear SYS_WDTRESET bit to use watchdog reset
When SYS_WDTRESET is set, watchdog timer reset request is ignored by power management unit. Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos')
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-pmu.h5
-rw-r--r--arch/arm/mach-exynos/pmu.c14
2 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 43a99e6f56ab..d4e392b811a3 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -232,6 +232,11 @@
232 232
233#define EXYNOS5_USB_CFG S5P_PMUREG(0x0230) 233#define EXYNOS5_USB_CFG S5P_PMUREG(0x0230)
234 234
235#define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408)
236#define EXYNOS5_MASK_WDTRESET_REQUEST S5P_PMUREG(0x040C)
237
238#define EXYNOS5_SYS_WDTRESET (1 << 20)
239
235#define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000) 240#define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000)
236#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004) 241#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004)
237#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008) 242#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008)
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 4aacb66f7161..bb4c522f8e05 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -390,6 +390,8 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
390 390
391static int __init exynos_pmu_init(void) 391static int __init exynos_pmu_init(void)
392{ 392{
393 unsigned int value;
394
393 exynos_pmu_config = exynos4210_pmu_config; 395 exynos_pmu_config = exynos4210_pmu_config;
394 396
395 if (soc_is_exynos4210()) { 397 if (soc_is_exynos4210()) {
@@ -399,6 +401,18 @@ static int __init exynos_pmu_init(void)
399 exynos_pmu_config = exynos4x12_pmu_config; 401 exynos_pmu_config = exynos4x12_pmu_config;
400 pr_info("EXYNOS4x12 PMU Initialize\n"); 402 pr_info("EXYNOS4x12 PMU Initialize\n");
401 } else if (soc_is_exynos5250()) { 403 } else if (soc_is_exynos5250()) {
404 /*
405 * When SYS_WDTRESET is set, watchdog timer reset request
406 * is ignored by power management unit.
407 */
408 value = __raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
409 value &= ~EXYNOS5_SYS_WDTRESET;
410 __raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
411
412 value = __raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
413 value &= ~EXYNOS5_SYS_WDTRESET;
414 __raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
415
402 exynos_pmu_config = exynos5250_pmu_config; 416 exynos_pmu_config = exynos5250_pmu_config;
403 pr_info("EXYNOS5250 PMU Initialize\n"); 417 pr_info("EXYNOS5250 PMU Initialize\n");
404 } else { 418 } else {