aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-exynos
diff options
context:
space:
mode:
authorTushar Behera <tushar.behera@linaro.org>2012-03-13 00:17:02 -0400
committerKukjin Kim <kgene.kim@samsung.com>2012-03-14 05:13:01 -0400
commit790254665293fd5f0961a4bb6e2ab07d5d311522 (patch)
treec957a667563d1663b8f99d174a636c6a8421b149 /arch/arm/mach-exynos
parentefd9960b0e1bdfe48490504a8166ffdbcc466dba (diff)
ARM: EXYNOS: Add clkdev lookup entry for lcd clock
The framebuffer driver needs the clock named 'lcd' as its bus clock but the equivalent clock on Exynos4 is named as 'fimd'. Hence, create a clkdev lookup entry with the name 'lcd' that references the 'fimd' clock. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Acked-by: Jingoo Han <jg1.han@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> [kgene.kim@samsung.com: rebased on top of latest samsung tree] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos')
-rw-r--r--arch/arm/mach-exynos/clock-exynos4.c14
1 files changed, 9 insertions, 5 deletions
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index 1bc0b751520e..6504d8b1f8e5 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -491,11 +491,6 @@ static struct clk exynos4_init_clocks_off[] = {
491 .enable = exynos4_clk_ip_cam_ctrl, 491 .enable = exynos4_clk_ip_cam_ctrl,
492 .ctrlbit = (1 << 3), 492 .ctrlbit = (1 << 3),
493 }, { 493 }, {
494 .name = "fimd",
495 .devname = "exynos4-fb.0",
496 .enable = exynos4_clk_ip_lcd0_ctrl,
497 .ctrlbit = (1 << 0),
498 }, {
499 .name = "hsmmc", 494 .name = "hsmmc",
500 .devname = "s3c-sdhci.0", 495 .devname = "s3c-sdhci.0",
501 .parent = &exynos4_clk_aclk_133.clk, 496 .parent = &exynos4_clk_aclk_133.clk,
@@ -791,6 +786,13 @@ static struct clk exynos4_clk_mdma1 = {
791 .ctrlbit = ((1 << 8) | (1 << 5) | (1 << 2)), 786 .ctrlbit = ((1 << 8) | (1 << 5) | (1 << 2)),
792}; 787};
793 788
789static struct clk exynos4_clk_fimd0 = {
790 .name = "fimd",
791 .devname = "exynos4-fb.0",
792 .enable = exynos4_clk_ip_lcd0_ctrl,
793 .ctrlbit = (1 << 0),
794};
795
794struct clk *exynos4_clkset_group_list[] = { 796struct clk *exynos4_clkset_group_list[] = {
795 [0] = &clk_ext_xtal_mux, 797 [0] = &clk_ext_xtal_mux,
796 [1] = &clk_xusbxti, 798 [1] = &clk_xusbxti,
@@ -1310,6 +1312,7 @@ static struct clk *exynos4_clk_cdev[] = {
1310 &exynos4_clk_pdma0, 1312 &exynos4_clk_pdma0,
1311 &exynos4_clk_pdma1, 1313 &exynos4_clk_pdma1,
1312 &exynos4_clk_mdma1, 1314 &exynos4_clk_mdma1,
1315 &exynos4_clk_fimd0,
1313}; 1316};
1314 1317
1315static struct clksrc_clk *exynos4_clksrc_cdev[] = { 1318static struct clksrc_clk *exynos4_clksrc_cdev[] = {
@@ -1336,6 +1339,7 @@ static struct clk_lookup exynos4_clk_lookup[] = {
1336 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk), 1339 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
1337 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk), 1340 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
1338 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk), 1341 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
1342 CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
1339 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0), 1343 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
1340 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1), 1344 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
1341 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1), 1345 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),