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authorKukjin Kim <kgene.kim@samsung.com>2013-06-10 05:15:23 -0400
committerKukjin Kim <kgene.kim@samsung.com>2013-06-10 05:25:35 -0400
commit383ffda2fa8ff3c6380cc5be1eb6cde510de6fa8 (patch)
treec90c04ddd8df3155d385537fe5cc7625649a0ba0 /arch/arm/mach-exynos
parent317ddd256b9c24b0d78fa8018f80f1e495481a10 (diff)
ARM: EXYNOS: no more support non-DT for EXYNOS SoCs
As we discussed in mailing list, non-DT for EXYNOS SoCs will not be supported from v3.11. This patch removes regarding files for non-DT including board files and defconfig. Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Tomasz Figa <t.figa@samsung.com> Cc: Thomas Abraham <thomas.ab@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Olof Johansson <olof@lixom.net> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos')
-rw-r--r--arch/arm/mach-exynos/Kconfig320
-rw-r--r--arch/arm/mach-exynos/Makefile26
-rw-r--r--arch/arm/mach-exynos/common.c10
-rw-r--r--arch/arm/mach-exynos/dev-ahci.c255
-rw-r--r--arch/arm/mach-exynos/dev-ohci.c52
-rw-r--r--arch/arm/mach-exynos/dma.c322
-rw-r--r--arch/arm/mach-exynos/pm_domains.c7
7 files changed, 1 insertions, 991 deletions
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index ff18fc2ea46f..41fd73f4c29e 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -84,329 +84,11 @@ config SOC_EXYNOS5440
84 help 84 help
85 Enable EXYNOS5440 SoC support 85 Enable EXYNOS5440 SoC support
86 86
87config EXYNOS_ATAGS
88 bool "ATAGS based boot for EXYNOS (deprecated)"
89 depends on !ARCH_MULTIPLATFORM
90 depends on ATAGS
91 default y
92 help
93 The EXYNOS platform is moving towards being completely probed
94 through device tree. This enables support for board files using
95 the traditional ATAGS boot format.
96 Note that this option is not available for multiplatform builds.
97
98if EXYNOS_ATAGS
99
100config EXYNOS_DEV_DMA
101 bool
102 help
103 Compile in amba device definitions for DMA controller
104
105config EXYNOS4_DEV_AHCI
106 bool
107 help
108 Compile in platform device definitions for AHCI
109
110config EXYNOS4_SETUP_FIMD0
111 bool
112 help
113 Common setup code for FIMD0.
114
115config EXYNOS4_DEV_USB_OHCI
116 bool
117 help
118 Compile in platform device definition for USB OHCI
119
120config EXYNOS4_SETUP_I2C1
121 bool
122 help
123 Common setup code for i2c bus 1.
124
125config EXYNOS4_SETUP_I2C2
126 bool
127 help
128 Common setup code for i2c bus 2.
129
130config EXYNOS4_SETUP_I2C3
131 bool
132 help
133 Common setup code for i2c bus 3.
134
135config EXYNOS4_SETUP_I2C4
136 bool
137 help
138 Common setup code for i2c bus 4.
139
140config EXYNOS4_SETUP_I2C5
141 bool
142 help
143 Common setup code for i2c bus 5.
144
145config EXYNOS4_SETUP_I2C6
146 bool
147 help
148 Common setup code for i2c bus 6.
149
150config EXYNOS4_SETUP_I2C7
151 bool
152 help
153 Common setup code for i2c bus 7.
154
155config EXYNOS4_SETUP_KEYPAD
156 bool
157 help
158 Common setup code for keypad.
159
160config EXYNOS4_SETUP_SDHCI
161 bool
162 select EXYNOS4_SETUP_SDHCI_GPIO
163 help
164 Internal helper functions for EXYNOS4 based SDHCI systems.
165
166config EXYNOS4_SETUP_SDHCI_GPIO
167 bool
168 help
169 Common setup code for SDHCI gpio.
170
171config EXYNOS4_SETUP_FIMC
172 bool
173 help
174 Common setup code for the camera interfaces.
175
176config EXYNOS4_SETUP_USB_PHY
177 bool
178 help
179 Common setup code for USB PHY controller
180
181config EXYNOS_SETUP_SPI
182 bool
183 help
184 Common setup code for SPI GPIO configurations.
185
186# machine support
187
188if ARCH_EXYNOS4
189
190comment "EXYNOS4210 Boards"
191
192config MACH_SMDKC210
193 bool "SMDKC210"
194 select MACH_SMDKV310
195 help
196 Machine support for Samsung SMDKC210
197
198config MACH_SMDKV310
199 bool "SMDKV310"
200 select CPU_EXYNOS4210
201 select EXYNOS4_DEV_AHCI
202 select EXYNOS4_DEV_USB_OHCI
203 select EXYNOS4_SETUP_FIMD0
204 select EXYNOS4_SETUP_I2C1
205 select EXYNOS4_SETUP_KEYPAD
206 select EXYNOS4_SETUP_SDHCI
207 select EXYNOS4_SETUP_USB_PHY
208 select EXYNOS_DEV_DMA
209 select EXYNOS_DEV_SYSMMU
210 select S3C24XX_PWM
211 select S3C_DEV_HSMMC
212 select S3C_DEV_HSMMC1
213 select S3C_DEV_HSMMC2
214 select S3C_DEV_HSMMC3
215 select S3C_DEV_I2C1
216 select S3C_DEV_RTC
217 select S3C_DEV_USB_HSOTG
218 select S3C_DEV_WDT
219 select S5P_DEV_FIMC0
220 select S5P_DEV_FIMC1
221 select S5P_DEV_FIMC2
222 select S5P_DEV_FIMC3
223 select S5P_DEV_FIMD0
224 select S5P_DEV_G2D
225 select S5P_DEV_I2C_HDMIPHY
226 select S5P_DEV_JPEG
227 select S5P_DEV_MFC
228 select S5P_DEV_TV
229 select S5P_DEV_USB_EHCI
230 select SAMSUNG_DEV_BACKLIGHT
231 select SAMSUNG_DEV_KEYPAD
232 select SAMSUNG_DEV_PWM
233 help
234 Machine support for Samsung SMDKV310
235
236config MACH_ARMLEX4210
237 bool "ARMLEX4210"
238 select CPU_EXYNOS4210
239 select EXYNOS4_DEV_AHCI
240 select EXYNOS4_SETUP_SDHCI
241 select EXYNOS_DEV_DMA
242 select S3C_DEV_HSMMC
243 select S3C_DEV_HSMMC2
244 select S3C_DEV_HSMMC3
245 select S3C_DEV_RTC
246 select S3C_DEV_WDT
247 help
248 Machine support for Samsung ARMLEX4210 based on EXYNOS4210
249
250config MACH_UNIVERSAL_C210
251 bool "Mobile UNIVERSAL_C210 Board"
252 select CLKSRC_MMIO
253 select CLKSRC_SAMSUNG_PWM
254 select CPU_EXYNOS4210
255 select EXYNOS4_SETUP_FIMC
256 select EXYNOS4_SETUP_FIMD0
257 select EXYNOS4_SETUP_I2C1
258 select EXYNOS4_SETUP_I2C3
259 select EXYNOS4_SETUP_I2C5
260 select EXYNOS4_SETUP_SDHCI
261 select EXYNOS4_SETUP_USB_PHY
262 select EXYNOS_DEV_DMA
263 select EXYNOS_DEV_SYSMMU
264 select S3C_DEV_HSMMC
265 select S3C_DEV_HSMMC2
266 select S3C_DEV_HSMMC3
267 select S3C_DEV_I2C1
268 select S3C_DEV_I2C3
269 select S3C_DEV_I2C5
270 select S3C_DEV_USB_HSOTG
271 select S5P_DEV_CSIS0
272 select S5P_DEV_FIMC0
273 select S5P_DEV_FIMC1
274 select S5P_DEV_FIMC2
275 select S5P_DEV_FIMC3
276 select S5P_DEV_FIMD0
277 select S5P_DEV_G2D
278 select S5P_DEV_I2C_HDMIPHY
279 select S5P_DEV_JPEG
280 select S5P_DEV_MFC
281 select S5P_DEV_ONENAND
282 select S5P_DEV_TV
283 select S5P_GPIO_INT
284 select S5P_SETUP_MIPIPHY
285 help
286 Machine support for Samsung Mobile Universal S5PC210 Reference
287 Board.
288
289config MACH_NURI
290 bool "Mobile NURI Board"
291 select CPU_EXYNOS4210
292 select EXYNOS4_SETUP_FIMC
293 select EXYNOS4_SETUP_FIMD0
294 select EXYNOS4_SETUP_I2C1
295 select EXYNOS4_SETUP_I2C3
296 select EXYNOS4_SETUP_I2C5
297 select EXYNOS4_SETUP_I2C6
298 select EXYNOS4_SETUP_SDHCI
299 select EXYNOS4_SETUP_USB_PHY
300 select EXYNOS_DEV_DMA
301 select S3C_DEV_HSMMC
302 select S3C_DEV_HSMMC2
303 select S3C_DEV_HSMMC3
304 select S3C_DEV_I2C1
305 select S3C_DEV_I2C3
306 select S3C_DEV_I2C5
307 select S3C_DEV_I2C6
308 select S3C_DEV_RTC
309 select S3C_DEV_USB_HSOTG
310 select S3C_DEV_WDT
311 select S5P_DEV_CSIS0
312 select S5P_DEV_FIMC0
313 select S5P_DEV_FIMC1
314 select S5P_DEV_FIMC2
315 select S5P_DEV_FIMC3
316 select S5P_DEV_FIMD0
317 select S5P_DEV_G2D
318 select S5P_DEV_JPEG
319 select S5P_DEV_MFC
320 select S5P_DEV_USB_EHCI
321 select S5P_GPIO_INT
322 select S5P_SETUP_MIPIPHY
323 select SAMSUNG_DEV_ADC
324 select SAMSUNG_DEV_PWM
325 help
326 Machine support for Samsung Mobile NURI Board.
327
328config MACH_ORIGEN
329 bool "ORIGEN"
330 select CPU_EXYNOS4210
331 select EXYNOS4_DEV_USB_OHCI
332 select EXYNOS4_SETUP_FIMD0
333 select EXYNOS4_SETUP_SDHCI
334 select EXYNOS4_SETUP_USB_PHY
335 select EXYNOS_DEV_DMA
336 select EXYNOS_DEV_SYSMMU
337 select S3C24XX_PWM
338 select S3C_DEV_HSMMC
339 select S3C_DEV_HSMMC2
340 select S3C_DEV_RTC
341 select S3C_DEV_USB_HSOTG
342 select S3C_DEV_WDT
343 select S5P_DEV_FIMC0
344 select S5P_DEV_FIMC1
345 select S5P_DEV_FIMC2
346 select S5P_DEV_FIMC3
347 select S5P_DEV_FIMD0
348 select S5P_DEV_G2D
349 select S5P_DEV_I2C_HDMIPHY
350 select S5P_DEV_JPEG
351 select S5P_DEV_MFC
352 select S5P_DEV_TV
353 select S5P_DEV_USB_EHCI
354 select SAMSUNG_DEV_BACKLIGHT
355 select SAMSUNG_DEV_PWM
356 help
357 Machine support for ORIGEN based on Samsung EXYNOS4210
358
359comment "EXYNOS4212 Boards"
360
361config MACH_SMDK4212
362 bool "SMDK4212"
363 select EXYNOS4_SETUP_FIMD0
364 select EXYNOS4_SETUP_I2C1
365 select EXYNOS4_SETUP_I2C3
366 select EXYNOS4_SETUP_I2C7
367 select EXYNOS4_SETUP_KEYPAD
368 select EXYNOS4_SETUP_SDHCI
369 select EXYNOS4_SETUP_USB_PHY
370 select EXYNOS_DEV_DMA
371 select EXYNOS_DEV_SYSMMU
372 select S3C24XX_PWM
373 select S3C_DEV_HSMMC2
374 select S3C_DEV_HSMMC3
375 select S3C_DEV_I2C1
376 select S3C_DEV_I2C3
377 select S3C_DEV_I2C7
378 select S3C_DEV_RTC
379 select S3C_DEV_USB_HSOTG
380 select S3C_DEV_WDT
381 select S5P_DEV_FIMC0
382 select S5P_DEV_FIMC1
383 select S5P_DEV_FIMC2
384 select S5P_DEV_FIMC3
385 select S5P_DEV_FIMD0
386 select S5P_DEV_MFC
387 select SAMSUNG_DEV_BACKLIGHT
388 select SAMSUNG_DEV_KEYPAD
389 select SAMSUNG_DEV_PWM
390 select SOC_EXYNOS4212
391 help
392 Machine support for Samsung SMDK4212
393
394comment "EXYNOS4412 Boards"
395
396config MACH_SMDK4412
397 bool "SMDK4412"
398 select MACH_SMDK4212
399 select SOC_EXYNOS4412
400 help
401 Machine support for Samsung SMDK4412
402endif
403
404endif
405
406comment "Flattened Device Tree based board for EXYNOS SoCs" 87comment "Flattened Device Tree based board for EXYNOS SoCs"
407 88
408config MACH_EXYNOS4_DT 89config MACH_EXYNOS4_DT
409 bool "Samsung Exynos4 Machine using device tree" 90 bool "Samsung Exynos4 Machine using device tree"
91 default y
410 depends on ARCH_EXYNOS4 92 depends on ARCH_EXYNOS4
411 select ARM_AMBA 93 select ARM_AMBA
412 select CLKSRC_OF 94 select CLKSRC_OF
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index b09b027178f3..9811f87308b1 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -32,16 +32,6 @@ AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec)
32 32
33# machine support 33# machine support
34 34
35obj-$(CONFIG_MACH_SMDKC210) += mach-smdkv310.o
36obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o
37obj-$(CONFIG_MACH_ARMLEX4210) += mach-armlex4210.o
38obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
39obj-$(CONFIG_MACH_NURI) += mach-nuri.o
40obj-$(CONFIG_MACH_ORIGEN) += mach-origen.o
41
42obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4x12.o
43obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o
44
45obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o 35obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o
46obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o 36obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
47 37
@@ -49,21 +39,5 @@ obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
49 39
50obj-y += dev-uart.o 40obj-y += dev-uart.o
51obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o 41obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
52obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
53obj-$(CONFIG_EXYNOS_DEV_DMA) += dma.o
54obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
55 42
56obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o 43obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o
57obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
58obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o
59obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
60obj-$(CONFIG_EXYNOS4_SETUP_I2C2) += setup-i2c2.o
61obj-$(CONFIG_EXYNOS4_SETUP_I2C3) += setup-i2c3.o
62obj-$(CONFIG_EXYNOS4_SETUP_I2C4) += setup-i2c4.o
63obj-$(CONFIG_EXYNOS4_SETUP_I2C5) += setup-i2c5.o
64obj-$(CONFIG_EXYNOS4_SETUP_I2C6) += setup-i2c6.o
65obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
66obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o
67obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
68obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o
69obj-$(CONFIG_EXYNOS_SETUP_SPI) += setup-spi.o
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index f7e504b7874d..9834357707d8 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -353,7 +353,6 @@ void __init exynos_init_late(void)
353 exynos_pm_late_initcall(); 353 exynos_pm_late_initcall();
354} 354}
355 355
356#ifdef CONFIG_OF
357int __init exynos_fdt_map_chipid(unsigned long node, const char *uname, 356int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
358 int depth, void *data) 357 int depth, void *data)
359{ 358{
@@ -376,7 +375,6 @@ int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
376 iotable_init(&iodesc, 1); 375 iotable_init(&iodesc, 1);
377 return 1; 376 return 1;
378} 377}
379#endif
380 378
381/* 379/*
382 * exynos_map_io 380 * exynos_map_io
@@ -388,11 +386,9 @@ void __init exynos_init_io(struct map_desc *mach_desc, int size)
388{ 386{
389 debug_ll_io_init(); 387 debug_ll_io_init();
390 388
391#ifdef CONFIG_OF
392 if (initial_boot_params) 389 if (initial_boot_params)
393 of_scan_flat_dt(exynos_fdt_map_chipid, NULL); 390 of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
394 else 391 else
395#endif
396 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc)); 392 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
397 393
398 if (mach_desc) 394 if (mach_desc)
@@ -475,10 +471,8 @@ void __init exynos_init_time(void)
475 }; 471 };
476 472
477 if (of_have_populated_dt()) { 473 if (of_have_populated_dt()) {
478#ifdef CONFIG_OF
479 of_clk_init(NULL); 474 of_clk_init(NULL);
480 clocksource_of_init(); 475 clocksource_of_init();
481#endif
482 } else { 476 } else {
483 /* todo: remove after migrating legacy E4 platforms to dt */ 477 /* todo: remove after migrating legacy E4 platforms to dt */
484#ifdef CONFIG_ARCH_EXYNOS4 478#ifdef CONFIG_ARCH_EXYNOS4
@@ -517,10 +511,8 @@ void __init exynos4_init_irq(void)
517 511
518 if (!of_have_populated_dt()) 512 if (!of_have_populated_dt())
519 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL); 513 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
520#ifdef CONFIG_OF
521 else 514 else
522 irqchip_init(); 515 irqchip_init();
523#endif
524 516
525 if (!of_have_populated_dt()) 517 if (!of_have_populated_dt())
526 combiner_init(S5P_VA_COMBINER_BASE, NULL, 518 combiner_init(S5P_VA_COMBINER_BASE, NULL,
@@ -531,9 +523,7 @@ void __init exynos4_init_irq(void)
531 523
532void __init exynos5_init_irq(void) 524void __init exynos5_init_irq(void)
533{ 525{
534#ifdef CONFIG_OF
535 irqchip_init(); 526 irqchip_init();
536#endif
537 gic_arch_extn.irq_set_wake = s3c_irq_wake; 527 gic_arch_extn.irq_set_wake = s3c_irq_wake;
538} 528}
539 529
diff --git a/arch/arm/mach-exynos/dev-ahci.c b/arch/arm/mach-exynos/dev-ahci.c
deleted file mode 100644
index ce1aad3eeeb9..000000000000
--- a/arch/arm/mach-exynos/dev-ahci.c
+++ /dev/null
@@ -1,255 +0,0 @@
1/* linux/arch/arm/mach-exynos4/dev-ahci.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - AHCI support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/dma-mapping.h>
16#include <linux/platform_device.h>
17#include <linux/ahci_platform.h>
18
19#include <plat/cpu.h>
20
21#include <mach/irqs.h>
22#include <mach/map.h>
23#include <mach/regs-pmu.h>
24
25/* PHY Control Register */
26#define SATA_CTRL0 0x0
27/* PHY Link Control Register */
28#define SATA_CTRL1 0x4
29/* PHY Status Register */
30#define SATA_PHY_STATUS 0x8
31
32#define SATA_CTRL0_RX_DATA_VALID(x) (x << 27)
33#define SATA_CTRL0_SPEED_MODE (1 << 26)
34#define SATA_CTRL0_M_PHY_CAL (1 << 19)
35#define SATA_CTRL0_PHY_CMU_RST_N (1 << 10)
36#define SATA_CTRL0_M_PHY_LN_RST_N (1 << 9)
37#define SATA_CTRL0_PHY_POR_N (1 << 8)
38
39#define SATA_CTRL1_RST_PMALIVE_N (1 << 8)
40#define SATA_CTRL1_RST_RXOOB_N (1 << 7)
41#define SATA_CTRL1_RST_RX_N (1 << 6)
42#define SATA_CTRL1_RST_TX_N (1 << 5)
43
44#define SATA_PHY_STATUS_CMU_OK (1 << 18)
45#define SATA_PHY_STATUS_LANE_OK (1 << 16)
46
47#define LANE0 0x200
48#define COM_LANE 0xA00
49
50#define HOST_PORTS_IMPL 0xC
51#define SCLK_SATA_FREQ (67 * MHZ)
52
53static void __iomem *phy_base, *phy_ctrl;
54
55struct phy_reg {
56 u8 reg;
57 u8 val;
58};
59
60/* SATA PHY setup */
61static const struct phy_reg exynos4_sataphy_cmu[] = {
62 { 0x00, 0x06 }, { 0x02, 0x80 }, { 0x22, 0xa0 }, { 0x23, 0x42 },
63 { 0x2e, 0x04 }, { 0x2f, 0x50 }, { 0x30, 0x70 }, { 0x31, 0x02 },
64 { 0x32, 0x25 }, { 0x33, 0x40 }, { 0x34, 0x01 }, { 0x35, 0x40 },
65 { 0x61, 0x2e }, { 0x63, 0x5e }, { 0x65, 0x42 }, { 0x66, 0xd1 },
66 { 0x67, 0x20 }, { 0x68, 0x28 }, { 0x69, 0x78 }, { 0x6a, 0x04 },
67 { 0x6b, 0xc8 }, { 0x6c, 0x06 },
68};
69
70static const struct phy_reg exynos4_sataphy_lane[] = {
71 { 0x00, 0x02 }, { 0x05, 0x10 }, { 0x06, 0x84 }, { 0x07, 0x04 },
72 { 0x08, 0xe0 }, { 0x10, 0x23 }, { 0x13, 0x05 }, { 0x14, 0x30 },
73 { 0x15, 0x00 }, { 0x17, 0x70 }, { 0x18, 0xf2 }, { 0x19, 0x1e },
74 { 0x1a, 0x18 }, { 0x1b, 0x0d }, { 0x1c, 0x08 }, { 0x50, 0x60 },
75 { 0x51, 0x0f },
76};
77
78static const struct phy_reg exynos4_sataphy_comlane[] = {
79 { 0x01, 0x20 }, { 0x03, 0x40 }, { 0x04, 0x3c }, { 0x05, 0x7d },
80 { 0x06, 0x1d }, { 0x07, 0xcf }, { 0x08, 0x05 }, { 0x09, 0x63 },
81 { 0x0a, 0x29 }, { 0x0b, 0xc4 }, { 0x0c, 0x01 }, { 0x0d, 0x03 },
82 { 0x0e, 0x28 }, { 0x0f, 0x98 }, { 0x10, 0x19 }, { 0x13, 0x80 },
83 { 0x14, 0xf0 }, { 0x15, 0xd0 }, { 0x39, 0xa0 }, { 0x3a, 0xa0 },
84 { 0x3b, 0xa0 }, { 0x3c, 0xa0 }, { 0x3d, 0xa0 }, { 0x3e, 0xa0 },
85 { 0x3f, 0xa0 }, { 0x40, 0x42 }, { 0x42, 0x80 }, { 0x43, 0x58 },
86 { 0x45, 0x44 }, { 0x46, 0x5c }, { 0x47, 0x86 }, { 0x48, 0x8d },
87 { 0x49, 0xd0 }, { 0x4a, 0x09 }, { 0x4b, 0x90 }, { 0x4c, 0x07 },
88 { 0x4d, 0x40 }, { 0x51, 0x20 }, { 0x52, 0x32 }, { 0x7f, 0xd8 },
89 { 0x80, 0x1a }, { 0x81, 0xff }, { 0x82, 0x11 }, { 0x83, 0x00 },
90 { 0x87, 0xf0 }, { 0x87, 0xff }, { 0x87, 0xff }, { 0x87, 0xff },
91 { 0x87, 0xff }, { 0x8c, 0x1c }, { 0x8d, 0xc2 }, { 0x8e, 0xc3 },
92 { 0x8f, 0x3f }, { 0x90, 0x0a }, { 0x96, 0xf8 },
93};
94
95static int wait_for_phy_ready(void __iomem *reg, unsigned long bit)
96{
97 unsigned long timeout;
98
99 /* wait for maximum of 3 sec */
100 timeout = jiffies + msecs_to_jiffies(3000);
101 while (!(__raw_readl(reg) & bit)) {
102 if (time_after(jiffies, timeout))
103 return -1;
104 cpu_relax();
105 }
106 return 0;
107}
108
109static int ahci_phy_init(void __iomem *mmio)
110{
111 int i, ctrl0;
112
113 for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_cmu); i++)
114 __raw_writeb(exynos4_sataphy_cmu[i].val,
115 phy_base + (exynos4_sataphy_cmu[i].reg * 4));
116
117 for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_lane); i++)
118 __raw_writeb(exynos4_sataphy_lane[i].val,
119 phy_base + (LANE0 + exynos4_sataphy_lane[i].reg) * 4);
120
121 for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_comlane); i++)
122 __raw_writeb(exynos4_sataphy_comlane[i].val,
123 phy_base + (COM_LANE + exynos4_sataphy_comlane[i].reg) * 4);
124
125 __raw_writeb(0x07, phy_base);
126
127 ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
128 ctrl0 |= SATA_CTRL0_PHY_CMU_RST_N;
129 __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
130
131 if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
132 SATA_PHY_STATUS_CMU_OK) < 0) {
133 printk(KERN_ERR "PHY CMU not ready\n");
134 return -EBUSY;
135 }
136
137 __raw_writeb(0x03, phy_base + (COM_LANE * 4));
138
139 ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
140 ctrl0 |= SATA_CTRL0_M_PHY_LN_RST_N;
141 __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
142
143 if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
144 SATA_PHY_STATUS_LANE_OK) < 0) {
145 printk(KERN_ERR "PHY LANE not ready\n");
146 return -EBUSY;
147 }
148
149 ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
150 ctrl0 |= SATA_CTRL0_M_PHY_CAL;
151 __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
152
153 return 0;
154}
155
156static int exynos4_ahci_init(struct device *dev, void __iomem *mmio)
157{
158 struct clk *clk_sata, *clk_sataphy, *clk_sclk_sata;
159 int val, ret;
160
161 phy_base = ioremap(EXYNOS4_PA_SATAPHY, SZ_64K);
162 if (!phy_base) {
163 dev_err(dev, "failed to allocate memory for SATA PHY\n");
164 return -ENOMEM;
165 }
166
167 phy_ctrl = ioremap(EXYNOS4_PA_SATAPHY_CTRL, SZ_16);
168 if (!phy_ctrl) {
169 dev_err(dev, "failed to allocate memory for SATA PHY CTRL\n");
170 ret = -ENOMEM;
171 goto err1;
172 }
173
174 clk_sata = clk_get(dev, "sata");
175 if (IS_ERR(clk_sata)) {
176 dev_err(dev, "failed to get sata clock\n");
177 ret = PTR_ERR(clk_sata);
178 clk_sata = NULL;
179 goto err2;
180
181 }
182 clk_enable(clk_sata);
183
184 clk_sataphy = clk_get(dev, "sataphy");
185 if (IS_ERR(clk_sataphy)) {
186 dev_err(dev, "failed to get sataphy clock\n");
187 ret = PTR_ERR(clk_sataphy);
188 clk_sataphy = NULL;
189 goto err3;
190 }
191 clk_enable(clk_sataphy);
192
193 clk_sclk_sata = clk_get(dev, "sclk_sata");
194 if (IS_ERR(clk_sclk_sata)) {
195 dev_err(dev, "failed to get sclk_sata\n");
196 ret = PTR_ERR(clk_sclk_sata);
197 clk_sclk_sata = NULL;
198 goto err4;
199 }
200 clk_enable(clk_sclk_sata);
201 clk_set_rate(clk_sclk_sata, SCLK_SATA_FREQ);
202
203 __raw_writel(S5P_PMU_SATA_PHY_CONTROL_EN, S5P_PMU_SATA_PHY_CONTROL);
204
205 /* Enable PHY link control */
206 val = SATA_CTRL1_RST_PMALIVE_N | SATA_CTRL1_RST_RXOOB_N |
207 SATA_CTRL1_RST_RX_N | SATA_CTRL1_RST_TX_N;
208 __raw_writel(val, phy_ctrl + SATA_CTRL1);
209
210 /* Set communication speed as 3Gbps and enable PHY power */
211 val = SATA_CTRL0_RX_DATA_VALID(3) | SATA_CTRL0_SPEED_MODE |
212 SATA_CTRL0_PHY_POR_N;
213 __raw_writel(val, phy_ctrl + SATA_CTRL0);
214
215 /* Port0 is available */
216 __raw_writel(0x1, mmio + HOST_PORTS_IMPL);
217
218 return ahci_phy_init(mmio);
219
220err4:
221 clk_disable(clk_sataphy);
222 clk_put(clk_sataphy);
223err3:
224 clk_disable(clk_sata);
225 clk_put(clk_sata);
226err2:
227 iounmap(phy_ctrl);
228err1:
229 iounmap(phy_base);
230
231 return ret;
232}
233
234static struct ahci_platform_data exynos4_ahci_pdata = {
235 .init = exynos4_ahci_init,
236};
237
238static struct resource exynos4_ahci_resource[] = {
239 [0] = DEFINE_RES_MEM(EXYNOS4_PA_SATA, SZ_64K),
240 [1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_SATA),
241};
242
243static u64 exynos4_ahci_dmamask = DMA_BIT_MASK(32);
244
245struct platform_device exynos4_device_ahci = {
246 .name = "ahci",
247 .id = -1,
248 .resource = exynos4_ahci_resource,
249 .num_resources = ARRAY_SIZE(exynos4_ahci_resource),
250 .dev = {
251 .platform_data = &exynos4_ahci_pdata,
252 .dma_mask = &exynos4_ahci_dmamask,
253 .coherent_dma_mask = DMA_BIT_MASK(32),
254 },
255};
diff --git a/arch/arm/mach-exynos/dev-ohci.c b/arch/arm/mach-exynos/dev-ohci.c
deleted file mode 100644
index d5bc129e6bb7..000000000000
--- a/arch/arm/mach-exynos/dev-ohci.c
+++ /dev/null
@@ -1,52 +0,0 @@
1/* linux/arch/arm/mach-exynos/dev-ohci.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS - OHCI support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/dma-mapping.h>
14#include <linux/platform_device.h>
15#include <linux/platform_data/usb-ohci-exynos.h>
16
17#include <mach/irqs.h>
18#include <mach/map.h>
19
20#include <plat/devs.h>
21#include <plat/usb-phy.h>
22
23static struct resource exynos4_ohci_resource[] = {
24 [0] = DEFINE_RES_MEM(EXYNOS4_PA_OHCI, SZ_256),
25 [1] = DEFINE_RES_IRQ(IRQ_USB_HOST),
26};
27
28static u64 exynos4_ohci_dma_mask = DMA_BIT_MASK(32);
29
30struct platform_device exynos4_device_ohci = {
31 .name = "exynos-ohci",
32 .id = -1,
33 .num_resources = ARRAY_SIZE(exynos4_ohci_resource),
34 .resource = exynos4_ohci_resource,
35 .dev = {
36 .dma_mask = &exynos4_ohci_dma_mask,
37 .coherent_dma_mask = DMA_BIT_MASK(32),
38 }
39};
40
41void __init exynos4_ohci_set_platdata(struct exynos4_ohci_platdata *pd)
42{
43 struct exynos4_ohci_platdata *npd;
44
45 npd = s3c_set_platdata(pd, sizeof(struct exynos4_ohci_platdata),
46 &exynos4_device_ohci);
47
48 if (!npd->phy_init)
49 npd->phy_init = s5p_usb_phy_init;
50 if (!npd->phy_exit)
51 npd->phy_exit = s5p_usb_phy_exit;
52}
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
deleted file mode 100644
index 87e07d6fc615..000000000000
--- a/arch/arm/mach-exynos/dma.c
+++ /dev/null
@@ -1,322 +0,0 @@
1/* linux/arch/arm/mach-exynos4/dma.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
7 * Jaswinder Singh <jassi.brar@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#include <linux/dma-mapping.h>
25#include <linux/amba/bus.h>
26#include <linux/amba/pl330.h>
27#include <linux/of.h>
28
29#include <asm/irq.h>
30#include <plat/devs.h>
31#include <plat/irqs.h>
32#include <plat/cpu.h>
33
34#include <mach/map.h>
35#include <mach/irqs.h>
36#include <mach/dma.h>
37
38static u8 exynos4210_pdma0_peri[] = {
39 DMACH_PCM0_RX,
40 DMACH_PCM0_TX,
41 DMACH_PCM2_RX,
42 DMACH_PCM2_TX,
43 DMACH_MSM_REQ0,
44 DMACH_MSM_REQ2,
45 DMACH_SPI0_RX,
46 DMACH_SPI0_TX,
47 DMACH_SPI2_RX,
48 DMACH_SPI2_TX,
49 DMACH_I2S0S_TX,
50 DMACH_I2S0_RX,
51 DMACH_I2S0_TX,
52 DMACH_I2S2_RX,
53 DMACH_I2S2_TX,
54 DMACH_UART0_RX,
55 DMACH_UART0_TX,
56 DMACH_UART2_RX,
57 DMACH_UART2_TX,
58 DMACH_UART4_RX,
59 DMACH_UART4_TX,
60 DMACH_SLIMBUS0_RX,
61 DMACH_SLIMBUS0_TX,
62 DMACH_SLIMBUS2_RX,
63 DMACH_SLIMBUS2_TX,
64 DMACH_SLIMBUS4_RX,
65 DMACH_SLIMBUS4_TX,
66 DMACH_AC97_MICIN,
67 DMACH_AC97_PCMIN,
68 DMACH_AC97_PCMOUT,
69};
70
71static u8 exynos4212_pdma0_peri[] = {
72 DMACH_PCM0_RX,
73 DMACH_PCM0_TX,
74 DMACH_PCM2_RX,
75 DMACH_PCM2_TX,
76 DMACH_MIPI_HSI0,
77 DMACH_MIPI_HSI1,
78 DMACH_SPI0_RX,
79 DMACH_SPI0_TX,
80 DMACH_SPI2_RX,
81 DMACH_SPI2_TX,
82 DMACH_I2S0S_TX,
83 DMACH_I2S0_RX,
84 DMACH_I2S0_TX,
85 DMACH_I2S2_RX,
86 DMACH_I2S2_TX,
87 DMACH_UART0_RX,
88 DMACH_UART0_TX,
89 DMACH_UART2_RX,
90 DMACH_UART2_TX,
91 DMACH_UART4_RX,
92 DMACH_UART4_TX,
93 DMACH_SLIMBUS0_RX,
94 DMACH_SLIMBUS0_TX,
95 DMACH_SLIMBUS2_RX,
96 DMACH_SLIMBUS2_TX,
97 DMACH_SLIMBUS4_RX,
98 DMACH_SLIMBUS4_TX,
99 DMACH_AC97_MICIN,
100 DMACH_AC97_PCMIN,
101 DMACH_AC97_PCMOUT,
102 DMACH_MIPI_HSI4,
103 DMACH_MIPI_HSI5,
104};
105
106static u8 exynos5250_pdma0_peri[] = {
107 DMACH_PCM0_RX,
108 DMACH_PCM0_TX,
109 DMACH_PCM2_RX,
110 DMACH_PCM2_TX,
111 DMACH_SPI0_RX,
112 DMACH_SPI0_TX,
113 DMACH_SPI2_RX,
114 DMACH_SPI2_TX,
115 DMACH_I2S0S_TX,
116 DMACH_I2S0_RX,
117 DMACH_I2S0_TX,
118 DMACH_I2S2_RX,
119 DMACH_I2S2_TX,
120 DMACH_UART0_RX,
121 DMACH_UART0_TX,
122 DMACH_UART2_RX,
123 DMACH_UART2_TX,
124 DMACH_UART4_RX,
125 DMACH_UART4_TX,
126 DMACH_SLIMBUS0_RX,
127 DMACH_SLIMBUS0_TX,
128 DMACH_SLIMBUS2_RX,
129 DMACH_SLIMBUS2_TX,
130 DMACH_SLIMBUS4_RX,
131 DMACH_SLIMBUS4_TX,
132 DMACH_AC97_MICIN,
133 DMACH_AC97_PCMIN,
134 DMACH_AC97_PCMOUT,
135 DMACH_MIPI_HSI0,
136 DMACH_MIPI_HSI2,
137 DMACH_MIPI_HSI4,
138 DMACH_MIPI_HSI6,
139};
140
141static struct dma_pl330_platdata exynos_pdma0_pdata;
142
143static AMBA_AHB_DEVICE(exynos_pdma0, "dma-pl330.0", 0x00041330,
144 EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos_pdma0_pdata);
145
146static u8 exynos4210_pdma1_peri[] = {
147 DMACH_PCM0_RX,
148 DMACH_PCM0_TX,
149 DMACH_PCM1_RX,
150 DMACH_PCM1_TX,
151 DMACH_MSM_REQ1,
152 DMACH_MSM_REQ3,
153 DMACH_SPI1_RX,
154 DMACH_SPI1_TX,
155 DMACH_I2S0S_TX,
156 DMACH_I2S0_RX,
157 DMACH_I2S0_TX,
158 DMACH_I2S1_RX,
159 DMACH_I2S1_TX,
160 DMACH_UART0_RX,
161 DMACH_UART0_TX,
162 DMACH_UART1_RX,
163 DMACH_UART1_TX,
164 DMACH_UART3_RX,
165 DMACH_UART3_TX,
166 DMACH_SLIMBUS1_RX,
167 DMACH_SLIMBUS1_TX,
168 DMACH_SLIMBUS3_RX,
169 DMACH_SLIMBUS3_TX,
170 DMACH_SLIMBUS5_RX,
171 DMACH_SLIMBUS5_TX,
172};
173
174static u8 exynos4212_pdma1_peri[] = {
175 DMACH_PCM0_RX,
176 DMACH_PCM0_TX,
177 DMACH_PCM1_RX,
178 DMACH_PCM1_TX,
179 DMACH_MIPI_HSI2,
180 DMACH_MIPI_HSI3,
181 DMACH_SPI1_RX,
182 DMACH_SPI1_TX,
183 DMACH_I2S0S_TX,
184 DMACH_I2S0_RX,
185 DMACH_I2S0_TX,
186 DMACH_I2S1_RX,
187 DMACH_I2S1_TX,
188 DMACH_UART0_RX,
189 DMACH_UART0_TX,
190 DMACH_UART1_RX,
191 DMACH_UART1_TX,
192 DMACH_UART3_RX,
193 DMACH_UART3_TX,
194 DMACH_SLIMBUS1_RX,
195 DMACH_SLIMBUS1_TX,
196 DMACH_SLIMBUS3_RX,
197 DMACH_SLIMBUS3_TX,
198 DMACH_SLIMBUS5_RX,
199 DMACH_SLIMBUS5_TX,
200 DMACH_SLIMBUS0AUX_RX,
201 DMACH_SLIMBUS0AUX_TX,
202 DMACH_SPDIF,
203 DMACH_MIPI_HSI6,
204 DMACH_MIPI_HSI7,
205};
206
207static u8 exynos5250_pdma1_peri[] = {
208 DMACH_PCM0_RX,
209 DMACH_PCM0_TX,
210 DMACH_PCM1_RX,
211 DMACH_PCM1_TX,
212 DMACH_SPI1_RX,
213 DMACH_SPI1_TX,
214 DMACH_PWM,
215 DMACH_SPDIF,
216 DMACH_I2S0S_TX,
217 DMACH_I2S0_RX,
218 DMACH_I2S0_TX,
219 DMACH_I2S1_RX,
220 DMACH_I2S1_TX,
221 DMACH_UART0_RX,
222 DMACH_UART0_TX,
223 DMACH_UART1_RX,
224 DMACH_UART1_TX,
225 DMACH_UART3_RX,
226 DMACH_UART3_TX,
227 DMACH_SLIMBUS1_RX,
228 DMACH_SLIMBUS1_TX,
229 DMACH_SLIMBUS3_RX,
230 DMACH_SLIMBUS3_TX,
231 DMACH_SLIMBUS5_RX,
232 DMACH_SLIMBUS5_TX,
233 DMACH_SLIMBUS0AUX_RX,
234 DMACH_SLIMBUS0AUX_TX,
235 DMACH_DISP1,
236 DMACH_MIPI_HSI1,
237 DMACH_MIPI_HSI3,
238 DMACH_MIPI_HSI5,
239 DMACH_MIPI_HSI7,
240};
241
242static struct dma_pl330_platdata exynos_pdma1_pdata;
243
244static AMBA_AHB_DEVICE(exynos_pdma1, "dma-pl330.1", 0x00041330,
245 EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos_pdma1_pdata);
246
247static u8 mdma_peri[] = {
248 DMACH_MTOM_0,
249 DMACH_MTOM_1,
250 DMACH_MTOM_2,
251 DMACH_MTOM_3,
252 DMACH_MTOM_4,
253 DMACH_MTOM_5,
254 DMACH_MTOM_6,
255 DMACH_MTOM_7,
256};
257
258static struct dma_pl330_platdata exynos_mdma1_pdata = {
259 .nr_valid_peri = ARRAY_SIZE(mdma_peri),
260 .peri_id = mdma_peri,
261};
262
263static AMBA_AHB_DEVICE(exynos_mdma1, "dma-pl330.2", 0x00041330,
264 EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos_mdma1_pdata);
265
266static int __init exynos_dma_init(void)
267{
268 if (of_have_populated_dt())
269 return 0;
270
271 if (soc_is_exynos4210()) {
272 exynos_pdma0_pdata.nr_valid_peri =
273 ARRAY_SIZE(exynos4210_pdma0_peri);
274 exynos_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
275 exynos_pdma1_pdata.nr_valid_peri =
276 ARRAY_SIZE(exynos4210_pdma1_peri);
277 exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
278
279 if (samsung_rev() == EXYNOS4210_REV_0)
280 exynos_mdma1_device.res.start = EXYNOS4_PA_S_MDMA1;
281 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
282 exynos_pdma0_pdata.nr_valid_peri =
283 ARRAY_SIZE(exynos4212_pdma0_peri);
284 exynos_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
285 exynos_pdma1_pdata.nr_valid_peri =
286 ARRAY_SIZE(exynos4212_pdma1_peri);
287 exynos_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
288 } else if (soc_is_exynos5250()) {
289 exynos_pdma0_pdata.nr_valid_peri =
290 ARRAY_SIZE(exynos5250_pdma0_peri);
291 exynos_pdma0_pdata.peri_id = exynos5250_pdma0_peri;
292 exynos_pdma1_pdata.nr_valid_peri =
293 ARRAY_SIZE(exynos5250_pdma1_peri);
294 exynos_pdma1_pdata.peri_id = exynos5250_pdma1_peri;
295
296 exynos_pdma0_device.res.start = EXYNOS5_PA_PDMA0;
297 exynos_pdma0_device.res.end = EXYNOS5_PA_PDMA0 + SZ_4K;
298 exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA0;
299 exynos_pdma1_device.res.start = EXYNOS5_PA_PDMA1;
300 exynos_pdma1_device.res.end = EXYNOS5_PA_PDMA1 + SZ_4K;
301 exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA1;
302 exynos_mdma1_device.res.start = EXYNOS5_PA_MDMA1;
303 exynos_mdma1_device.res.end = EXYNOS5_PA_MDMA1 + SZ_4K;
304 exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_MDMA1;
305 }
306
307 dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask);
308 dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask);
309 dma_cap_set(DMA_PRIVATE, exynos_pdma0_pdata.cap_mask);
310 amba_device_register(&exynos_pdma0_device, &iomem_resource);
311
312 dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask);
313 dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask);
314 dma_cap_set(DMA_PRIVATE, exynos_pdma1_pdata.cap_mask);
315 amba_device_register(&exynos_pdma1_device, &iomem_resource);
316
317 dma_cap_set(DMA_MEMCPY, exynos_mdma1_pdata.cap_mask);
318 amba_device_register(&exynos_mdma1_device, &iomem_resource);
319
320 return 0;
321}
322arch_initcall(exynos_dma_init);
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index 9f1351de52f7..beb946d86fa3 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -84,7 +84,6 @@ static struct exynos_pm_domain PD = { \
84 }, \ 84 }, \
85} 85}
86 86
87#ifdef CONFIG_OF
88static void exynos_add_device_to_domain(struct exynos_pm_domain *pd, 87static void exynos_add_device_to_domain(struct exynos_pm_domain *pd,
89 struct device *dev) 88 struct device *dev)
90{ 89{
@@ -193,12 +192,6 @@ static __init int exynos_pm_dt_parse_domains(void)
193 192
194 return 0; 193 return 0;
195} 194}
196#else
197static __init int exynos_pm_dt_parse_domains(void)
198{
199 return 0;
200}
201#endif /* CONFIG_OF */
202 195
203static __init __maybe_unused void exynos_pm_add_dev_to_genpd(struct platform_device *pdev, 196static __init __maybe_unused void exynos_pm_add_dev_to_genpd(struct platform_device *pdev,
204 struct exynos_pm_domain *pd) 197 struct exynos_pm_domain *pd)
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-01 15:25:24 -0500