diff options
| author | Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> | 2015-03-26 13:32:56 -0400 |
|---|---|---|
| committer | Kukjin Kim <kgene@kernel.org> | 2015-03-26 13:32:56 -0400 |
| commit | 497ab3b30c7687f52e6711e2ac72d1b696ec7685 (patch) | |
| tree | 54220f51a7de1ee57e7787c3fa2d03fca9e99cff /arch/arm/mach-exynos/regs-pmu.h | |
| parent | 4e330ae4ab2915444f1e6dca1358a910aa259362 (diff) | |
ARM: EXYNOS: fix CPU1 hotplug on Exynos3250
CPU1 hotplug may hang when AFTR is used. Fix it by:
- setting AUTOWAKEUP_EN bit in ARM_COREx_CONFIGURATION register in
exynos_cpu_power_up()
- not clearing reserved bits of ARM_COREx_CONFIGURATION register in
exynos_cpu_power_down()
- waiting while an undocumented register 0x0908 becomes non-zero in
exynos_core_restart()
- using dsb_sev() instead of IPI in exynos_boot_secondary() on
Exynos3250
This patch also fixes hotplug issues during resume from S2R:
$ echo mem > /sys/power/state
[ 156.517266] Disabling non-boot CPUs ...
[ 156.517781] IRQ18 no longer affine to CPU1
[ 156.518043] CPU1: shutdown
[ 156.544718] Enabling non-boot CPUs ...
[ 156.554925] CPU1: Software reset
[ 158.552631] CPU1: failed to come online
[ 158.552753] Error taking CPU1 up: -5
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
Diffstat (limited to 'arch/arm/mach-exynos/regs-pmu.h')
| -rw-r--r-- | arch/arm/mach-exynos/regs-pmu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h index eb461e1c325a..84ddce142ab1 100644 --- a/arch/arm/mach-exynos/regs-pmu.h +++ b/arch/arm/mach-exynos/regs-pmu.h | |||
| @@ -49,6 +49,7 @@ | |||
| 49 | #define S5P_INFORM5 0x0814 | 49 | #define S5P_INFORM5 0x0814 |
| 50 | #define S5P_INFORM6 0x0818 | 50 | #define S5P_INFORM6 0x0818 |
| 51 | #define S5P_INFORM7 0x081C | 51 | #define S5P_INFORM7 0x081C |
| 52 | #define S5P_PMU_SPARE2 0x0908 | ||
| 52 | #define S5P_PMU_SPARE3 0x090C | 53 | #define S5P_PMU_SPARE3 0x090C |
| 53 | 54 | ||
| 54 | #define EXYNOS_IROM_DATA2 0x0988 | 55 | #define EXYNOS_IROM_DATA2 0x0988 |
| @@ -182,6 +183,7 @@ | |||
| 182 | 183 | ||
| 183 | #define S5P_CORE_LOCAL_PWR_EN 0x3 | 184 | #define S5P_CORE_LOCAL_PWR_EN 0x3 |
| 184 | #define S5P_CORE_WAKEUP_FROM_LOCAL_CFG (0x3 << 8) | 185 | #define S5P_CORE_WAKEUP_FROM_LOCAL_CFG (0x3 << 8) |
| 186 | #define S5P_CORE_AUTOWAKEUP_EN (1 << 31) | ||
| 185 | 187 | ||
| 186 | /* Only for EXYNOS4210 */ | 188 | /* Only for EXYNOS4210 */ |
| 187 | #define S5P_CMU_CLKSTOP_LCD1_LOWPWR 0x1154 | 189 | #define S5P_CMU_CLKSTOP_LCD1_LOWPWR 0x1154 |