diff options
author | Arnd Bergmann <arnd@arndb.de> | 2012-03-19 16:52:33 -0400 |
---|---|---|
committer | Arnd Bergmann <arnd@arndb.de> | 2012-03-20 06:07:48 -0400 |
commit | bde755679a3ba5af0d16231f8532e8373c5e2ecc (patch) | |
tree | 782fa01306ada3e084bd3c47ea1af378b97c0e16 /arch/arm/mach-exynos/include | |
parent | 62a16d025c683fe9e1eada7683095013b96ce9d1 (diff) | |
parent | 44b2cef5ae6da48523fa634230ca66107110a7dd (diff) |
Merge branch 'samsung/cleanup-exynos-clock' into next/soc
Conflicts:
arch/arm/mach-exynos/clock-exynos4.c
arch/arm/mach-exynos/clock.c
The cleanup moves the exynos4 clock implementation away, while
the other branch modifies the file with the old name.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-exynos/include')
-rw-r--r-- | arch/arm/mach-exynos/include/mach/exynos4-clock.h | 43 | ||||
-rw-r--r-- | arch/arm/mach-exynos/include/mach/regs-clock.h | 416 |
2 files changed, 234 insertions, 225 deletions
diff --git a/arch/arm/mach-exynos/include/mach/exynos4-clock.h b/arch/arm/mach-exynos/include/mach/exynos4-clock.h deleted file mode 100644 index a07fcbf55251..000000000000 --- a/arch/arm/mach-exynos/include/mach/exynos4-clock.h +++ /dev/null | |||
@@ -1,43 +0,0 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h | ||
3 | * | ||
4 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | ||
5 | * http://www.samsung.com | ||
6 | * | ||
7 | * Header file for exynos4 clock support | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_CLOCK_H | ||
15 | #define __ASM_ARCH_CLOCK_H __FILE__ | ||
16 | |||
17 | #include <linux/clk.h> | ||
18 | |||
19 | extern struct clk clk_sclk_hdmi27m; | ||
20 | extern struct clk clk_sclk_usbphy0; | ||
21 | extern struct clk clk_sclk_usbphy1; | ||
22 | extern struct clk clk_sclk_hdmiphy; | ||
23 | |||
24 | extern struct clksrc_clk clk_sclk_apll; | ||
25 | extern struct clksrc_clk clk_mout_mpll; | ||
26 | extern struct clksrc_clk clk_aclk_133; | ||
27 | extern struct clksrc_clk clk_mout_epll; | ||
28 | extern struct clksrc_clk clk_sclk_vpll; | ||
29 | |||
30 | extern struct clk *clkset_corebus_list[]; | ||
31 | extern struct clksrc_sources clkset_mout_corebus; | ||
32 | |||
33 | extern struct clk *clkset_aclk_top_list[]; | ||
34 | extern struct clksrc_sources clkset_aclk; | ||
35 | |||
36 | extern struct clk *clkset_group_list[]; | ||
37 | extern struct clksrc_sources clkset_group; | ||
38 | |||
39 | extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable); | ||
40 | extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable); | ||
41 | extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable); | ||
42 | |||
43 | #endif /* __ASM_ARCH_CLOCK_H */ | ||
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h index 6c37ebe94829..1e4abd64a547 100644 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h | |||
@@ -16,195 +16,247 @@ | |||
16 | #include <plat/cpu.h> | 16 | #include <plat/cpu.h> |
17 | #include <mach/map.h> | 17 | #include <mach/map.h> |
18 | 18 | ||
19 | #define S5P_CLKREG(x) (S5P_VA_CMU + (x)) | 19 | #define EXYNOS_CLKREG(x) (S5P_VA_CMU + (x)) |
20 | 20 | ||
21 | #define S5P_CLKDIV_LEFTBUS S5P_CLKREG(0x04500) | 21 | #define EXYNOS4_CLKDIV_LEFTBUS EXYNOS_CLKREG(0x04500) |
22 | #define S5P_CLKDIV_STAT_LEFTBUS S5P_CLKREG(0x04600) | 22 | #define EXYNOS4_CLKDIV_STAT_LEFTBUS EXYNOS_CLKREG(0x04600) |
23 | #define S5P_CLKGATE_IP_LEFTBUS S5P_CLKREG(0x04800) | 23 | #define EXYNOS4_CLKGATE_IP_LEFTBUS EXYNOS_CLKREG(0x04800) |
24 | 24 | ||
25 | #define S5P_CLKDIV_RIGHTBUS S5P_CLKREG(0x08500) | 25 | #define EXYNOS4_CLKDIV_RIGHTBUS EXYNOS_CLKREG(0x08500) |
26 | #define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600) | 26 | #define EXYNOS4_CLKDIV_STAT_RIGHTBUS EXYNOS_CLKREG(0x08600) |
27 | #define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800) | 27 | #define EXYNOS4_CLKGATE_IP_RIGHTBUS EXYNOS_CLKREG(0x08800) |
28 | 28 | ||
29 | #define S5P_EPLL_LOCK S5P_CLKREG(0x0C010) | 29 | #define EXYNOS4_EPLL_LOCK EXYNOS_CLKREG(0x0C010) |
30 | #define S5P_VPLL_LOCK S5P_CLKREG(0x0C020) | 30 | #define EXYNOS4_VPLL_LOCK EXYNOS_CLKREG(0x0C020) |
31 | 31 | ||
32 | #define S5P_EPLL_CON0 S5P_CLKREG(0x0C110) | 32 | #define EXYNOS4_EPLL_CON0 EXYNOS_CLKREG(0x0C110) |
33 | #define S5P_EPLL_CON1 S5P_CLKREG(0x0C114) | 33 | #define EXYNOS4_EPLL_CON1 EXYNOS_CLKREG(0x0C114) |
34 | #define S5P_VPLL_CON0 S5P_CLKREG(0x0C120) | 34 | #define EXYNOS4_VPLL_CON0 EXYNOS_CLKREG(0x0C120) |
35 | #define S5P_VPLL_CON1 S5P_CLKREG(0x0C124) | 35 | #define EXYNOS4_VPLL_CON1 EXYNOS_CLKREG(0x0C124) |
36 | 36 | ||
37 | #define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210) | 37 | #define EXYNOS4_CLKSRC_TOP0 EXYNOS_CLKREG(0x0C210) |
38 | #define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214) | 38 | #define EXYNOS4_CLKSRC_TOP1 EXYNOS_CLKREG(0x0C214) |
39 | #define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220) | 39 | #define EXYNOS4_CLKSRC_CAM EXYNOS_CLKREG(0x0C220) |
40 | #define S5P_CLKSRC_TV S5P_CLKREG(0x0C224) | 40 | #define EXYNOS4_CLKSRC_TV EXYNOS_CLKREG(0x0C224) |
41 | #define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228) | 41 | #define EXYNOS4_CLKSRC_MFC EXYNOS_CLKREG(0x0C228) |
42 | #define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C) | 42 | #define EXYNOS4_CLKSRC_G3D EXYNOS_CLKREG(0x0C22C) |
43 | #define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230) | 43 | #define EXYNOS4_CLKSRC_IMAGE EXYNOS_CLKREG(0x0C230) |
44 | #define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234) | 44 | #define EXYNOS4_CLKSRC_LCD0 EXYNOS_CLKREG(0x0C234) |
45 | #define S5P_CLKSRC_MAUDIO S5P_CLKREG(0x0C23C) | 45 | #define EXYNOS4_CLKSRC_MAUDIO EXYNOS_CLKREG(0x0C23C) |
46 | #define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240) | 46 | #define EXYNOS4_CLKSRC_FSYS EXYNOS_CLKREG(0x0C240) |
47 | #define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250) | 47 | #define EXYNOS4_CLKSRC_PERIL0 EXYNOS_CLKREG(0x0C250) |
48 | #define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254) | 48 | #define EXYNOS4_CLKSRC_PERIL1 EXYNOS_CLKREG(0x0C254) |
49 | 49 | ||
50 | #define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310) | 50 | #define EXYNOS4_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x0C310) |
51 | #define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320) | 51 | #define EXYNOS4_CLKSRC_MASK_CAM EXYNOS_CLKREG(0x0C320) |
52 | #define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324) | 52 | #define EXYNOS4_CLKSRC_MASK_TV EXYNOS_CLKREG(0x0C324) |
53 | #define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334) | 53 | #define EXYNOS4_CLKSRC_MASK_LCD0 EXYNOS_CLKREG(0x0C334) |
54 | #define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C) | 54 | #define EXYNOS4_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x0C33C) |
55 | #define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340) | 55 | #define EXYNOS4_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x0C340) |
56 | #define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350) | 56 | #define EXYNOS4_CLKSRC_MASK_PERIL0 EXYNOS_CLKREG(0x0C350) |
57 | #define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354) | 57 | #define EXYNOS4_CLKSRC_MASK_PERIL1 EXYNOS_CLKREG(0x0C354) |
58 | 58 | ||
59 | #define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510) | 59 | #define EXYNOS4_CLKDIV_TOP EXYNOS_CLKREG(0x0C510) |
60 | #define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520) | 60 | #define EXYNOS4_CLKDIV_CAM EXYNOS_CLKREG(0x0C520) |
61 | #define S5P_CLKDIV_TV S5P_CLKREG(0x0C524) | 61 | #define EXYNOS4_CLKDIV_TV EXYNOS_CLKREG(0x0C524) |
62 | #define S5P_CLKDIV_MFC S5P_CLKREG(0x0C528) | 62 | #define EXYNOS4_CLKDIV_MFC EXYNOS_CLKREG(0x0C528) |
63 | #define S5P_CLKDIV_G3D S5P_CLKREG(0x0C52C) | 63 | #define EXYNOS4_CLKDIV_G3D EXYNOS_CLKREG(0x0C52C) |
64 | #define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530) | 64 | #define EXYNOS4_CLKDIV_IMAGE EXYNOS_CLKREG(0x0C530) |
65 | #define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534) | 65 | #define EXYNOS4_CLKDIV_LCD0 EXYNOS_CLKREG(0x0C534) |
66 | #define S5P_CLKDIV_MAUDIO S5P_CLKREG(0x0C53C) | 66 | #define EXYNOS4_CLKDIV_MAUDIO EXYNOS_CLKREG(0x0C53C) |
67 | #define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540) | 67 | #define EXYNOS4_CLKDIV_FSYS0 EXYNOS_CLKREG(0x0C540) |
68 | #define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544) | 68 | #define EXYNOS4_CLKDIV_FSYS1 EXYNOS_CLKREG(0x0C544) |
69 | #define S5P_CLKDIV_FSYS2 S5P_CLKREG(0x0C548) | 69 | #define EXYNOS4_CLKDIV_FSYS2 EXYNOS_CLKREG(0x0C548) |
70 | #define S5P_CLKDIV_FSYS3 S5P_CLKREG(0x0C54C) | 70 | #define EXYNOS4_CLKDIV_FSYS3 EXYNOS_CLKREG(0x0C54C) |
71 | #define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550) | 71 | #define EXYNOS4_CLKDIV_PERIL0 EXYNOS_CLKREG(0x0C550) |
72 | #define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x0C554) | 72 | #define EXYNOS4_CLKDIV_PERIL1 EXYNOS_CLKREG(0x0C554) |
73 | #define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x0C558) | 73 | #define EXYNOS4_CLKDIV_PERIL2 EXYNOS_CLKREG(0x0C558) |
74 | #define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C) | 74 | #define EXYNOS4_CLKDIV_PERIL3 EXYNOS_CLKREG(0x0C55C) |
75 | #define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560) | 75 | #define EXYNOS4_CLKDIV_PERIL4 EXYNOS_CLKREG(0x0C560) |
76 | #define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564) | 76 | #define EXYNOS4_CLKDIV_PERIL5 EXYNOS_CLKREG(0x0C564) |
77 | #define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580) | 77 | #define EXYNOS4_CLKDIV2_RATIO EXYNOS_CLKREG(0x0C580) |
78 | 78 | ||
79 | #define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610) | 79 | #define EXYNOS4_CLKDIV_STAT_TOP EXYNOS_CLKREG(0x0C610) |
80 | 80 | #define EXYNOS4_CLKDIV_STAT_MFC EXYNOS_CLKREG(0x0C628) | |
81 | #define S5P_CLKGATE_SCLKCAM S5P_CLKREG(0x0C820) | 81 | |
82 | #define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920) | 82 | #define EXYNOS4_CLKGATE_SCLKCAM EXYNOS_CLKREG(0x0C820) |
83 | #define S5P_CLKGATE_IP_TV S5P_CLKREG(0x0C924) | 83 | #define EXYNOS4_CLKGATE_IP_CAM EXYNOS_CLKREG(0x0C920) |
84 | #define S5P_CLKGATE_IP_MFC S5P_CLKREG(0x0C928) | 84 | #define EXYNOS4_CLKGATE_IP_TV EXYNOS_CLKREG(0x0C924) |
85 | #define S5P_CLKGATE_IP_G3D S5P_CLKREG(0x0C92C) | 85 | #define EXYNOS4_CLKGATE_IP_MFC EXYNOS_CLKREG(0x0C928) |
86 | #define S5P_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \ | 86 | #define EXYNOS4_CLKGATE_IP_G3D EXYNOS_CLKREG(0x0C92C) |
87 | S5P_CLKREG(0x0C930) : \ | 87 | #define EXYNOS4_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \ |
88 | S5P_CLKREG(0x04930)) | 88 | EXYNOS_CLKREG(0x0C930) : \ |
89 | #define S5P_CLKGATE_IP_IMAGE_4210 S5P_CLKREG(0x0C930) | 89 | EXYNOS_CLKREG(0x04930)) |
90 | #define S5P_CLKGATE_IP_IMAGE_4212 S5P_CLKREG(0x04930) | 90 | #define EXYNOS4210_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x0C930) |
91 | #define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934) | 91 | #define EXYNOS4212_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x04930) |
92 | #define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940) | 92 | #define EXYNOS4_CLKGATE_IP_LCD0 EXYNOS_CLKREG(0x0C934) |
93 | #define S5P_CLKGATE_IP_GPS S5P_CLKREG(0x0C94C) | 93 | #define EXYNOS4_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x0C940) |
94 | #define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950) | 94 | #define EXYNOS4_CLKGATE_IP_GPS EXYNOS_CLKREG(0x0C94C) |
95 | #define S5P_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \ | 95 | #define EXYNOS4_CLKGATE_IP_PERIL EXYNOS_CLKREG(0x0C950) |
96 | S5P_CLKREG(0x0C960) : \ | 96 | #define EXYNOS4_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \ |
97 | S5P_CLKREG(0x08960)) | 97 | EXYNOS_CLKREG(0x0C960) : \ |
98 | #define S5P_CLKGATE_IP_PERIR_4210 S5P_CLKREG(0x0C960) | 98 | EXYNOS_CLKREG(0x08960)) |
99 | #define S5P_CLKGATE_IP_PERIR_4212 S5P_CLKREG(0x08960) | 99 | #define EXYNOS4210_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x0C960) |
100 | #define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970) | 100 | #define EXYNOS4212_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x08960) |
101 | 101 | #define EXYNOS4_CLKGATE_BLOCK EXYNOS_CLKREG(0x0C970) | |
102 | #define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300) | 102 | |
103 | #define S5P_CLKSRC_DMC S5P_CLKREG(0x10200) | 103 | #define EXYNOS4_CLKSRC_MASK_DMC EXYNOS_CLKREG(0x10300) |
104 | #define S5P_CLKDIV_DMC0 S5P_CLKREG(0x10500) | 104 | #define EXYNOS4_CLKSRC_DMC EXYNOS_CLKREG(0x10200) |
105 | #define S5P_CLKDIV_DMC1 S5P_CLKREG(0x10504) | 105 | #define EXYNOS4_CLKDIV_DMC0 EXYNOS_CLKREG(0x10500) |
106 | #define S5P_CLKDIV_STAT_DMC0 S5P_CLKREG(0x10600) | 106 | #define EXYNOS4_CLKDIV_DMC1 EXYNOS_CLKREG(0x10504) |
107 | #define S5P_CLKGATE_IP_DMC S5P_CLKREG(0x10900) | 107 | #define EXYNOS4_CLKDIV_STAT_DMC0 EXYNOS_CLKREG(0x10600) |
108 | 108 | #define EXYNOS4_CLKDIV_STAT_DMC1 EXYNOS_CLKREG(0x10604) | |
109 | #define S5P_APLL_LOCK S5P_CLKREG(0x14000) | 109 | #define EXYNOS4_CLKGATE_IP_DMC EXYNOS_CLKREG(0x10900) |
110 | #define S5P_MPLL_LOCK (soc_is_exynos4210() ? \ | 110 | |
111 | S5P_CLKREG(0x14004) : \ | 111 | #define EXYNOS4_DMC_PAUSE_CTRL EXYNOS_CLKREG(0x11094) |
112 | S5P_CLKREG(0x10008)) | 112 | #define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0) |
113 | #define S5P_APLL_CON0 S5P_CLKREG(0x14100) | 113 | |
114 | #define S5P_APLL_CON1 S5P_CLKREG(0x14104) | 114 | #define EXYNOS4_APLL_LOCK EXYNOS_CLKREG(0x14000) |
115 | #define S5P_MPLL_CON0 (soc_is_exynos4210() ? \ | 115 | #define EXYNOS4_MPLL_LOCK (soc_is_exynos4210() ? \ |
116 | S5P_CLKREG(0x14108) : \ | 116 | EXYNOS_CLKREG(0x14004) : \ |
117 | S5P_CLKREG(0x10108)) | 117 | EXYNOS_CLKREG(0x10008)) |
118 | #define S5P_MPLL_CON1 (soc_is_exynos4210() ? \ | 118 | #define EXYNOS4_APLL_CON0 EXYNOS_CLKREG(0x14100) |
119 | S5P_CLKREG(0x1410C) : \ | 119 | #define EXYNOS4_APLL_CON1 EXYNOS_CLKREG(0x14104) |
120 | S5P_CLKREG(0x1010C)) | 120 | #define EXYNOS4_MPLL_CON0 (soc_is_exynos4210() ? \ |
121 | 121 | EXYNOS_CLKREG(0x14108) : \ | |
122 | #define S5P_CLKSRC_CPU S5P_CLKREG(0x14200) | 122 | EXYNOS_CLKREG(0x10108)) |
123 | #define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400) | 123 | #define EXYNOS4_MPLL_CON1 (soc_is_exynos4210() ? \ |
124 | 124 | EXYNOS_CLKREG(0x1410C) : \ | |
125 | #define S5P_CLKDIV_CPU S5P_CLKREG(0x14500) | 125 | EXYNOS_CLKREG(0x1010C)) |
126 | #define S5P_CLKDIV_CPU1 S5P_CLKREG(0x14504) | 126 | |
127 | #define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600) | 127 | #define EXYNOS4_CLKSRC_CPU EXYNOS_CLKREG(0x14200) |
128 | #define S5P_CLKDIV_STATCPU1 S5P_CLKREG(0x14604) | 128 | #define EXYNOS4_CLKMUX_STATCPU EXYNOS_CLKREG(0x14400) |
129 | 129 | ||
130 | #define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800) | 130 | #define EXYNOS4_CLKDIV_CPU EXYNOS_CLKREG(0x14500) |
131 | #define S5P_CLKGATE_IP_CPU S5P_CLKREG(0x14900) | 131 | #define EXYNOS4_CLKDIV_CPU1 EXYNOS_CLKREG(0x14504) |
132 | 132 | #define EXYNOS4_CLKDIV_STATCPU EXYNOS_CLKREG(0x14600) | |
133 | #define S5P_APLL_LOCKTIME (0x1C20) /* 300us */ | 133 | #define EXYNOS4_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x14604) |
134 | 134 | ||
135 | #define S5P_APLLCON0_ENABLE_SHIFT (31) | 135 | #define EXYNOS4_CLKGATE_SCLKCPU EXYNOS_CLKREG(0x14800) |
136 | #define S5P_APLLCON0_LOCKED_SHIFT (29) | 136 | #define EXYNOS4_CLKGATE_IP_CPU EXYNOS_CLKREG(0x14900) |
137 | #define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1) | 137 | |
138 | #define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1) | 138 | #define EXYNOS4_APLL_LOCKTIME (0x1C20) /* 300us */ |
139 | 139 | ||
140 | #define S5P_EPLLCON0_ENABLE_SHIFT (31) | 140 | #define EXYNOS4_APLLCON0_ENABLE_SHIFT (31) |
141 | #define S5P_EPLLCON0_LOCKED_SHIFT (29) | 141 | #define EXYNOS4_APLLCON0_LOCKED_SHIFT (29) |
142 | 142 | #define EXYNOS4_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1) | |
143 | #define S5P_VPLLCON0_ENABLE_SHIFT (31) | 143 | #define EXYNOS4_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1) |
144 | #define S5P_VPLLCON0_LOCKED_SHIFT (29) | 144 | |
145 | 145 | #define EXYNOS4_EPLLCON0_ENABLE_SHIFT (31) | |
146 | #define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16) | 146 | #define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29) |
147 | #define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT) | 147 | |
148 | 148 | #define EXYNOS4_VPLLCON0_ENABLE_SHIFT (31) | |
149 | #define S5P_CLKDIV_CPU0_CORE_SHIFT (0) | 149 | #define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29) |
150 | #define S5P_CLKDIV_CPU0_CORE_MASK (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT) | 150 | |
151 | #define S5P_CLKDIV_CPU0_COREM0_SHIFT (4) | 151 | #define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16) |
152 | #define S5P_CLKDIV_CPU0_COREM0_MASK (0x7 << S5P_CLKDIV_CPU0_COREM0_SHIFT) | 152 | #define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT) |
153 | #define S5P_CLKDIV_CPU0_COREM1_SHIFT (8) | 153 | |
154 | #define S5P_CLKDIV_CPU0_COREM1_MASK (0x7 << S5P_CLKDIV_CPU0_COREM1_SHIFT) | 154 | #define EXYNOS4_CLKDIV_CPU0_CORE_SHIFT (0) |
155 | #define S5P_CLKDIV_CPU0_PERIPH_SHIFT (12) | 155 | #define EXYNOS4_CLKDIV_CPU0_CORE_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) |
156 | #define S5P_CLKDIV_CPU0_PERIPH_MASK (0x7 << S5P_CLKDIV_CPU0_PERIPH_SHIFT) | 156 | #define EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT (4) |
157 | #define S5P_CLKDIV_CPU0_ATB_SHIFT (16) | 157 | #define EXYNOS4_CLKDIV_CPU0_COREM0_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) |
158 | #define S5P_CLKDIV_CPU0_ATB_MASK (0x7 << S5P_CLKDIV_CPU0_ATB_SHIFT) | 158 | #define EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT (8) |
159 | #define S5P_CLKDIV_CPU0_PCLKDBG_SHIFT (20) | 159 | #define EXYNOS4_CLKDIV_CPU0_COREM1_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) |
160 | #define S5P_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) | 160 | #define EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT (12) |
161 | #define S5P_CLKDIV_CPU0_APLL_SHIFT (24) | 161 | #define EXYNOS4_CLKDIV_CPU0_PERIPH_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) |
162 | #define S5P_CLKDIV_CPU0_APLL_MASK (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT) | 162 | #define EXYNOS4_CLKDIV_CPU0_ATB_SHIFT (16) |
163 | 163 | #define EXYNOS4_CLKDIV_CPU0_ATB_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) | |
164 | #define S5P_CLKDIV_DMC0_ACP_SHIFT (0) | 164 | #define EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT (20) |
165 | #define S5P_CLKDIV_DMC0_ACP_MASK (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT) | 165 | #define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) |
166 | #define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT (4) | 166 | #define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT (24) |
167 | #define S5P_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) | 167 | #define EXYNOS4_CLKDIV_CPU0_APLL_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT) |
168 | #define S5P_CLKDIV_DMC0_DPHY_SHIFT (8) | 168 | #define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT 28 |
169 | #define S5P_CLKDIV_DMC0_DPHY_MASK (0x7 << S5P_CLKDIV_DMC0_DPHY_SHIFT) | 169 | #define EXYNOS4_CLKDIV_CPU0_CORE2_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT) |
170 | #define S5P_CLKDIV_DMC0_DMC_SHIFT (12) | 170 | |
171 | #define S5P_CLKDIV_DMC0_DMC_MASK (0x7 << S5P_CLKDIV_DMC0_DMC_SHIFT) | 171 | #define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT 0 |
172 | #define S5P_CLKDIV_DMC0_DMCD_SHIFT (16) | 172 | #define EXYNOS4_CLKDIV_CPU1_COPY_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT) |
173 | #define S5P_CLKDIV_DMC0_DMCD_MASK (0x7 << S5P_CLKDIV_DMC0_DMCD_SHIFT) | 173 | #define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT 4 |
174 | #define S5P_CLKDIV_DMC0_DMCP_SHIFT (20) | 174 | #define EXYNOS4_CLKDIV_CPU1_HPM_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT) |
175 | #define S5P_CLKDIV_DMC0_DMCP_MASK (0x7 << S5P_CLKDIV_DMC0_DMCP_SHIFT) | 175 | #define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT 8 |
176 | #define S5P_CLKDIV_DMC0_COPY2_SHIFT (24) | 176 | #define EXYNOS4_CLKDIV_CPU1_CORES_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT) |
177 | #define S5P_CLKDIV_DMC0_COPY2_MASK (0x7 << S5P_CLKDIV_DMC0_COPY2_SHIFT) | 177 | |
178 | #define S5P_CLKDIV_DMC0_CORETI_SHIFT (28) | 178 | #define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0) |
179 | #define S5P_CLKDIV_DMC0_CORETI_MASK (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT) | 179 | #define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) |
180 | 180 | #define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4) | |
181 | #define S5P_CLKDIV_TOP_ACLK200_SHIFT (0) | 181 | #define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) |
182 | #define S5P_CLKDIV_TOP_ACLK200_MASK (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT) | 182 | #define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8) |
183 | #define S5P_CLKDIV_TOP_ACLK100_SHIFT (4) | 183 | #define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) |
184 | #define S5P_CLKDIV_TOP_ACLK100_MASK (0xf << S5P_CLKDIV_TOP_ACLK100_SHIFT) | 184 | #define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12) |
185 | #define S5P_CLKDIV_TOP_ACLK160_SHIFT (8) | 185 | #define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) |
186 | #define S5P_CLKDIV_TOP_ACLK160_MASK (0x7 << S5P_CLKDIV_TOP_ACLK160_SHIFT) | 186 | #define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16) |
187 | #define S5P_CLKDIV_TOP_ACLK133_SHIFT (12) | 187 | #define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) |
188 | #define S5P_CLKDIV_TOP_ACLK133_MASK (0x7 << S5P_CLKDIV_TOP_ACLK133_SHIFT) | 188 | #define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20) |
189 | #define S5P_CLKDIV_TOP_ONENAND_SHIFT (16) | 189 | #define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT) |
190 | #define S5P_CLKDIV_TOP_ONENAND_MASK (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT) | 190 | #define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24) |
191 | 191 | #define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT) | |
192 | #define S5P_CLKDIV_BUS_GDLR_SHIFT (0) | 192 | #define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28) |
193 | #define S5P_CLKDIV_BUS_GDLR_MASK (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT) | 193 | #define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT) |
194 | #define S5P_CLKDIV_BUS_GPLR_SHIFT (4) | 194 | |
195 | #define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT) | 195 | #define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0) |
196 | #define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT) | ||
197 | #define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4) | ||
198 | #define EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT) | ||
199 | #define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8) | ||
200 | #define EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT) | ||
201 | #define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12) | ||
202 | #define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT) | ||
203 | #define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16) | ||
204 | #define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT) | ||
205 | #define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24) | ||
206 | #define EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT) | ||
207 | |||
208 | #define EXYNOS4_CLKDIV_MFC_SHIFT (0) | ||
209 | #define EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT) | ||
210 | |||
211 | #define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0) | ||
212 | #define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT) | ||
213 | #define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4) | ||
214 | #define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) | ||
215 | #define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8) | ||
216 | #define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) | ||
217 | #define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12) | ||
218 | #define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) | ||
219 | #define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16) | ||
220 | #define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT) | ||
221 | #define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20) | ||
222 | #define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT) | ||
223 | #define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24) | ||
224 | #define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT) | ||
225 | |||
226 | #define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0) | ||
227 | #define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) | ||
228 | #define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4) | ||
229 | #define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT) | ||
230 | |||
231 | #define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0) | ||
232 | #define EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT) | ||
233 | #define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4) | ||
234 | #define EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT) | ||
235 | #define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8) | ||
236 | #define EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT) | ||
237 | #define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12) | ||
238 | #define EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT) | ||
196 | 239 | ||
197 | /* Only for EXYNOS4210 */ | 240 | /* Only for EXYNOS4210 */ |
198 | 241 | ||
199 | #define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238) | 242 | #define EXYNOS4210_CLKSRC_LCD1 EXYNOS_CLKREG(0x0C238) |
200 | #define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338) | 243 | #define EXYNOS4210_CLKSRC_MASK_LCD1 EXYNOS_CLKREG(0x0C338) |
201 | #define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538) | 244 | #define EXYNOS4210_CLKDIV_LCD1 EXYNOS_CLKREG(0x0C538) |
202 | #define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938) | 245 | #define EXYNOS4210_CLKGATE_IP_LCD1 EXYNOS_CLKREG(0x0C938) |
246 | |||
247 | /* Only for EXYNOS4212 */ | ||
248 | |||
249 | #define EXYNOS4_CLKDIV_CAM1 EXYNOS_CLKREG(0x0C568) | ||
250 | |||
251 | #define EXYNOS4_CLKDIV_STAT_CAM1 EXYNOS_CLKREG(0x0C668) | ||
252 | |||
253 | #define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0) | ||
254 | #define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT) | ||
203 | 255 | ||
204 | /* Compatibility defines and inclusion */ | 256 | /* Compatibility defines and inclusion */ |
205 | 257 | ||
206 | #include <mach/regs-pmu.h> | 258 | #include <mach/regs-pmu.h> |
207 | 259 | ||
208 | #define S5P_EPLL_CON S5P_EPLL_CON0 | 260 | #define S5P_EPLL_CON EXYNOS4_EPLL_CON0 |
209 | 261 | ||
210 | #endif /* __ASM_ARCH_REGS_CLOCK_H */ | 262 | #endif /* __ASM_ARCH_REGS_CLOCK_H */ |