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authorLinus Torvalds <torvalds@linux-foundation.org>2013-07-02 16:43:38 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-07-02 16:43:38 -0400
commit3883cbb6c1bda013a3ce2dbdab7dc97c52e4a232 (patch)
tree5b69f83b049d24ac81123ac954ca8c9128e48443 /arch/arm/mach-exynos/include
parentd2033f2c1d1de2239ded15e478ddb4028f192a15 (diff)
parent1eb92b24e243085d242cf5ffd64829bba70972e1 (diff)
Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC specific changes from Arnd Bergmann: "These changes are all to SoC-specific code, a total of 33 branches on 17 platforms were pulled into this. Like last time, Renesas sh-mobile is now the platform with the most changes, followed by OMAP and EXYNOS. Two new platforms, TI Keystone and Rockchips RK3xxx are added in this branch, both containing almost no platform specific code at all, since they are using generic subsystem interfaces for clocks, pinctrl, interrupts etc. The device drivers are getting merged through the respective subsystem maintainer trees. One more SoC (u300) is now multiplatform capable and several others (shmobile, exynos, msm, integrator, kirkwood, clps711x) are moving towards that goal with this series but need more work. Also noteworthy is the work on PCI here, which is traditionally part of the SoC specific code. With the changes done by Thomas Petazzoni, we can now more easily have PCI host controller drivers as loadable modules and keep them separate from the platform code in drivers/pci/host. This has already led to the discovery that three platforms (exynos, spear and imx) are actually using an identical PCIe host controller and will be able to share a driver once support for spear and imx is added." * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (480 commits) ARM: integrator: let pciv3 use mem/premem from device tree ARM: integrator: set local side PCI addresses right ARM: dts: Add pcie controller node for exynos5440-ssdk5440 ARM: dts: Add pcie controller node for Samsung EXYNOS5440 SoC ARM: EXYNOS: Enable PCIe support for Exynos5440 pci: Add PCIe driver for Samsung Exynos ARM: OMAP5: voltagedomain data: remove temporary OMAP4 voltage data ARM: keystone: Move CPU bringup code to dedicated asm file ARM: multiplatform: always pick one CPU type ARM: imx: select syscon for IMX6SL ARM: keystone: select ARM_ERRATA_798181 only for SMP ARM: imx: Synertronixx scb9328 needs to select SOC_IMX1 ARM: OMAP2+: AM43x: resolve SMP related build error dmaengine: edma: enable build for AM33XX ARM: edma: Add EDMA crossbar event mux support ARM: edma: Add DT and runtime PM support to the private EDMA API dmaengine: edma: Add TI EDMA device tree binding arm: add basic support for Rockchip RK3066a boards arm: add debug uarts for rockchip rk29xx and rk3xxx series arm: Add basic clocks for Rockchip rk3066a SoCs ...
Diffstat (limited to 'arch/arm/mach-exynos/include')
-rw-r--r--arch/arm/mach-exynos/include/mach/gpio.h289
-rw-r--r--arch/arm/mach-exynos/include/mach/irqs.h476
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h214
-rw-r--r--arch/arm/mach-exynos/include/mach/pm-core.h12
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-gpio.h40
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-usb-phy.h74
6 files changed, 6 insertions, 1099 deletions
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
deleted file mode 100644
index eb24f1eb8e3b..000000000000
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ /dev/null
@@ -1,289 +0,0 @@
1/*
2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS - GPIO lib support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef __ASM_ARCH_GPIO_H
13#define __ASM_ARCH_GPIO_H __FILE__
14
15/* Macro for EXYNOS GPIO numbering */
16
17#define EXYNOS_GPIO_NEXT(__gpio) \
18 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
19
20/* EXYNOS4 GPIO bank sizes */
21
22#define EXYNOS4_GPIO_A0_NR (8)
23#define EXYNOS4_GPIO_A1_NR (6)
24#define EXYNOS4_GPIO_B_NR (8)
25#define EXYNOS4_GPIO_C0_NR (5)
26#define EXYNOS4_GPIO_C1_NR (5)
27#define EXYNOS4_GPIO_D0_NR (4)
28#define EXYNOS4_GPIO_D1_NR (4)
29#define EXYNOS4_GPIO_E0_NR (5)
30#define EXYNOS4_GPIO_E1_NR (8)
31#define EXYNOS4_GPIO_E2_NR (6)
32#define EXYNOS4_GPIO_E3_NR (8)
33#define EXYNOS4_GPIO_E4_NR (8)
34#define EXYNOS4_GPIO_F0_NR (8)
35#define EXYNOS4_GPIO_F1_NR (8)
36#define EXYNOS4_GPIO_F2_NR (8)
37#define EXYNOS4_GPIO_F3_NR (6)
38#define EXYNOS4_GPIO_J0_NR (8)
39#define EXYNOS4_GPIO_J1_NR (5)
40#define EXYNOS4_GPIO_K0_NR (7)
41#define EXYNOS4_GPIO_K1_NR (7)
42#define EXYNOS4_GPIO_K2_NR (7)
43#define EXYNOS4_GPIO_K3_NR (7)
44#define EXYNOS4_GPIO_L0_NR (8)
45#define EXYNOS4_GPIO_L1_NR (3)
46#define EXYNOS4_GPIO_L2_NR (8)
47#define EXYNOS4_GPIO_X0_NR (8)
48#define EXYNOS4_GPIO_X1_NR (8)
49#define EXYNOS4_GPIO_X2_NR (8)
50#define EXYNOS4_GPIO_X3_NR (8)
51#define EXYNOS4_GPIO_Y0_NR (6)
52#define EXYNOS4_GPIO_Y1_NR (4)
53#define EXYNOS4_GPIO_Y2_NR (6)
54#define EXYNOS4_GPIO_Y3_NR (8)
55#define EXYNOS4_GPIO_Y4_NR (8)
56#define EXYNOS4_GPIO_Y5_NR (8)
57#define EXYNOS4_GPIO_Y6_NR (8)
58#define EXYNOS4_GPIO_Z_NR (7)
59
60/* EXYNOS4 GPIO bank numbers */
61
62enum exynos4_gpio_number {
63 EXYNOS4_GPIO_A0_START = 0,
64 EXYNOS4_GPIO_A1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A0),
65 EXYNOS4_GPIO_B_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A1),
66 EXYNOS4_GPIO_C0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_B),
67 EXYNOS4_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C0),
68 EXYNOS4_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C1),
69 EXYNOS4_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0),
70 EXYNOS4_GPIO_E0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
71 EXYNOS4_GPIO_E1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E0),
72 EXYNOS4_GPIO_E2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E1),
73 EXYNOS4_GPIO_E3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E2),
74 EXYNOS4_GPIO_E4_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E3),
75 EXYNOS4_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E4),
76 EXYNOS4_GPIO_F1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F0),
77 EXYNOS4_GPIO_F2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F1),
78 EXYNOS4_GPIO_F3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),
79 EXYNOS4_GPIO_J0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F3),
80 EXYNOS4_GPIO_J1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J0),
81 EXYNOS4_GPIO_K0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J1),
82 EXYNOS4_GPIO_K1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K0),
83 EXYNOS4_GPIO_K2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K1),
84 EXYNOS4_GPIO_K3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K2),
85 EXYNOS4_GPIO_L0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K3),
86 EXYNOS4_GPIO_L1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L0),
87 EXYNOS4_GPIO_L2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L1),
88 EXYNOS4_GPIO_X0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L2),
89 EXYNOS4_GPIO_X1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X0),
90 EXYNOS4_GPIO_X2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X1),
91 EXYNOS4_GPIO_X3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X2),
92 EXYNOS4_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X3),
93 EXYNOS4_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y0),
94 EXYNOS4_GPIO_Y2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y1),
95 EXYNOS4_GPIO_Y3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y2),
96 EXYNOS4_GPIO_Y4_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y3),
97 EXYNOS4_GPIO_Y5_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y4),
98 EXYNOS4_GPIO_Y6_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y5),
99 EXYNOS4_GPIO_Z_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y6),
100};
101
102/* EXYNOS4 GPIO number definitions */
103
104#define EXYNOS4_GPA0(_nr) (EXYNOS4_GPIO_A0_START + (_nr))
105#define EXYNOS4_GPA1(_nr) (EXYNOS4_GPIO_A1_START + (_nr))
106#define EXYNOS4_GPB(_nr) (EXYNOS4_GPIO_B_START + (_nr))
107#define EXYNOS4_GPC0(_nr) (EXYNOS4_GPIO_C0_START + (_nr))
108#define EXYNOS4_GPC1(_nr) (EXYNOS4_GPIO_C1_START + (_nr))
109#define EXYNOS4_GPD0(_nr) (EXYNOS4_GPIO_D0_START + (_nr))
110#define EXYNOS4_GPD1(_nr) (EXYNOS4_GPIO_D1_START + (_nr))
111#define EXYNOS4_GPE0(_nr) (EXYNOS4_GPIO_E0_START + (_nr))
112#define EXYNOS4_GPE1(_nr) (EXYNOS4_GPIO_E1_START + (_nr))
113#define EXYNOS4_GPE2(_nr) (EXYNOS4_GPIO_E2_START + (_nr))
114#define EXYNOS4_GPE3(_nr) (EXYNOS4_GPIO_E3_START + (_nr))
115#define EXYNOS4_GPE4(_nr) (EXYNOS4_GPIO_E4_START + (_nr))
116#define EXYNOS4_GPF0(_nr) (EXYNOS4_GPIO_F0_START + (_nr))
117#define EXYNOS4_GPF1(_nr) (EXYNOS4_GPIO_F1_START + (_nr))
118#define EXYNOS4_GPF2(_nr) (EXYNOS4_GPIO_F2_START + (_nr))
119#define EXYNOS4_GPF3(_nr) (EXYNOS4_GPIO_F3_START + (_nr))
120#define EXYNOS4_GPJ0(_nr) (EXYNOS4_GPIO_J0_START + (_nr))
121#define EXYNOS4_GPJ1(_nr) (EXYNOS4_GPIO_J1_START + (_nr))
122#define EXYNOS4_GPK0(_nr) (EXYNOS4_GPIO_K0_START + (_nr))
123#define EXYNOS4_GPK1(_nr) (EXYNOS4_GPIO_K1_START + (_nr))
124#define EXYNOS4_GPK2(_nr) (EXYNOS4_GPIO_K2_START + (_nr))
125#define EXYNOS4_GPK3(_nr) (EXYNOS4_GPIO_K3_START + (_nr))
126#define EXYNOS4_GPL0(_nr) (EXYNOS4_GPIO_L0_START + (_nr))
127#define EXYNOS4_GPL1(_nr) (EXYNOS4_GPIO_L1_START + (_nr))
128#define EXYNOS4_GPL2(_nr) (EXYNOS4_GPIO_L2_START + (_nr))
129#define EXYNOS4_GPX0(_nr) (EXYNOS4_GPIO_X0_START + (_nr))
130#define EXYNOS4_GPX1(_nr) (EXYNOS4_GPIO_X1_START + (_nr))
131#define EXYNOS4_GPX2(_nr) (EXYNOS4_GPIO_X2_START + (_nr))
132#define EXYNOS4_GPX3(_nr) (EXYNOS4_GPIO_X3_START + (_nr))
133#define EXYNOS4_GPY0(_nr) (EXYNOS4_GPIO_Y0_START + (_nr))
134#define EXYNOS4_GPY1(_nr) (EXYNOS4_GPIO_Y1_START + (_nr))
135#define EXYNOS4_GPY2(_nr) (EXYNOS4_GPIO_Y2_START + (_nr))
136#define EXYNOS4_GPY3(_nr) (EXYNOS4_GPIO_Y3_START + (_nr))
137#define EXYNOS4_GPY4(_nr) (EXYNOS4_GPIO_Y4_START + (_nr))
138#define EXYNOS4_GPY5(_nr) (EXYNOS4_GPIO_Y5_START + (_nr))
139#define EXYNOS4_GPY6(_nr) (EXYNOS4_GPIO_Y6_START + (_nr))
140#define EXYNOS4_GPZ(_nr) (EXYNOS4_GPIO_Z_START + (_nr))
141
142/* the end of the EXYNOS4 specific gpios */
143
144#define EXYNOS4_GPIO_END (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1)
145
146/* EXYNOS5 GPIO bank sizes */
147
148#define EXYNOS5_GPIO_A0_NR (8)
149#define EXYNOS5_GPIO_A1_NR (6)
150#define EXYNOS5_GPIO_A2_NR (8)
151#define EXYNOS5_GPIO_B0_NR (5)
152#define EXYNOS5_GPIO_B1_NR (5)
153#define EXYNOS5_GPIO_B2_NR (4)
154#define EXYNOS5_GPIO_B3_NR (4)
155#define EXYNOS5_GPIO_C0_NR (7)
156#define EXYNOS5_GPIO_C1_NR (4)
157#define EXYNOS5_GPIO_C2_NR (7)
158#define EXYNOS5_GPIO_C3_NR (7)
159#define EXYNOS5_GPIO_C4_NR (7)
160#define EXYNOS5_GPIO_D0_NR (4)
161#define EXYNOS5_GPIO_D1_NR (8)
162#define EXYNOS5_GPIO_Y0_NR (6)
163#define EXYNOS5_GPIO_Y1_NR (4)
164#define EXYNOS5_GPIO_Y2_NR (6)
165#define EXYNOS5_GPIO_Y3_NR (8)
166#define EXYNOS5_GPIO_Y4_NR (8)
167#define EXYNOS5_GPIO_Y5_NR (8)
168#define EXYNOS5_GPIO_Y6_NR (8)
169#define EXYNOS5_GPIO_X0_NR (8)
170#define EXYNOS5_GPIO_X1_NR (8)
171#define EXYNOS5_GPIO_X2_NR (8)
172#define EXYNOS5_GPIO_X3_NR (8)
173#define EXYNOS5_GPIO_E0_NR (8)
174#define EXYNOS5_GPIO_E1_NR (2)
175#define EXYNOS5_GPIO_F0_NR (4)
176#define EXYNOS5_GPIO_F1_NR (4)
177#define EXYNOS5_GPIO_G0_NR (8)
178#define EXYNOS5_GPIO_G1_NR (8)
179#define EXYNOS5_GPIO_G2_NR (2)
180#define EXYNOS5_GPIO_H0_NR (4)
181#define EXYNOS5_GPIO_H1_NR (8)
182#define EXYNOS5_GPIO_V0_NR (8)
183#define EXYNOS5_GPIO_V1_NR (8)
184#define EXYNOS5_GPIO_V2_NR (8)
185#define EXYNOS5_GPIO_V3_NR (8)
186#define EXYNOS5_GPIO_V4_NR (2)
187#define EXYNOS5_GPIO_Z_NR (7)
188
189/* EXYNOS5 GPIO bank numbers */
190
191enum exynos5_gpio_number {
192 EXYNOS5_GPIO_A0_START = 0,
193 EXYNOS5_GPIO_A1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A0),
194 EXYNOS5_GPIO_A2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A1),
195 EXYNOS5_GPIO_B0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A2),
196 EXYNOS5_GPIO_B1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B0),
197 EXYNOS5_GPIO_B2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B1),
198 EXYNOS5_GPIO_B3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B2),
199 EXYNOS5_GPIO_C0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B3),
200 EXYNOS5_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
201 EXYNOS5_GPIO_C2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
202 EXYNOS5_GPIO_C3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
203 EXYNOS5_GPIO_C4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
204 EXYNOS5_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4),
205 EXYNOS5_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
206 EXYNOS5_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
207 EXYNOS5_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),
208 EXYNOS5_GPIO_Y2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y1),
209 EXYNOS5_GPIO_Y3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y2),
210 EXYNOS5_GPIO_Y4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y3),
211 EXYNOS5_GPIO_Y5_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y4),
212 EXYNOS5_GPIO_Y6_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y5),
213 EXYNOS5_GPIO_X0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y6),
214 EXYNOS5_GPIO_X1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X0),
215 EXYNOS5_GPIO_X2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X1),
216 EXYNOS5_GPIO_X3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X2),
217 EXYNOS5_GPIO_E0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X3),
218 EXYNOS5_GPIO_E1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E0),
219 EXYNOS5_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E1),
220 EXYNOS5_GPIO_F1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F0),
221 EXYNOS5_GPIO_G0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F1),
222 EXYNOS5_GPIO_G1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G0),
223 EXYNOS5_GPIO_G2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G1),
224 EXYNOS5_GPIO_H0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G2),
225 EXYNOS5_GPIO_H1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H0),
226 EXYNOS5_GPIO_V0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H1),
227 EXYNOS5_GPIO_V1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V0),
228 EXYNOS5_GPIO_V2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V1),
229 EXYNOS5_GPIO_V3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V2),
230 EXYNOS5_GPIO_V4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V3),
231 EXYNOS5_GPIO_Z_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V4),
232};
233
234/* EXYNOS5 GPIO number definitions */
235
236#define EXYNOS5_GPA0(_nr) (EXYNOS5_GPIO_A0_START + (_nr))
237#define EXYNOS5_GPA1(_nr) (EXYNOS5_GPIO_A1_START + (_nr))
238#define EXYNOS5_GPA2(_nr) (EXYNOS5_GPIO_A2_START + (_nr))
239#define EXYNOS5_GPB0(_nr) (EXYNOS5_GPIO_B0_START + (_nr))
240#define EXYNOS5_GPB1(_nr) (EXYNOS5_GPIO_B1_START + (_nr))
241#define EXYNOS5_GPB2(_nr) (EXYNOS5_GPIO_B2_START + (_nr))
242#define EXYNOS5_GPB3(_nr) (EXYNOS5_GPIO_B3_START + (_nr))
243#define EXYNOS5_GPC0(_nr) (EXYNOS5_GPIO_C0_START + (_nr))
244#define EXYNOS5_GPC1(_nr) (EXYNOS5_GPIO_C1_START + (_nr))
245#define EXYNOS5_GPC2(_nr) (EXYNOS5_GPIO_C2_START + (_nr))
246#define EXYNOS5_GPC3(_nr) (EXYNOS5_GPIO_C3_START + (_nr))
247#define EXYNOS5_GPC4(_nr) (EXYNOS5_GPIO_C4_START + (_nr))
248#define EXYNOS5_GPD0(_nr) (EXYNOS5_GPIO_D0_START + (_nr))
249#define EXYNOS5_GPD1(_nr) (EXYNOS5_GPIO_D1_START + (_nr))
250#define EXYNOS5_GPY0(_nr) (EXYNOS5_GPIO_Y0_START + (_nr))
251#define EXYNOS5_GPY1(_nr) (EXYNOS5_GPIO_Y1_START + (_nr))
252#define EXYNOS5_GPY2(_nr) (EXYNOS5_GPIO_Y2_START + (_nr))
253#define EXYNOS5_GPY3(_nr) (EXYNOS5_GPIO_Y3_START + (_nr))
254#define EXYNOS5_GPY4(_nr) (EXYNOS5_GPIO_Y4_START + (_nr))
255#define EXYNOS5_GPY5(_nr) (EXYNOS5_GPIO_Y5_START + (_nr))
256#define EXYNOS5_GPY6(_nr) (EXYNOS5_GPIO_Y6_START + (_nr))
257#define EXYNOS5_GPX0(_nr) (EXYNOS5_GPIO_X0_START + (_nr))
258#define EXYNOS5_GPX1(_nr) (EXYNOS5_GPIO_X1_START + (_nr))
259#define EXYNOS5_GPX2(_nr) (EXYNOS5_GPIO_X2_START + (_nr))
260#define EXYNOS5_GPX3(_nr) (EXYNOS5_GPIO_X3_START + (_nr))
261#define EXYNOS5_GPE0(_nr) (EXYNOS5_GPIO_E0_START + (_nr))
262#define EXYNOS5_GPE1(_nr) (EXYNOS5_GPIO_E1_START + (_nr))
263#define EXYNOS5_GPF0(_nr) (EXYNOS5_GPIO_F0_START + (_nr))
264#define EXYNOS5_GPF1(_nr) (EXYNOS5_GPIO_F1_START + (_nr))
265#define EXYNOS5_GPG0(_nr) (EXYNOS5_GPIO_G0_START + (_nr))
266#define EXYNOS5_GPG1(_nr) (EXYNOS5_GPIO_G1_START + (_nr))
267#define EXYNOS5_GPG2(_nr) (EXYNOS5_GPIO_G2_START + (_nr))
268#define EXYNOS5_GPH0(_nr) (EXYNOS5_GPIO_H0_START + (_nr))
269#define EXYNOS5_GPH1(_nr) (EXYNOS5_GPIO_H1_START + (_nr))
270#define EXYNOS5_GPV0(_nr) (EXYNOS5_GPIO_V0_START + (_nr))
271#define EXYNOS5_GPV1(_nr) (EXYNOS5_GPIO_V1_START + (_nr))
272#define EXYNOS5_GPV2(_nr) (EXYNOS5_GPIO_V2_START + (_nr))
273#define EXYNOS5_GPV3(_nr) (EXYNOS5_GPIO_V3_START + (_nr))
274#define EXYNOS5_GPV4(_nr) (EXYNOS5_GPIO_V4_START + (_nr))
275#define EXYNOS5_GPZ(_nr) (EXYNOS5_GPIO_Z_START + (_nr))
276
277/* the end of the EXYNOS5 specific gpios */
278
279#define EXYNOS5_GPIO_END (EXYNOS5_GPZ(EXYNOS5_GPIO_Z_NR) + 1)
280
281/* actually, EXYNOS5_GPIO_END is bigger than EXYNOS4 */
282
283#define S3C_GPIO_END (EXYNOS5_GPIO_END)
284
285/* define the number of gpios */
286
287#define ARCH_NR_GPIOS (CONFIG_SAMSUNG_GPIO_EXTRA + S3C_GPIO_END)
288
289#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
deleted file mode 100644
index c72f59d91fce..000000000000
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ /dev/null
@@ -1,476 +0,0 @@
1/*
2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS - IRQ definitions
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef __ASM_ARCH_IRQS_H
13#define __ASM_ARCH_IRQS_H __FILE__
14
15#include <plat/irqs.h>
16
17/* PPI: Private Peripheral Interrupt */
18
19#define IRQ_PPI(x) (x + 16)
20
21/* SPI: Shared Peripheral Interrupt */
22
23#define IRQ_SPI(x) (x + 32)
24
25/* COMBINER */
26
27#define MAX_IRQ_IN_COMBINER 8
28#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
29#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y)
30
31/* For EXYNOS4 and EXYNOS5 */
32
33#define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32)
34
35/* For EXYNOS4 SoCs */
36
37#define EXYNOS4_IRQ_EINT0 IRQ_SPI(16)
38#define EXYNOS4_IRQ_EINT1 IRQ_SPI(17)
39#define EXYNOS4_IRQ_EINT2 IRQ_SPI(18)
40#define EXYNOS4_IRQ_EINT3 IRQ_SPI(19)
41#define EXYNOS4_IRQ_EINT4 IRQ_SPI(20)
42#define EXYNOS4_IRQ_EINT5 IRQ_SPI(21)
43#define EXYNOS4_IRQ_EINT6 IRQ_SPI(22)
44#define EXYNOS4_IRQ_EINT7 IRQ_SPI(23)
45#define EXYNOS4_IRQ_EINT8 IRQ_SPI(24)
46#define EXYNOS4_IRQ_EINT9 IRQ_SPI(25)
47#define EXYNOS4_IRQ_EINT10 IRQ_SPI(26)
48#define EXYNOS4_IRQ_EINT11 IRQ_SPI(27)
49#define EXYNOS4_IRQ_EINT12 IRQ_SPI(28)
50#define EXYNOS4_IRQ_EINT13 IRQ_SPI(29)
51#define EXYNOS4_IRQ_EINT14 IRQ_SPI(30)
52#define EXYNOS4_IRQ_EINT15 IRQ_SPI(31)
53
54#define EXYNOS4_IRQ_MDMA0 IRQ_SPI(33)
55#define EXYNOS4_IRQ_MDMA1 IRQ_SPI(34)
56#define EXYNOS4_IRQ_PDMA0 IRQ_SPI(35)
57#define EXYNOS4_IRQ_PDMA1 IRQ_SPI(36)
58#define EXYNOS4_IRQ_TIMER0_VIC IRQ_SPI(37)
59#define EXYNOS4_IRQ_TIMER1_VIC IRQ_SPI(38)
60#define EXYNOS4_IRQ_TIMER2_VIC IRQ_SPI(39)
61#define EXYNOS4_IRQ_TIMER3_VIC IRQ_SPI(40)
62#define EXYNOS4_IRQ_TIMER4_VIC IRQ_SPI(41)
63#define EXYNOS4_IRQ_MCT_L0 IRQ_SPI(42)
64#define EXYNOS4_IRQ_WDT IRQ_SPI(43)
65#define EXYNOS4_IRQ_RTC_ALARM IRQ_SPI(44)
66#define EXYNOS4_IRQ_RTC_TIC IRQ_SPI(45)
67#define EXYNOS4_IRQ_GPIO_XB IRQ_SPI(46)
68#define EXYNOS4_IRQ_GPIO_XA IRQ_SPI(47)
69#define EXYNOS4_IRQ_MCT_L1 IRQ_SPI(48)
70
71#define EXYNOS4_IRQ_UART0 IRQ_SPI(52)
72#define EXYNOS4_IRQ_UART1 IRQ_SPI(53)
73#define EXYNOS4_IRQ_UART2 IRQ_SPI(54)
74#define EXYNOS4_IRQ_UART3 IRQ_SPI(55)
75#define EXYNOS4_IRQ_UART4 IRQ_SPI(56)
76#define EXYNOS4_IRQ_MCT_G0 IRQ_SPI(57)
77#define EXYNOS4_IRQ_IIC IRQ_SPI(58)
78#define EXYNOS4_IRQ_IIC1 IRQ_SPI(59)
79#define EXYNOS4_IRQ_IIC2 IRQ_SPI(60)
80#define EXYNOS4_IRQ_IIC3 IRQ_SPI(61)
81#define EXYNOS4_IRQ_IIC4 IRQ_SPI(62)
82#define EXYNOS4_IRQ_IIC5 IRQ_SPI(63)
83#define EXYNOS4_IRQ_IIC6 IRQ_SPI(64)
84#define EXYNOS4_IRQ_IIC7 IRQ_SPI(65)
85#define EXYNOS4_IRQ_SPI0 IRQ_SPI(66)
86#define EXYNOS4_IRQ_SPI1 IRQ_SPI(67)
87#define EXYNOS4_IRQ_SPI2 IRQ_SPI(68)
88
89#define EXYNOS4_IRQ_USB_HOST IRQ_SPI(70)
90#define EXYNOS4_IRQ_USB_HSOTG IRQ_SPI(71)
91#define EXYNOS4_IRQ_MODEM_IF IRQ_SPI(72)
92#define EXYNOS4_IRQ_HSMMC0 IRQ_SPI(73)
93#define EXYNOS4_IRQ_HSMMC1 IRQ_SPI(74)
94#define EXYNOS4_IRQ_HSMMC2 IRQ_SPI(75)
95#define EXYNOS4_IRQ_HSMMC3 IRQ_SPI(76)
96#define EXYNOS4_IRQ_DWMCI IRQ_SPI(77)
97
98#define EXYNOS4_IRQ_MIPI_CSIS0 IRQ_SPI(78)
99#define EXYNOS4_IRQ_MIPI_CSIS1 IRQ_SPI(80)
100
101#define EXYNOS4_IRQ_ONENAND_AUDI IRQ_SPI(82)
102#define EXYNOS4_IRQ_ROTATOR IRQ_SPI(83)
103#define EXYNOS4_IRQ_FIMC0 IRQ_SPI(84)
104#define EXYNOS4_IRQ_FIMC1 IRQ_SPI(85)
105#define EXYNOS4_IRQ_FIMC2 IRQ_SPI(86)
106#define EXYNOS4_IRQ_FIMC3 IRQ_SPI(87)
107#define EXYNOS4_IRQ_JPEG IRQ_SPI(88)
108#define EXYNOS4_IRQ_2D IRQ_SPI(89)
109#define EXYNOS4_IRQ_PCIE IRQ_SPI(90)
110
111#define EXYNOS4_IRQ_MIXER IRQ_SPI(91)
112#define EXYNOS4_IRQ_HDMI IRQ_SPI(92)
113#define EXYNOS4_IRQ_IIC_HDMIPHY IRQ_SPI(93)
114#define EXYNOS4_IRQ_MFC IRQ_SPI(94)
115#define EXYNOS4_IRQ_SDO IRQ_SPI(95)
116
117#define EXYNOS4_IRQ_AUDIO_SS IRQ_SPI(96)
118#define EXYNOS4_IRQ_I2S0 IRQ_SPI(97)
119#define EXYNOS4_IRQ_I2S1 IRQ_SPI(98)
120#define EXYNOS4_IRQ_I2S2 IRQ_SPI(99)
121#define EXYNOS4_IRQ_AC97 IRQ_SPI(100)
122
123#define EXYNOS4_IRQ_SPDIF IRQ_SPI(104)
124#define EXYNOS4_IRQ_ADC0 IRQ_SPI(105)
125#define EXYNOS4_IRQ_PEN0 IRQ_SPI(106)
126#define EXYNOS4_IRQ_ADC1 IRQ_SPI(107)
127#define EXYNOS4_IRQ_PEN1 IRQ_SPI(108)
128#define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109)
129#define EXYNOS4_IRQ_POWER_PMU IRQ_SPI(110)
130#define EXYNOS4_IRQ_GPS IRQ_SPI(111)
131#define EXYNOS4_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
132#define EXYNOS4_IRQ_SLIMBUS IRQ_SPI(113)
133
134#define EXYNOS4_IRQ_TSI IRQ_SPI(115)
135#define EXYNOS4_IRQ_SATA IRQ_SPI(116)
136
137#define EXYNOS4_IRQ_PMU COMBINER_IRQ(2, 2)
138#define EXYNOS4_IRQ_PMU_CPU1 COMBINER_IRQ(3, 2)
139#define EXYNOS4_IRQ_PMU_CPU2 COMBINER_IRQ(18, 2)
140#define EXYNOS4_IRQ_PMU_CPU3 COMBINER_IRQ(19, 2)
141
142#define EXYNOS4_IRQ_TMU_TRIG0 COMBINER_IRQ(2, 4)
143#define EXYNOS4_IRQ_TMU_TRIG1 COMBINER_IRQ(3, 4)
144
145#define EXYNOS4_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
146#define EXYNOS4_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1)
147#define EXYNOS4_IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2)
148#define EXYNOS4_IRQ_SYSMMU_FIMC1_0 COMBINER_IRQ(4, 3)
149#define EXYNOS4_IRQ_SYSMMU_FIMC2_0 COMBINER_IRQ(4, 4)
150#define EXYNOS4_IRQ_SYSMMU_FIMC3_0 COMBINER_IRQ(4, 5)
151#define EXYNOS4_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 6)
152#define EXYNOS4_IRQ_SYSMMU_2D_0 COMBINER_IRQ(4, 7)
153
154#define EXYNOS4_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(5, 0)
155#define EXYNOS4_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(5, 1)
156#define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0 COMBINER_IRQ(5, 2)
157#define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0 COMBINER_IRQ(5, 3)
158#define EXYNOS4_IRQ_SYSMMU_TV_M0_0 COMBINER_IRQ(5, 4)
159#define EXYNOS4_IRQ_SYSMMU_MFC_M0_0 COMBINER_IRQ(5, 5)
160#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6)
161#define EXYNOS4_IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7)
162
163#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE0_0 COMBINER_IRQ(16, 0)
164#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE1_0 COMBINER_IRQ(16, 1)
165#define EXYNOS4_IRQ_SYSMMU_FIMC_ISP_0 COMBINER_IRQ(16, 2)
166#define EXYNOS4_IRQ_SYSMMU_FIMC_DRC_0 COMBINER_IRQ(16, 3)
167#define EXYNOS4_IRQ_SYSMMU_FIMC_FD_0 COMBINER_IRQ(16, 4)
168#define EXYNOS4_IRQ_SYSMMU_FIMC_CX_0 COMBINER_IRQ(16, 5)
169
170#define EXYNOS4_IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0)
171#define EXYNOS4_IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
172#define EXYNOS4_IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
173
174#define EXYNOS4210_MAX_COMBINER_NR 16
175#define EXYNOS4212_MAX_COMBINER_NR 18
176#define EXYNOS4412_MAX_COMBINER_NR 20
177#define EXYNOS4_MAX_COMBINER_NR EXYNOS4412_MAX_COMBINER_NR
178
179#define EXYNOS4_IRQ_GPIO1_NR_GROUPS 16
180#define EXYNOS4_IRQ_GPIO2_NR_GROUPS 9
181
182/*
183 * For Compatibility:
184 * the default is for EXYNOS4, and
185 * for exynos5, should be re-mapped at function
186 */
187
188#define IRQ_TIMER0_VIC EXYNOS4_IRQ_TIMER0_VIC
189#define IRQ_TIMER1_VIC EXYNOS4_IRQ_TIMER1_VIC
190#define IRQ_TIMER2_VIC EXYNOS4_IRQ_TIMER2_VIC
191#define IRQ_TIMER3_VIC EXYNOS4_IRQ_TIMER3_VIC
192#define IRQ_TIMER4_VIC EXYNOS4_IRQ_TIMER4_VIC
193
194#define IRQ_WDT EXYNOS4_IRQ_WDT
195#define IRQ_RTC_ALARM EXYNOS4_IRQ_RTC_ALARM
196#define IRQ_RTC_TIC EXYNOS4_IRQ_RTC_TIC
197#define IRQ_GPIO_XB EXYNOS4_IRQ_GPIO_XB
198#define IRQ_GPIO_XA EXYNOS4_IRQ_GPIO_XA
199
200#define IRQ_IIC EXYNOS4_IRQ_IIC
201#define IRQ_IIC1 EXYNOS4_IRQ_IIC1
202#define IRQ_IIC3 EXYNOS4_IRQ_IIC3
203#define IRQ_IIC5 EXYNOS4_IRQ_IIC5
204#define IRQ_IIC6 EXYNOS4_IRQ_IIC6
205#define IRQ_IIC7 EXYNOS4_IRQ_IIC7
206
207#define IRQ_SPI0 EXYNOS4_IRQ_SPI0
208#define IRQ_SPI1 EXYNOS4_IRQ_SPI1
209#define IRQ_SPI2 EXYNOS4_IRQ_SPI2
210
211#define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST
212#define IRQ_OTG EXYNOS4_IRQ_USB_HSOTG
213
214#define IRQ_HSMMC0 EXYNOS4_IRQ_HSMMC0
215#define IRQ_HSMMC1 EXYNOS4_IRQ_HSMMC1
216#define IRQ_HSMMC2 EXYNOS4_IRQ_HSMMC2
217#define IRQ_HSMMC3 EXYNOS4_IRQ_HSMMC3
218
219#define IRQ_MIPI_CSIS0 EXYNOS4_IRQ_MIPI_CSIS0
220
221#define IRQ_ONENAND_AUDI EXYNOS4_IRQ_ONENAND_AUDI
222
223#define IRQ_FIMC0 EXYNOS4_IRQ_FIMC0
224#define IRQ_FIMC1 EXYNOS4_IRQ_FIMC1
225#define IRQ_FIMC2 EXYNOS4_IRQ_FIMC2
226#define IRQ_FIMC3 EXYNOS4_IRQ_FIMC3
227#define IRQ_JPEG EXYNOS4_IRQ_JPEG
228#define IRQ_2D EXYNOS4_IRQ_2D
229
230#define IRQ_MIXER EXYNOS4_IRQ_MIXER
231#define IRQ_HDMI EXYNOS4_IRQ_HDMI
232#define IRQ_IIC_HDMIPHY EXYNOS4_IRQ_IIC_HDMIPHY
233#define IRQ_MFC EXYNOS4_IRQ_MFC
234#define IRQ_SDO EXYNOS4_IRQ_SDO
235
236#define IRQ_I2S0 EXYNOS4_IRQ_I2S0
237
238#define IRQ_ADC EXYNOS4_IRQ_ADC0
239#define IRQ_TC EXYNOS4_IRQ_PEN0
240
241#define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD
242
243#define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO
244#define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC
245#define IRQ_FIMD0_SYSTEM EXYNOS4_IRQ_FIMD0_SYSTEM
246
247#define IRQ_GPIO1_NR_GROUPS EXYNOS4_IRQ_GPIO1_NR_GROUPS
248#define IRQ_GPIO2_NR_GROUPS EXYNOS4_IRQ_GPIO2_NR_GROUPS
249
250/* For EXYNOS5 SoCs */
251
252#define EXYNOS5_IRQ_MDMA0 IRQ_SPI(33)
253#define EXYNOS5_IRQ_PDMA0 IRQ_SPI(34)
254#define EXYNOS5_IRQ_PDMA1 IRQ_SPI(35)
255#define EXYNOS5_IRQ_TIMER0_VIC IRQ_SPI(36)
256#define EXYNOS5_IRQ_TIMER1_VIC IRQ_SPI(37)
257#define EXYNOS5_IRQ_TIMER2_VIC IRQ_SPI(38)
258#define EXYNOS5_IRQ_TIMER3_VIC IRQ_SPI(39)
259#define EXYNOS5_IRQ_TIMER4_VIC IRQ_SPI(40)
260#define EXYNOS5_IRQ_RTIC IRQ_SPI(41)
261#define EXYNOS5_IRQ_WDT IRQ_SPI(42)
262#define EXYNOS5_IRQ_RTC_ALARM IRQ_SPI(43)
263#define EXYNOS5_IRQ_RTC_TIC IRQ_SPI(44)
264#define EXYNOS5_IRQ_GPIO_XB IRQ_SPI(45)
265#define EXYNOS5_IRQ_GPIO_XA IRQ_SPI(46)
266#define EXYNOS5_IRQ_GPIO IRQ_SPI(47)
267#define EXYNOS5_IRQ_IEM_IEC IRQ_SPI(48)
268#define EXYNOS5_IRQ_IEM_APC IRQ_SPI(49)
269#define EXYNOS5_IRQ_GPIO_C2C IRQ_SPI(50)
270#define EXYNOS5_IRQ_IIC IRQ_SPI(56)
271#define EXYNOS5_IRQ_IIC1 IRQ_SPI(57)
272#define EXYNOS5_IRQ_IIC2 IRQ_SPI(58)
273#define EXYNOS5_IRQ_IIC3 IRQ_SPI(59)
274#define EXYNOS5_IRQ_IIC4 IRQ_SPI(60)
275#define EXYNOS5_IRQ_IIC5 IRQ_SPI(61)
276#define EXYNOS5_IRQ_IIC6 IRQ_SPI(62)
277#define EXYNOS5_IRQ_IIC7 IRQ_SPI(63)
278#define EXYNOS5_IRQ_IIC_HDMIPHY IRQ_SPI(64)
279#define EXYNOS5_IRQ_TMU IRQ_SPI(65)
280#define EXYNOS5_IRQ_FIQ_0 IRQ_SPI(66)
281#define EXYNOS5_IRQ_FIQ_1 IRQ_SPI(67)
282#define EXYNOS5_IRQ_SPI0 IRQ_SPI(68)
283#define EXYNOS5_IRQ_SPI1 IRQ_SPI(69)
284#define EXYNOS5_IRQ_SPI2 IRQ_SPI(70)
285#define EXYNOS5_IRQ_USB_HOST IRQ_SPI(71)
286#define EXYNOS5_IRQ_USB3_DRD IRQ_SPI(72)
287#define EXYNOS5_IRQ_MIPI_HSI IRQ_SPI(73)
288#define EXYNOS5_IRQ_USB_HSOTG IRQ_SPI(74)
289#define EXYNOS5_IRQ_HSMMC0 IRQ_SPI(75)
290#define EXYNOS5_IRQ_HSMMC1 IRQ_SPI(76)
291#define EXYNOS5_IRQ_HSMMC2 IRQ_SPI(77)
292#define EXYNOS5_IRQ_HSMMC3 IRQ_SPI(78)
293#define EXYNOS5_IRQ_MIPICSI0 IRQ_SPI(79)
294#define EXYNOS5_IRQ_MIPICSI1 IRQ_SPI(80)
295#define EXYNOS5_IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81)
296#define EXYNOS5_IRQ_MIPIDSI0 IRQ_SPI(82)
297#define EXYNOS5_IRQ_WDT_IOP IRQ_SPI(83)
298#define EXYNOS5_IRQ_ROTATOR IRQ_SPI(84)
299#define EXYNOS5_IRQ_GSC0 IRQ_SPI(85)
300#define EXYNOS5_IRQ_GSC1 IRQ_SPI(86)
301#define EXYNOS5_IRQ_GSC2 IRQ_SPI(87)
302#define EXYNOS5_IRQ_GSC3 IRQ_SPI(88)
303#define EXYNOS5_IRQ_JPEG IRQ_SPI(89)
304#define EXYNOS5_IRQ_EFNFCON_DMA IRQ_SPI(90)
305#define EXYNOS5_IRQ_2D IRQ_SPI(91)
306#define EXYNOS5_IRQ_EFNFCON_0 IRQ_SPI(92)
307#define EXYNOS5_IRQ_EFNFCON_1 IRQ_SPI(93)
308#define EXYNOS5_IRQ_MIXER IRQ_SPI(94)
309#define EXYNOS5_IRQ_HDMI IRQ_SPI(95)
310#define EXYNOS5_IRQ_MFC IRQ_SPI(96)
311#define EXYNOS5_IRQ_AUDIO_SS IRQ_SPI(97)
312#define EXYNOS5_IRQ_I2S0 IRQ_SPI(98)
313#define EXYNOS5_IRQ_I2S1 IRQ_SPI(99)
314#define EXYNOS5_IRQ_I2S2 IRQ_SPI(100)
315#define EXYNOS5_IRQ_AC97 IRQ_SPI(101)
316#define EXYNOS5_IRQ_PCM0 IRQ_SPI(102)
317#define EXYNOS5_IRQ_PCM1 IRQ_SPI(103)
318#define EXYNOS5_IRQ_PCM2 IRQ_SPI(104)
319#define EXYNOS5_IRQ_SPDIF IRQ_SPI(105)
320#define EXYNOS5_IRQ_ADC0 IRQ_SPI(106)
321#define EXYNOS5_IRQ_ADC1 IRQ_SPI(107)
322#define EXYNOS5_IRQ_SATA_PHY IRQ_SPI(108)
323#define EXYNOS5_IRQ_SATA_PMEMREQ IRQ_SPI(109)
324#define EXYNOS5_IRQ_CAM_C IRQ_SPI(110)
325#define EXYNOS5_IRQ_EAGLE_PMU IRQ_SPI(111)
326#define EXYNOS5_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
327#define EXYNOS5_IRQ_DP1_INTP1 IRQ_SPI(113)
328#define EXYNOS5_IRQ_CEC IRQ_SPI(114)
329#define EXYNOS5_IRQ_SATA IRQ_SPI(115)
330
331#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
332#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
333#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
334#define EXYNOS5_IRQ_FIMC_LITE1 IRQ_SPI(126)
335#define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127)
336
337/* EXYNOS5440 */
338
339#define EXYNOS5440_IRQ_UART0 IRQ_SPI(2)
340#define EXYNOS5440_IRQ_UART1 IRQ_SPI(3)
341
342#define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2)
343
344#define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0)
345#define EXYNOS5_IRQ_SYSMMU_GSC0_1 COMBINER_IRQ(2, 1)
346#define EXYNOS5_IRQ_SYSMMU_GSC1_0 COMBINER_IRQ(2, 2)
347#define EXYNOS5_IRQ_SYSMMU_GSC1_1 COMBINER_IRQ(2, 3)
348#define EXYNOS5_IRQ_SYSMMU_GSC2_0 COMBINER_IRQ(2, 4)
349#define EXYNOS5_IRQ_SYSMMU_GSC2_1 COMBINER_IRQ(2, 5)
350#define EXYNOS5_IRQ_SYSMMU_GSC3_0 COMBINER_IRQ(2, 6)
351#define EXYNOS5_IRQ_SYSMMU_GSC3_1 COMBINER_IRQ(2, 7)
352
353#define EXYNOS5_IRQ_SYSMMU_LITE2_0 COMBINER_IRQ(3, 0)
354#define EXYNOS5_IRQ_SYSMMU_LITE2_1 COMBINER_IRQ(3, 1)
355#define EXYNOS5_IRQ_SYSMMU_FIMD1_0 COMBINER_IRQ(3, 2)
356#define EXYNOS5_IRQ_SYSMMU_FIMD1_1 COMBINER_IRQ(3, 3)
357#define EXYNOS5_IRQ_SYSMMU_LITE0_0 COMBINER_IRQ(3, 4)
358#define EXYNOS5_IRQ_SYSMMU_LITE0_1 COMBINER_IRQ(3, 5)
359#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_0 COMBINER_IRQ(3, 6)
360#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_1 COMBINER_IRQ(3, 7)
361
362#define EXYNOS5_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(4, 0)
363#define EXYNOS5_IRQ_SYSMMU_ROTATOR_1 COMBINER_IRQ(4, 1)
364#define EXYNOS5_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 2)
365#define EXYNOS5_IRQ_SYSMMU_JPEG_1 COMBINER_IRQ(4, 3)
366
367#define EXYNOS5_IRQ_SYSMMU_FD_0 COMBINER_IRQ(5, 0)
368#define EXYNOS5_IRQ_SYSMMU_FD_1 COMBINER_IRQ(5, 1)
369#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_0 COMBINER_IRQ(5, 2)
370#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_1 COMBINER_IRQ(5, 3)
371#define EXYNOS5_IRQ_SYSMMU_MCUISP_0 COMBINER_IRQ(5, 4)
372#define EXYNOS5_IRQ_SYSMMU_MCUISP_1 COMBINER_IRQ(5, 5)
373#define EXYNOS5_IRQ_SYSMMU_3DNR_0 COMBINER_IRQ(5, 6)
374#define EXYNOS5_IRQ_SYSMMU_3DNR_1 COMBINER_IRQ(5, 7)
375
376#define EXYNOS5_IRQ_SYSMMU_ARM_0 COMBINER_IRQ(6, 0)
377#define EXYNOS5_IRQ_SYSMMU_ARM_1 COMBINER_IRQ(6, 1)
378#define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(6, 2)
379#define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(6, 3)
380#define EXYNOS5_IRQ_SYSMMU_RTIC_0 COMBINER_IRQ(6, 4)
381#define EXYNOS5_IRQ_SYSMMU_RTIC_1 COMBINER_IRQ(6, 5)
382#define EXYNOS5_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(6, 6)
383#define EXYNOS5_IRQ_SYSMMU_SSS_1 COMBINER_IRQ(6, 7)
384
385#define EXYNOS5_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(7, 0)
386#define EXYNOS5_IRQ_SYSMMU_MDMA0_1 COMBINER_IRQ(7, 1)
387#define EXYNOS5_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(7, 2)
388#define EXYNOS5_IRQ_SYSMMU_MDMA1_1 COMBINER_IRQ(7, 3)
389#define EXYNOS5_IRQ_SYSMMU_TV_0 COMBINER_IRQ(7, 4)
390#define EXYNOS5_IRQ_SYSMMU_TV_1 COMBINER_IRQ(7, 5)
391
392#define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(8, 5)
393#define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(8, 6)
394
395#define EXYNOS5_IRQ_SYSMMU_DIS1_0 COMBINER_IRQ(9, 4)
396#define EXYNOS5_IRQ_SYSMMU_DIS1_1 COMBINER_IRQ(9, 5)
397
398#define EXYNOS5_IRQ_DP COMBINER_IRQ(10, 3)
399#define EXYNOS5_IRQ_SYSMMU_DIS0_0 COMBINER_IRQ(10, 4)
400#define EXYNOS5_IRQ_SYSMMU_DIS0_1 COMBINER_IRQ(10, 5)
401#define EXYNOS5_IRQ_SYSMMU_ISP_0 COMBINER_IRQ(10, 6)
402#define EXYNOS5_IRQ_SYSMMU_ISP_1 COMBINER_IRQ(10, 7)
403
404#define EXYNOS5_IRQ_SYSMMU_ODC_0 COMBINER_IRQ(11, 0)
405#define EXYNOS5_IRQ_SYSMMU_ODC_1 COMBINER_IRQ(11, 1)
406#define EXYNOS5_IRQ_SYSMMU_DRC_0 COMBINER_IRQ(11, 6)
407#define EXYNOS5_IRQ_SYSMMU_DRC_1 COMBINER_IRQ(11, 7)
408
409#define EXYNOS5_IRQ_MDMA1_ABORT COMBINER_IRQ(13, 1)
410
411#define EXYNOS5_IRQ_MDMA0_ABORT COMBINER_IRQ(15, 3)
412
413#define EXYNOS5_IRQ_FIMD1_FIFO COMBINER_IRQ(18, 4)
414#define EXYNOS5_IRQ_FIMD1_VSYNC COMBINER_IRQ(18, 5)
415#define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6)
416
417#define EXYNOS5_IRQ_ARMIOP_GIC COMBINER_IRQ(19, 0)
418#define EXYNOS5_IRQ_ARMISP_GIC COMBINER_IRQ(19, 1)
419#define EXYNOS5_IRQ_IOP_GIC COMBINER_IRQ(19, 3)
420#define EXYNOS5_IRQ_ISP_GIC COMBINER_IRQ(19, 4)
421
422#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4)
423
424#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
425
426#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0)
427#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1)
428#define EXYNOS5_IRQ_SYSMMU_LITE1_1 COMBINER_IRQ(24, 2)
429#define EXYNOS5_IRQ_SYSMMU_2D_0 COMBINER_IRQ(24, 5)
430#define EXYNOS5_IRQ_SYSMMU_2D_1 COMBINER_IRQ(24, 6)
431
432#define EXYNOS5_IRQ_EINT2 COMBINER_IRQ(25, 0)
433#define EXYNOS5_IRQ_EINT3 COMBINER_IRQ(25, 1)
434
435#define EXYNOS5_IRQ_EINT4 COMBINER_IRQ(26, 0)
436#define EXYNOS5_IRQ_EINT5 COMBINER_IRQ(26, 1)
437
438#define EXYNOS5_IRQ_EINT6 COMBINER_IRQ(27, 0)
439#define EXYNOS5_IRQ_EINT7 COMBINER_IRQ(27, 1)
440
441#define EXYNOS5_IRQ_EINT8 COMBINER_IRQ(28, 0)
442#define EXYNOS5_IRQ_EINT9 COMBINER_IRQ(28, 1)
443
444#define EXYNOS5_IRQ_EINT10 COMBINER_IRQ(29, 0)
445#define EXYNOS5_IRQ_EINT11 COMBINER_IRQ(29, 1)
446
447#define EXYNOS5_IRQ_EINT12 COMBINER_IRQ(30, 0)
448#define EXYNOS5_IRQ_EINT13 COMBINER_IRQ(30, 1)
449
450#define EXYNOS5_IRQ_EINT14 COMBINER_IRQ(31, 0)
451#define EXYNOS5_IRQ_EINT15 COMBINER_IRQ(31, 1)
452
453#define EXYNOS5_MAX_COMBINER_NR 32
454
455#define EXYNOS5_IRQ_GPIO1_NR_GROUPS 14
456#define EXYNOS5_IRQ_GPIO2_NR_GROUPS 9
457#define EXYNOS5_IRQ_GPIO3_NR_GROUPS 5
458#define EXYNOS5_IRQ_GPIO4_NR_GROUPS 1
459
460#define MAX_COMBINER_NR (EXYNOS4_MAX_COMBINER_NR > EXYNOS5_MAX_COMBINER_NR ? \
461 EXYNOS4_MAX_COMBINER_NR : EXYNOS5_MAX_COMBINER_NR)
462
463#define S5P_EINT_BASE1 COMBINER_IRQ(MAX_COMBINER_NR, 0)
464#define S5P_EINT_BASE2 (S5P_EINT_BASE1 + 16)
465#define S5P_GPIOINT_BASE (S5P_EINT_BASE1 + 32)
466#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
467#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64)
468
469/* Set the default NR_IRQS */
470#define EXYNOS_NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
471
472#ifndef CONFIG_SPARSE_IRQ
473#define NR_IRQS EXYNOS_NR_IRQS
474#endif
475
476#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 92b29bb583cb..7b046b59d9ec 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -30,31 +30,6 @@
30#define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000 30#define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000
31#define EXYNOS5250_PA_SYSRAM_NS 0x0204F000 31#define EXYNOS5250_PA_SYSRAM_NS 0x0204F000
32 32
33#define EXYNOS4_PA_FIMC0 0x11800000
34#define EXYNOS4_PA_FIMC1 0x11810000
35#define EXYNOS4_PA_FIMC2 0x11820000
36#define EXYNOS4_PA_FIMC3 0x11830000
37
38#define EXYNOS4_PA_JPEG 0x11840000
39
40/* x = 0...1 */
41#define EXYNOS4_PA_FIMC_LITE(x) (0x12390000 + ((x) * 0x10000))
42
43#define EXYNOS4_PA_G2D 0x12800000
44
45#define EXYNOS4_PA_I2S0 0x03830000
46#define EXYNOS4_PA_I2S1 0xE3100000
47#define EXYNOS4_PA_I2S2 0xE2A00000
48
49#define EXYNOS4_PA_PCM0 0x03840000
50#define EXYNOS4_PA_PCM1 0x13980000
51#define EXYNOS4_PA_PCM2 0x13990000
52
53#define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
54
55#define EXYNOS4_PA_ONENAND 0x0C000000
56#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
57
58#define EXYNOS_PA_CHIPID 0x10000000 33#define EXYNOS_PA_CHIPID 0x10000000
59 34
60#define EXYNOS4_PA_SYSCON 0x10010000 35#define EXYNOS4_PA_SYSCON 0x10010000
@@ -71,10 +46,6 @@
71#define EXYNOS4_PA_WATCHDOG 0x10060000 46#define EXYNOS4_PA_WATCHDOG 0x10060000
72#define EXYNOS5_PA_WATCHDOG 0x101D0000 47#define EXYNOS5_PA_WATCHDOG 0x101D0000
73 48
74#define EXYNOS4_PA_RTC 0x10070000
75
76#define EXYNOS4_PA_KEYPAD 0x100A0000
77
78#define EXYNOS4_PA_DMC0 0x10400000 49#define EXYNOS4_PA_DMC0 0x10400000
79#define EXYNOS4_PA_DMC1 0x10410000 50#define EXYNOS4_PA_DMC1 0x10410000
80 51
@@ -87,207 +58,22 @@
87#define EXYNOS5_PA_GIC_DIST 0x10481000 58#define EXYNOS5_PA_GIC_DIST 0x10481000
88 59
89#define EXYNOS4_PA_COREPERI 0x10500000 60#define EXYNOS4_PA_COREPERI 0x10500000
90#define EXYNOS4_PA_TWD 0x10500600
91#define EXYNOS4_PA_L2CC 0x10502000 61#define EXYNOS4_PA_L2CC 0x10502000
92 62
93#define EXYNOS4_PA_TMU 0x100C0000
94
95#define EXYNOS4_PA_MDMA0 0x10810000
96#define EXYNOS4_PA_MDMA1 0x12850000
97#define EXYNOS4_PA_S_MDMA1 0x12840000
98#define EXYNOS4_PA_PDMA0 0x12680000
99#define EXYNOS4_PA_PDMA1 0x12690000
100#define EXYNOS5_PA_MDMA0 0x10800000
101#define EXYNOS5_PA_MDMA1 0x11C10000
102#define EXYNOS5_PA_PDMA0 0x121A0000
103#define EXYNOS5_PA_PDMA1 0x121B0000
104
105#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000
106#define EXYNOS4_PA_SYSMMU_2D_ACP 0x10A40000
107#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000
108#define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000
109#define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000
110#define EXYNOS4_PA_SYSMMU_FIMC2 0x11A40000
111#define EXYNOS4_PA_SYSMMU_FIMC3 0x11A50000
112#define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000
113#define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000
114#define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000
115#define EXYNOS4_PA_SYSMMU_FIMC_ISP 0x12260000
116#define EXYNOS4_PA_SYSMMU_FIMC_DRC 0x12270000
117#define EXYNOS4_PA_SYSMMU_FIMC_FD 0x122A0000
118#define EXYNOS4_PA_SYSMMU_ISPCPU 0x122B0000
119#define EXYNOS4_PA_SYSMMU_FIMC_LITE0 0x123B0000
120#define EXYNOS4_PA_SYSMMU_FIMC_LITE1 0x123C0000
121#define EXYNOS4_PA_SYSMMU_PCIe 0x12620000
122#define EXYNOS4_PA_SYSMMU_G2D 0x12A20000
123#define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000
124#define EXYNOS4_PA_SYSMMU_MDMA2 0x12A40000
125#define EXYNOS4_PA_SYSMMU_TV 0x12E20000
126#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
127#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
128
129#define EXYNOS5_PA_GSC0 0x13E00000
130#define EXYNOS5_PA_GSC1 0x13E10000
131#define EXYNOS5_PA_GSC2 0x13E20000
132#define EXYNOS5_PA_GSC3 0x13E30000
133
134#define EXYNOS5_PA_SYSMMU_MDMA1 0x10A40000
135#define EXYNOS5_PA_SYSMMU_SSS 0x10A50000
136#define EXYNOS5_PA_SYSMMU_2D 0x10A60000
137#define EXYNOS5_PA_SYSMMU_MFC_L 0x11200000
138#define EXYNOS5_PA_SYSMMU_MFC_R 0x11210000
139#define EXYNOS5_PA_SYSMMU_ROTATOR 0x11D40000
140#define EXYNOS5_PA_SYSMMU_MDMA2 0x11D50000
141#define EXYNOS5_PA_SYSMMU_JPEG 0x11F20000
142#define EXYNOS5_PA_SYSMMU_IOP 0x12360000
143#define EXYNOS5_PA_SYSMMU_RTIC 0x12370000
144#define EXYNOS5_PA_SYSMMU_ISP 0x13260000
145#define EXYNOS5_PA_SYSMMU_DRC 0x12370000
146#define EXYNOS5_PA_SYSMMU_SCALERC 0x13280000
147#define EXYNOS5_PA_SYSMMU_SCALERP 0x13290000
148#define EXYNOS5_PA_SYSMMU_FD 0x132A0000
149#define EXYNOS5_PA_SYSMMU_ISPCPU 0x132B0000
150#define EXYNOS5_PA_SYSMMU_ODC 0x132C0000
151#define EXYNOS5_PA_SYSMMU_DIS0 0x132D0000
152#define EXYNOS5_PA_SYSMMU_DIS1 0x132E0000
153#define EXYNOS5_PA_SYSMMU_3DNR 0x132F0000
154#define EXYNOS5_PA_SYSMMU_LITE0 0x13C40000
155#define EXYNOS5_PA_SYSMMU_LITE1 0x13C50000
156#define EXYNOS5_PA_SYSMMU_GSC0 0x13E80000
157#define EXYNOS5_PA_SYSMMU_GSC1 0x13E90000
158#define EXYNOS5_PA_SYSMMU_GSC2 0x13EA0000
159#define EXYNOS5_PA_SYSMMU_GSC3 0x13EB0000
160#define EXYNOS5_PA_SYSMMU_FIMD1 0x14640000
161#define EXYNOS5_PA_SYSMMU_TV 0x14650000
162
163#define EXYNOS4_PA_SPI0 0x13920000
164#define EXYNOS4_PA_SPI1 0x13930000
165#define EXYNOS4_PA_SPI2 0x13940000
166#define EXYNOS5_PA_SPI0 0x12D20000
167#define EXYNOS5_PA_SPI1 0x12D30000
168#define EXYNOS5_PA_SPI2 0x12D40000
169
170#define EXYNOS4_PA_GPIO1 0x11400000
171#define EXYNOS4_PA_GPIO2 0x11000000
172#define EXYNOS4_PA_GPIO3 0x03860000
173#define EXYNOS5_PA_GPIO1 0x11400000
174#define EXYNOS5_PA_GPIO2 0x13400000
175#define EXYNOS5_PA_GPIO3 0x10D10000
176#define EXYNOS5_PA_GPIO4 0x03860000
177
178#define EXYNOS4_PA_MIPI_CSIS0 0x11880000
179#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
180
181#define EXYNOS4_PA_FIMD0 0x11C00000
182
183#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
184#define EXYNOS4_PA_DWMCI 0x12550000
185#define EXYNOS5_PA_DWMCI0 0x12200000
186#define EXYNOS5_PA_DWMCI1 0x12210000
187#define EXYNOS5_PA_DWMCI2 0x12220000
188#define EXYNOS5_PA_DWMCI3 0x12230000
189
190#define EXYNOS4_PA_HSOTG 0x12480000
191#define EXYNOS4_PA_USB_HSPHY 0x125B0000
192
193#define EXYNOS4_PA_SATA 0x12560000
194#define EXYNOS4_PA_SATAPHY 0x125D0000
195#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000
196
197#define EXYNOS4_PA_SROMC 0x12570000 63#define EXYNOS4_PA_SROMC 0x12570000
198#define EXYNOS5_PA_SROMC 0x12250000 64#define EXYNOS5_PA_SROMC 0x12250000
199 65
200#define EXYNOS4_PA_EHCI 0x12580000
201#define EXYNOS4_PA_OHCI 0x12590000
202#define EXYNOS4_PA_HSPHY 0x125B0000 66#define EXYNOS4_PA_HSPHY 0x125B0000
203#define EXYNOS4_PA_MFC 0x13400000
204 67
205#define EXYNOS4_PA_UART 0x13800000 68#define EXYNOS4_PA_UART 0x13800000
206#define EXYNOS5_PA_UART 0x12C00000 69#define EXYNOS5_PA_UART 0x12C00000
207 70
208#define EXYNOS4_PA_VP 0x12C00000
209#define EXYNOS4_PA_MIXER 0x12C10000
210#define EXYNOS4_PA_SDO 0x12C20000
211#define EXYNOS4_PA_HDMI 0x12D00000
212#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000
213
214#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
215#define EXYNOS5_PA_IIC(x) (0x12C60000 + ((x) * 0x10000))
216
217#define EXYNOS4_PA_ADC 0x13910000
218#define EXYNOS4_PA_ADC1 0x13911000
219
220#define EXYNOS4_PA_AC97 0x139A0000
221
222#define EXYNOS4_PA_SPDIF 0x139B0000
223
224#define EXYNOS4_PA_TIMER 0x139D0000 71#define EXYNOS4_PA_TIMER 0x139D0000
225#define EXYNOS5_PA_TIMER 0x12DD0000 72#define EXYNOS5_PA_TIMER 0x12DD0000
226 73
227#define EXYNOS4_PA_SDRAM 0x40000000
228#define EXYNOS5_PA_SDRAM 0x40000000
229
230/* Compatibiltiy Defines */
231
232#define S3C_PA_HSMMC0 EXYNOS4_PA_HSMMC(0)
233#define S3C_PA_HSMMC1 EXYNOS4_PA_HSMMC(1)
234#define S3C_PA_HSMMC2 EXYNOS4_PA_HSMMC(2)
235#define S3C_PA_HSMMC3 EXYNOS4_PA_HSMMC(3)
236#define S3C_PA_IIC EXYNOS4_PA_IIC(0)
237#define S3C_PA_IIC1 EXYNOS4_PA_IIC(1)
238#define S3C_PA_IIC2 EXYNOS4_PA_IIC(2)
239#define S3C_PA_IIC3 EXYNOS4_PA_IIC(3)
240#define S3C_PA_IIC4 EXYNOS4_PA_IIC(4)
241#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5)
242#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6)
243#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
244#define S3C_PA_RTC EXYNOS4_PA_RTC
245#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
246#define S3C_PA_SPI0 EXYNOS4_PA_SPI0
247#define S3C_PA_SPI1 EXYNOS4_PA_SPI1
248#define S3C_PA_SPI2 EXYNOS4_PA_SPI2
249#define S3C_PA_USB_HSOTG EXYNOS4_PA_HSOTG
250
251#define S5P_PA_EHCI EXYNOS4_PA_EHCI
252#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0
253#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1
254#define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2
255#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3
256#define S5P_PA_JPEG EXYNOS4_PA_JPEG
257#define S5P_PA_G2D EXYNOS4_PA_G2D
258#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0
259#define S5P_PA_HDMI EXYNOS4_PA_HDMI
260#define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY
261#define S5P_PA_MFC EXYNOS4_PA_MFC
262#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0
263#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1
264#define S5P_PA_MIXER EXYNOS4_PA_MIXER
265#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND
266#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
267#define S5P_PA_SDO EXYNOS4_PA_SDO
268#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
269#define S5P_PA_VP EXYNOS4_PA_VP
270
271#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
272#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1
273#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD
274
275/* Compatibility UART */ 74/* Compatibility UART */
276 75
277#define EXYNOS4_PA_UART0 0x13800000
278#define EXYNOS4_PA_UART1 0x13810000
279#define EXYNOS4_PA_UART2 0x13820000
280#define EXYNOS4_PA_UART3 0x13830000
281#define EXYNOS4_SZ_UART SZ_256
282
283#define EXYNOS5_PA_UART0 0x12C00000
284#define EXYNOS5_PA_UART1 0x12C10000
285#define EXYNOS5_PA_UART2 0x12C20000
286#define EXYNOS5_PA_UART3 0x12C30000
287
288#define EXYNOS5440_PA_UART0 0x000B0000 76#define EXYNOS5440_PA_UART0 0x000B0000
289#define EXYNOS5440_PA_UART1 0x000C0000
290#define EXYNOS5440_SZ_UART SZ_256
291 77
292#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) 78#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
293 79
diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h
index 296090e7f423..2b00833b6641 100644
--- a/arch/arm/mach-exynos/include/mach/pm-core.h
+++ b/arch/arm/mach-exynos/include/mach/pm-core.h
@@ -34,12 +34,7 @@ static inline void s3c_pm_debug_init_uart(void)
34 34
35static inline void s3c_pm_arch_prepare_irqs(void) 35static inline void s3c_pm_arch_prepare_irqs(void)
36{ 36{
37 u32 eintmask = s3c_irqwake_eintmask; 37 __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
38
39 if (of_have_populated_dt())
40 eintmask = exynos_get_eint_wake_mask();
41
42 __raw_writel(eintmask, S5P_EINT_WAKEUP_MASK);
43 __raw_writel(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); 38 __raw_writel(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
44} 39}
45 40
@@ -69,4 +64,9 @@ static inline void samsung_pm_saved_gpios(void)
69 /* nothing here yet */ 64 /* nothing here yet */
70} 65}
71 66
67/* Compatibility definitions to make plat-samsung/pm.c compile */
68#define IRQ_EINT_BIT(x) 1
69#define s3c_irqwake_intallow 0
70#define s3c_irqwake_eintallow 0
71
72#endif /* __ASM_ARCH_PM_CORE_H */ 72#endif /* __ASM_ARCH_PM_CORE_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-gpio.h b/arch/arm/mach-exynos/include/mach/regs-gpio.h
deleted file mode 100644
index e4b5b60dcb85..000000000000
--- a/arch/arm/mach-exynos/include/mach/regs-gpio.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/* linux/arch/arm/mach-exynos4/include/mach/regs-gpio.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - GPIO (including EINT) register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_GPIO_H
14#define __ASM_ARCH_REGS_GPIO_H __FILE__
15
16#include <mach/map.h>
17#include <mach/irqs.h>
18
19#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
20#define EINT_CON(b, x) (b + 0xE00 + (EINT_REG_NR(x) * 4))
21#define EINT_FLTCON(b, x) (b + 0xE80 + (EINT_REG_NR(x) * 4))
22#define EINT_MASK(b, x) (b + 0xF00 + (EINT_REG_NR(x) * 4))
23#define EINT_PEND(b, x) (b + 0xF40 + (EINT_REG_NR(x) * 4))
24
25#define EINT_OFFSET_BIT(x) (1 << (EINT_OFFSET(x) & 0x7))
26
27/* compatibility for plat-s5p/irq-pm.c */
28#define EXYNOS4_EINT40CON (S5P_VA_GPIO2 + 0xE00)
29#define S5P_EINT_CON(x) (EXYNOS4_EINT40CON + ((x) * 0x4))
30
31#define EXYNOS4_EINT40FLTCON0 (S5P_VA_GPIO2 + 0xE80)
32#define S5P_EINT_FLTCON(x) (EXYNOS4_EINT40FLTCON0 + ((x) * 0x4))
33
34#define EXYNOS4_EINT40MASK (S5P_VA_GPIO2 + 0xF00)
35#define S5P_EINT_MASK(x) (EXYNOS4_EINT40MASK + ((x) * 0x4))
36
37#define EXYNOS4_EINT40PEND (S5P_VA_GPIO2 + 0xF40)
38#define S5P_EINT_PEND(x) (EXYNOS4_EINT40PEND + ((x) * 0x4))
39
40#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
deleted file mode 100644
index 07277735252e..000000000000
--- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
+++ /dev/null
@@ -1,74 +0,0 @@
1/*
2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
3 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#ifndef __PLAT_S5P_REGS_USB_PHY_H
12#define __PLAT_S5P_REGS_USB_PHY_H
13
14#define EXYNOS4_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY)
15
16#define EXYNOS4_PHYPWR EXYNOS4_HSOTG_PHYREG(0x00)
17#define PHY1_HSIC_NORMAL_MASK (0xf << 9)
18#define PHY1_HSIC1_SLEEP (1 << 12)
19#define PHY1_HSIC1_FORCE_SUSPEND (1 << 11)
20#define PHY1_HSIC0_SLEEP (1 << 10)
21#define PHY1_HSIC0_FORCE_SUSPEND (1 << 9)
22
23#define PHY1_STD_NORMAL_MASK (0x7 << 6)
24#define PHY1_STD_SLEEP (1 << 8)
25#define PHY1_STD_ANALOG_POWERDOWN (1 << 7)
26#define PHY1_STD_FORCE_SUSPEND (1 << 6)
27
28#define PHY0_NORMAL_MASK (0x39 << 0)
29#define PHY0_SLEEP (1 << 5)
30#define PHY0_OTG_DISABLE (1 << 4)
31#define PHY0_ANALOG_POWERDOWN (1 << 3)
32#define PHY0_FORCE_SUSPEND (1 << 0)
33
34#define EXYNOS4_PHYCLK EXYNOS4_HSOTG_PHYREG(0x04)
35#define PHY1_COMMON_ON_N (1 << 7)
36#define PHY0_COMMON_ON_N (1 << 4)
37#define PHY0_ID_PULLUP (1 << 2)
38
39#define EXYNOS4_CLKSEL_SHIFT (0)
40
41#define EXYNOS4210_CLKSEL_MASK (0x3 << 0)
42#define EXYNOS4210_CLKSEL_48M (0x0 << 0)
43#define EXYNOS4210_CLKSEL_12M (0x2 << 0)
44#define EXYNOS4210_CLKSEL_24M (0x3 << 0)
45
46#define EXYNOS4X12_CLKSEL_MASK (0x7 << 0)
47#define EXYNOS4X12_CLKSEL_9600K (0x0 << 0)
48#define EXYNOS4X12_CLKSEL_10M (0x1 << 0)
49#define EXYNOS4X12_CLKSEL_12M (0x2 << 0)
50#define EXYNOS4X12_CLKSEL_19200K (0x3 << 0)
51#define EXYNOS4X12_CLKSEL_20M (0x4 << 0)
52#define EXYNOS4X12_CLKSEL_24M (0x5 << 0)
53
54#define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08)
55#define HOST_LINK_PORT_SWRST_MASK (0xf << 6)
56#define HOST_LINK_PORT2_SWRST (1 << 9)
57#define HOST_LINK_PORT1_SWRST (1 << 8)
58#define HOST_LINK_PORT0_SWRST (1 << 7)
59#define HOST_LINK_ALL_SWRST (1 << 6)
60
61#define PHY1_SWRST_MASK (0x7 << 3)
62#define PHY1_HSIC_SWRST (1 << 5)
63#define PHY1_STD_SWRST (1 << 4)
64#define PHY1_ALL_SWRST (1 << 3)
65
66#define PHY0_SWRST_MASK (0x7 << 0)
67#define PHY0_PHYLINK_SWRST (1 << 2)
68#define PHY0_HLINK_SWRST (1 << 1)
69#define PHY0_SWRST (1 << 0)
70
71#define EXYNOS4_PHY1CON EXYNOS4_HSOTG_PHYREG(0x34)
72#define FPENABLEN (1 << 0)
73
74#endif /* __PLAT_S5P_REGS_USB_PHY_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-19 01:56:20 -0500