ARM: EXYNOS: Change System MMU platform device definitions

Handling System MMUs with an identifier is not flexible to manage
System MMU platform devices because of the following reasons:
1. A device driver which needs to handle System MMU must know the ID.
2. A System MMU may not present in some implementations of Exynos family.
3. Handling System MMU with IOMMU API does not require an ID.

This patch is the result of removing ID of System MMUs.
Instead, a device driver that needs to handle its System MMU must
use IOMMU API while its descriptor of platform device is given.

This patch also includes the following enhancements:
- A System MMU device becomes a child if its power domain device.
- clkdev

Signed-off-by: KyongHo Cho <pullip.cho@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

5 files changed, 104 insertions, 80 deletions

diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 9bee8535d9e0..f140e1a2d335 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -154,6 +154,13 @@
 #define EXYNOS4_IRQ_SYSMMU_MFC_M1_0     COMBINER_IRQ(5, 6)
 #define EXYNOS4_IRQ_SYSMMU_PCIE_0       COMBINER_IRQ(5, 7)
 
+#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE0_0 COMBINER_IRQ(16, 0)
+#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE1_0 COMBINER_IRQ(16, 1)
+#define EXYNOS4_IRQ_SYSMMU_FIMC_ISP_0   COMBINER_IRQ(16, 2)
+#define EXYNOS4_IRQ_SYSMMU_FIMC_DRC_0   COMBINER_IRQ(16, 3)
+#define EXYNOS4_IRQ_SYSMMU_FIMC_FD_0    COMBINER_IRQ(16, 4)
+#define EXYNOS4_IRQ_SYSMMU_FIMC_CX_0    COMBINER_IRQ(16, 5)
+
 #define EXYNOS4_IRQ_FIMD0_FIFO          COMBINER_IRQ(11, 0)
 #define EXYNOS4_IRQ_FIMD0_VSYNC         COMBINER_IRQ(11, 1)
 #define EXYNOS4_IRQ_FIMD0_SYSTEM        COMBINER_IRQ(11, 2)
@@ -218,24 +225,6 @@
 #define IRQ_KEYPAD                      EXYNOS4_IRQ_KEYPAD
 #define IRQ_PMU                         EXYNOS4_IRQ_PMU
 
-#define IRQ_SYSMMU_MDMA0_0              EXYNOS4_IRQ_SYSMMU_MDMA0_0
-#define IRQ_SYSMMU_SSS_0                EXYNOS4_IRQ_SYSMMU_SSS_0
-#define IRQ_SYSMMU_FIMC0_0              EXYNOS4_IRQ_SYSMMU_FIMC0_0
-#define IRQ_SYSMMU_FIMC1_0              EXYNOS4_IRQ_SYSMMU_FIMC1_0
-#define IRQ_SYSMMU_FIMC2_0              EXYNOS4_IRQ_SYSMMU_FIMC2_0
-#define IRQ_SYSMMU_FIMC3_0              EXYNOS4_IRQ_SYSMMU_FIMC3_0
-#define IRQ_SYSMMU_JPEG_0               EXYNOS4_IRQ_SYSMMU_JPEG_0
-#define IRQ_SYSMMU_2D_0                 EXYNOS4_IRQ_SYSMMU_2D_0
-
-#define IRQ_SYSMMU_ROTATOR_0            EXYNOS4_IRQ_SYSMMU_ROTATOR_0
-#define IRQ_SYSMMU_MDMA1_0              EXYNOS4_IRQ_SYSMMU_MDMA1_0
-#define IRQ_SYSMMU_LCD0_M0_0            EXYNOS4_IRQ_SYSMMU_LCD0_M0_0
-#define IRQ_SYSMMU_LCD1_M1_0            EXYNOS4_IRQ_SYSMMU_LCD1_M1_0
-#define IRQ_SYSMMU_TV_M0_0              EXYNOS4_IRQ_SYSMMU_TV_M0_0
-#define IRQ_SYSMMU_MFC_M0_0             EXYNOS4_IRQ_SYSMMU_MFC_M0_0
-#define IRQ_SYSMMU_MFC_M1_0             EXYNOS4_IRQ_SYSMMU_MFC_M1_0
-#define IRQ_SYSMMU_PCIE_0               EXYNOS4_IRQ_SYSMMU_PCIE_0
-
 #define IRQ_FIMD0_FIFO                  EXYNOS4_IRQ_FIMD0_FIFO
 #define IRQ_FIMD0_VSYNC                 EXYNOS4_IRQ_FIMD0_VSYNC
 #define IRQ_FIMD0_SYSTEM                EXYNOS4_IRQ_FIMD0_SYSTEM
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 024d38ff1718..69f2ea6fb0d2 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -91,6 +91,7 @@
 #define EXYNOS4_PA_PDMA1                0x12690000
 
 #define EXYNOS4_PA_SYSMMU_MDMA          0x10A40000
+#define EXYNOS4_PA_SYSMMU_2D_ACP        0x10A40000
 #define EXYNOS4_PA_SYSMMU_SSS           0x10A50000
 #define EXYNOS4_PA_SYSMMU_FIMC0         0x11A20000
 #define EXYNOS4_PA_SYSMMU_FIMC1         0x11A30000
@@ -99,6 +100,12 @@
 #define EXYNOS4_PA_SYSMMU_JPEG          0x11A60000
 #define EXYNOS4_PA_SYSMMU_FIMD0         0x11E20000
 #define EXYNOS4_PA_SYSMMU_FIMD1         0x12220000
+#define EXYNOS4_PA_SYSMMU_FIMC_ISP      0x12260000
+#define EXYNOS4_PA_SYSMMU_FIMC_DRC      0x12270000
+#define EXYNOS4_PA_SYSMMU_FIMC_FD       0x122A0000
+#define EXYNOS4_PA_SYSMMU_ISPCPU        0x122B0000
+#define EXYNOS4_PA_SYSMMU_FIMC_LITE0    0x123B0000
+#define EXYNOS4_PA_SYSMMU_FIMC_LITE1    0x123C0000
 #define EXYNOS4_PA_SYSMMU_PCIe          0x12620000
 #define EXYNOS4_PA_SYSMMU_G2D           0x12A20000
 #define EXYNOS4_PA_SYSMMU_ROTATOR       0x12A30000
@@ -106,6 +113,37 @@
 #define EXYNOS4_PA_SYSMMU_TV            0x12E20000
 #define EXYNOS4_PA_SYSMMU_MFC_L         0x13620000
 #define EXYNOS4_PA_SYSMMU_MFC_R         0x13630000
+
+#define EXYNOS5_PA_SYSMMU_MDMA1         0x10A40000
+#define EXYNOS5_PA_SYSMMU_SSS           0x10A50000
+#define EXYNOS5_PA_SYSMMU_2D            0x10A60000
+#define EXYNOS5_PA_SYSMMU_MFC_L         0x11200000
+#define EXYNOS5_PA_SYSMMU_MFC_R         0x11210000
+#define EXYNOS5_PA_SYSMMU_ROTATOR       0x11D40000
+#define EXYNOS5_PA_SYSMMU_MDMA2         0x11D50000
+#define EXYNOS5_PA_SYSMMU_JPEG          0x11F20000
+#define EXYNOS5_PA_SYSMMU_IOP           0x12360000
+#define EXYNOS5_PA_SYSMMU_RTIC          0x12370000
+#define EXYNOS5_PA_SYSMMU_GPS           0x12630000
+#define EXYNOS5_PA_SYSMMU_ISP           0x13260000
+#define EXYNOS5_PA_SYSMMU_DRC           0x12370000
+#define EXYNOS5_PA_SYSMMU_SCALERC       0x13280000
+#define EXYNOS5_PA_SYSMMU_SCALERP       0x13290000
+#define EXYNOS5_PA_SYSMMU_FD            0x132A0000
+#define EXYNOS5_PA_SYSMMU_ISPCPU        0x132B0000
+#define EXYNOS5_PA_SYSMMU_ODC           0x132C0000
+#define EXYNOS5_PA_SYSMMU_DIS0          0x132D0000
+#define EXYNOS5_PA_SYSMMU_DIS1          0x132E0000
+#define EXYNOS5_PA_SYSMMU_3DNR          0x132F0000
+#define EXYNOS5_PA_SYSMMU_LITE0         0x13C40000
+#define EXYNOS5_PA_SYSMMU_LITE1         0x13C50000
+#define EXYNOS5_PA_SYSMMU_GSC0          0x13E80000
+#define EXYNOS5_PA_SYSMMU_GSC1          0x13E90000
+#define EXYNOS5_PA_SYSMMU_GSC2          0x13EA0000
+#define EXYNOS5_PA_SYSMMU_GSC3          0x13EB0000
+#define EXYNOS5_PA_SYSMMU_FIMD1         0x14640000
+#define EXYNOS5_PA_SYSMMU_TV            0x14650000
+
 #define EXYNOS4_PA_SPI0                 0x13920000
 #define EXYNOS4_PA_SPI1                 0x13930000
 #define EXYNOS4_PA_SPI2                 0x13940000
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index e141c1fd68d8..7395236ffc0e 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -135,6 +135,9 @@
 #define EXYNOS4_CLKGATE_SCLKCPU                 EXYNOS_CLKREG(0x14800)
 #define EXYNOS4_CLKGATE_IP_CPU                  EXYNOS_CLKREG(0x14900)
 
+#define EXYNOS4_CLKGATE_IP_ISP0                 EXYNOS_CLKREG(0x18800)
+#define EXYNOS4_CLKGATE_IP_ISP1                 EXYNOS_CLKREG(0x18804)
+
 #define EXYNOS4_APLL_LOCKTIME                   (0x1C20)        /* 300us */
 
 #define EXYNOS4_APLLCON0_ENABLE_SHIFT           (31)
@@ -297,6 +300,8 @@
 #define EXYNOS5_CLKDIV_PERIC0                   EXYNOS_CLKREG(0x10558)
 
 #define EXYNOS5_CLKGATE_IP_ACP                  EXYNOS_CLKREG(0x08800)
+#define EXYNOS5_CLKGATE_IP_ISP0                 EXYNOS_CLKREG(0x0C800)
+#define EXYNOS5_CLKGATE_IP_ISP1                 EXYNOS_CLKREG(0x0C804)
 #define EXYNOS5_CLKGATE_IP_GSCL                 EXYNOS_CLKREG(0x10920)
 #define EXYNOS5_CLKGATE_IP_DISP1                EXYNOS_CLKREG(0x10928)
 #define EXYNOS5_CLKGATE_IP_MFC                  EXYNOS_CLKREG(0x1092C)
diff --git a/arch/arm/mach-exynos/include/mach/regs-sysmmu.h b/arch/arm/mach-exynos/include/mach/regs-sysmmu.h
deleted file mode 100644
index 68ff6ad08a2b..000000000000
--- a/arch/arm/mach-exynos/include/mach/regs-sysmmu.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - System MMU register
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_SYSMMU_H
-#define __ASM_ARCH_REGS_SYSMMU_H __FILE__
-
-#define S5P_MMU_CTRL                    0x000
-#define S5P_MMU_CFG                     0x004
-#define S5P_MMU_STATUS                  0x008
-#define S5P_MMU_FLUSH                   0x00C
-#define S5P_PT_BASE_ADDR                0x014
-#define S5P_INT_STATUS                  0x018
-#define S5P_INT_CLEAR                   0x01C
-#define S5P_PAGE_FAULT_ADDR             0x024
-#define S5P_AW_FAULT_ADDR               0x028
-#define S5P_AR_FAULT_ADDR               0x02C
-#define S5P_DEFAULT_SLAVE_ADDR          0x030
-
-#endif /* __ASM_ARCH_REGS_SYSMMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/sysmmu.h b/arch/arm/mach-exynos/include/mach/sysmmu.h
index 6a5fbb534e82..998daf2add92 100644
--- a/arch/arm/mach-exynos/include/mach/sysmmu.h
+++ b/arch/arm/mach-exynos/include/mach/sysmmu.h
@@ -1,46 +1,66 @@
-/* linux/arch/arm/mach-exynos4/include/mach/sysmmu.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+/*
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
- * Samsung sysmmu driver for EXYNOS4
+ * EXYNOS - System MMU support
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARM_ARCH_SYSMMU_H
-#define __ASM_ARM_ARCH_SYSMMU_H __FILE__
-
-enum exynos4_sysmmu_ips {
-        SYSMMU_MDMA,
-        SYSMMU_SSS,
-        SYSMMU_FIMC0,
-        SYSMMU_FIMC1,
-        SYSMMU_FIMC2,
-        SYSMMU_FIMC3,
-        SYSMMU_JPEG,
-        SYSMMU_FIMD0,
-        SYSMMU_FIMD1,
-        SYSMMU_PCIe,
-        SYSMMU_G2D,
-        SYSMMU_ROTATOR,
-        SYSMMU_MDMA2,
-        SYSMMU_TV,
-        SYSMMU_MFC_L,
-        SYSMMU_MFC_R,
-        EXYNOS4_SYSMMU_TOTAL_IPNUM,
+ */
+
+#ifndef _ARM_MACH_EXYNOS_SYSMMU_H_
+#define _ARM_MACH_EXYNOS_SYSMMU_H_
+
+struct sysmmu_platform_data {
+        char *dbgname;
+        /* comma(,) separated list of clock names for clock gating */
+        char *clockname;
 };
 
-#define S5P_SYSMMU_TOTAL_IPNUM          EXYNOS4_SYSMMU_TOTAL_IPNUM
+#define SYSMMU_DEVNAME_BASE "exynos-sysmmu"
+
+#define SYSMMU_CLOCK_NAME "sysmmu"
+#define SYSMMU_CLOCK_NAME2 "sysmmu_mc"
+
+#ifdef CONFIG_EXYNOS_DEV_SYSMMU
+#include <linux/device.h>
+struct platform_device;
+
+#define SYSMMU_PLATDEV(ipname) exynos_device_sysmmu_##ipname
+
+extern struct platform_device SYSMMU_PLATDEV(mfc_l);
+extern struct platform_device SYSMMU_PLATDEV(mfc_r);
+extern struct platform_device SYSMMU_PLATDEV(tv);
+extern struct platform_device SYSMMU_PLATDEV(jpeg);
+extern struct platform_device SYSMMU_PLATDEV(rot);
+extern struct platform_device SYSMMU_PLATDEV(fimc0);
+extern struct platform_device SYSMMU_PLATDEV(fimc1);
+extern struct platform_device SYSMMU_PLATDEV(fimc2);
+extern struct platform_device SYSMMU_PLATDEV(fimc3);
+extern struct platform_device SYSMMU_PLATDEV(gsc0);
+extern struct platform_device SYSMMU_PLATDEV(gsc1);
+extern struct platform_device SYSMMU_PLATDEV(gsc2);
+extern struct platform_device SYSMMU_PLATDEV(gsc3);
+extern struct platform_device SYSMMU_PLATDEV(isp);
+extern struct platform_device SYSMMU_PLATDEV(fimd0);
+extern struct platform_device SYSMMU_PLATDEV(fimd1);
+extern struct platform_device SYSMMU_PLATDEV(camif0);
+extern struct platform_device SYSMMU_PLATDEV(camif1);
+extern struct platform_device SYSMMU_PLATDEV(2d);
 
-extern const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM];
+#ifdef CONFIG_IOMMU_API
+static inline void platform_set_sysmmu(
+                                struct device *sysmmu, struct device *dev)
+{
+        dev->archdata.iommu = sysmmu;
+}
+#endif
 
-typedef enum exynos4_sysmmu_ips sysmmu_ips;
+#else /* !CONFIG_EXYNOS_DEV_SYSMMU */
+#define platform_set_sysmmu(dev, sysmmu) do { } while (0)
+#endif
 
-void sysmmu_clk_init(struct device *dev, sysmmu_ips ips);
-void sysmmu_clk_enable(sysmmu_ips ips);
-void sysmmu_clk_disable(sysmmu_ips ips);
+#define SYSMMU_CLOCK_DEVNAME(ipname, id) (SYSMMU_DEVNAME_BASE "." #id)
 
-#endif /* __ASM_ARM_ARCH_SYSMMU_H */
+#endif /* _ARM_MACH_EXYNOS_SYSMMU_H_ */