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author | Mauro Carvalho Chehab <mchehab@redhat.com> | 2013-01-24 15:49:18 -0500 |
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committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2013-01-24 15:49:18 -0500 |
commit | a32f7d1ad3744914273c6907204c2ab3b5d496a0 (patch) | |
tree | 1c5ae321ee85665707177547c07810ff7e09e1ab /arch/arm/mach-exynos/common.c | |
parent | 6b9e50c463efc5c361496ae6a895cc966ff8025b (diff) | |
parent | 68d6f84ba0c47e658beff3a4bf0c43acee4b4690 (diff) |
Merge branch 'v4l_for_linus' into staging/for_v3.9
* v4l_for_linus: (464 commits)
[media] uvcvideo: Set error_idx properly for S_EXT_CTRLS failures
[media] uvcvideo: Cleanup leftovers of partial revert
[media] uvcvideo: Return -EACCES when trying to set a read-only control
Linux 3.8-rc3
mm: reinstante dropped pmd_trans_splitting() check
cred: Remove tgcred pointer from struct cred
drm/ttm: fix fence locking in ttm_buffer_object_transfer
ARM: clps711x: Fix bad merge of clockevents setup
ARM: highbank: save and restore L2 cache and GIC on suspend
ARM: highbank: add a power request clear
ARM: highbank: fix secondary boot and hotplug
ARM: highbank: fix typos with hignbank in power request functions
ARM: dts: fix highbank cpu mpidr values
ARM: dts: add device_type prop to cpu nodes on Calxeda platforms
drm/prime: drop reference on imported dma-buf come from gem
xen/netfront: improve truesize tracking
ARM: mx5: Fix MX53 flexcan2 clock
ARM: OMAP2+: am33xx-hwmod: Fix wrongly terminated am33xx_usbss_mpu_irqs array
sctp: fix Kconfig bug in default cookie hmac selection
EDAC: Cleanup device deregistering path
...
Conflicts:
drivers/media/pci/dm1105/dm1105.c
drivers/media/platform/soc_camera/mx2_camera.c
Diffstat (limited to 'arch/arm/mach-exynos/common.c')
-rw-r--r-- | arch/arm/mach-exynos/common.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index d6d0dc651089..1a89824a5f78 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c | |||
@@ -424,11 +424,18 @@ static void __init exynos5_init_clocks(int xtal) | |||
424 | { | 424 | { |
425 | printk(KERN_DEBUG "%s: initializing clocks\n", __func__); | 425 | printk(KERN_DEBUG "%s: initializing clocks\n", __func__); |
426 | 426 | ||
427 | /* EXYNOS5440 can support only common clock framework */ | ||
428 | |||
429 | if (soc_is_exynos5440()) | ||
430 | return; | ||
431 | |||
432 | #ifdef CONFIG_SOC_EXYNOS5250 | ||
427 | s3c24xx_register_baseclocks(xtal); | 433 | s3c24xx_register_baseclocks(xtal); |
428 | s5p_register_clocks(xtal); | 434 | s5p_register_clocks(xtal); |
429 | 435 | ||
430 | exynos5_register_clocks(); | 436 | exynos5_register_clocks(); |
431 | exynos5_setup_clocks(); | 437 | exynos5_setup_clocks(); |
438 | #endif | ||
432 | } | 439 | } |
433 | 440 | ||
434 | #define COMBINER_ENABLE_SET 0x0 | 441 | #define COMBINER_ENABLE_SET 0x0 |