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authorJingoo Han <jg1.han@samsung.com>2012-10-23 09:41:21 -0400
committerKukjin Kim <kgene.kim@samsung.com>2012-10-18 21:05:44 -0400
commit0dca30003bc752b2fc15906e562ef4e4925725fd (patch)
tree46d2ece60793c5a026305ab43826918a1d18d6cb /arch/arm/mach-exynos/clock-exynos5.c
parent619271353dd60415b68779c0a87c17568037f5f8 (diff)
ARM: EXYNOS: Add dp clock support for EXYNOS5
Add dp clock instance for EXYNOS5 dp controller. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos/clock-exynos5.c')
-rw-r--r--arch/arm/mach-exynos/clock-exynos5.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index c44ca1ee1b8d..e5c59fae225c 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -678,6 +678,11 @@ static struct clk exynos5_init_clocks_off[] = {
678 .enable = exynos5_clk_ip_disp1_ctrl, 678 .enable = exynos5_clk_ip_disp1_ctrl,
679 .ctrlbit = (1 << 5), 679 .ctrlbit = (1 << 5),
680 }, { 680 }, {
681 .name = "dp",
682 .devname = "exynos-dp",
683 .enable = exynos5_clk_ip_disp1_ctrl,
684 .ctrlbit = (1 << 4),
685 }, {
681 .name = "jpeg", 686 .name = "jpeg",
682 .enable = exynos5_clk_ip_gen_ctrl, 687 .enable = exynos5_clk_ip_gen_ctrl,
683 .ctrlbit = (1 << 2), 688 .ctrlbit = (1 << 2),