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authorKukjin Kim <kgene.kim@samsung.com>2012-03-09 17:19:10 -0500
committerKukjin Kim <kgene.kim@samsung.com>2012-03-11 01:29:01 -0500
commita855039ee4b814782aebe2448d838944d2d29fcb (patch)
treeb98c88859fda8930ee9470b9383365c899a1c0e5 /arch/arm/mach-exynos/clock-exynos4.c
parentb1d6c5b26d8e242dce12e3a59710e6acad4f9d06 (diff)
ARM: EXYNOS: change the prefix S5P_ to EXYNOS4_ for clock
This patch changes prefix of the clk register from S5P_ to EXYNOS4_ for new EXYNOS SoCs such as EXYNOS5 and adds prefix exynos4_ on clk declarations. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-exynos/clock-exynos4.c')
-rw-r--r--arch/arm/mach-exynos/clock-exynos4.c1028
1 files changed, 514 insertions, 514 deletions
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index 860b73fcd2a1..31b59e65463a 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com 3 * http://www.samsung.com
4 * 4 *
5 * EXYNOS4 - Clock support 5 * EXYNOS4 - Clock support
@@ -31,85 +31,85 @@
31 31
32#ifdef CONFIG_PM_SLEEP 32#ifdef CONFIG_PM_SLEEP
33static struct sleep_save exynos4_clock_save[] = { 33static struct sleep_save exynos4_clock_save[] = {
34 SAVE_ITEM(S5P_CLKDIV_LEFTBUS), 34 SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
35 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS), 35 SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
36 SAVE_ITEM(S5P_CLKDIV_RIGHTBUS), 36 SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
37 SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS), 37 SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
38 SAVE_ITEM(S5P_CLKSRC_TOP0), 38 SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
39 SAVE_ITEM(S5P_CLKSRC_TOP1), 39 SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
40 SAVE_ITEM(S5P_CLKSRC_CAM), 40 SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
41 SAVE_ITEM(S5P_CLKSRC_TV), 41 SAVE_ITEM(EXYNOS4_CLKSRC_TV),
42 SAVE_ITEM(S5P_CLKSRC_MFC), 42 SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
43 SAVE_ITEM(S5P_CLKSRC_G3D), 43 SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
44 SAVE_ITEM(S5P_CLKSRC_LCD0), 44 SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
45 SAVE_ITEM(S5P_CLKSRC_MAUDIO), 45 SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
46 SAVE_ITEM(S5P_CLKSRC_FSYS), 46 SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
47 SAVE_ITEM(S5P_CLKSRC_PERIL0), 47 SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
48 SAVE_ITEM(S5P_CLKSRC_PERIL1), 48 SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
49 SAVE_ITEM(S5P_CLKDIV_CAM), 49 SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
50 SAVE_ITEM(S5P_CLKDIV_TV), 50 SAVE_ITEM(EXYNOS4_CLKDIV_TV),
51 SAVE_ITEM(S5P_CLKDIV_MFC), 51 SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
52 SAVE_ITEM(S5P_CLKDIV_G3D), 52 SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
53 SAVE_ITEM(S5P_CLKDIV_LCD0), 53 SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
54 SAVE_ITEM(S5P_CLKDIV_MAUDIO), 54 SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
55 SAVE_ITEM(S5P_CLKDIV_FSYS0), 55 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
56 SAVE_ITEM(S5P_CLKDIV_FSYS1), 56 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
57 SAVE_ITEM(S5P_CLKDIV_FSYS2), 57 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
58 SAVE_ITEM(S5P_CLKDIV_FSYS3), 58 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
59 SAVE_ITEM(S5P_CLKDIV_PERIL0), 59 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
60 SAVE_ITEM(S5P_CLKDIV_PERIL1), 60 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
61 SAVE_ITEM(S5P_CLKDIV_PERIL2), 61 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
62 SAVE_ITEM(S5P_CLKDIV_PERIL3), 62 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
63 SAVE_ITEM(S5P_CLKDIV_PERIL4), 63 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
64 SAVE_ITEM(S5P_CLKDIV_PERIL5), 64 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
65 SAVE_ITEM(S5P_CLKDIV_TOP), 65 SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
66 SAVE_ITEM(S5P_CLKSRC_MASK_TOP), 66 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
67 SAVE_ITEM(S5P_CLKSRC_MASK_CAM), 67 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
68 SAVE_ITEM(S5P_CLKSRC_MASK_TV), 68 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
69 SAVE_ITEM(S5P_CLKSRC_MASK_LCD0), 69 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
70 SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO), 70 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
71 SAVE_ITEM(S5P_CLKSRC_MASK_FSYS), 71 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
72 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0), 72 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
73 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1), 73 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
74 SAVE_ITEM(S5P_CLKDIV2_RATIO), 74 SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
75 SAVE_ITEM(S5P_CLKGATE_SCLKCAM), 75 SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
76 SAVE_ITEM(S5P_CLKGATE_IP_CAM), 76 SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
77 SAVE_ITEM(S5P_CLKGATE_IP_TV), 77 SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
78 SAVE_ITEM(S5P_CLKGATE_IP_MFC), 78 SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
79 SAVE_ITEM(S5P_CLKGATE_IP_G3D), 79 SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
80 SAVE_ITEM(S5P_CLKGATE_IP_LCD0), 80 SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
81 SAVE_ITEM(S5P_CLKGATE_IP_FSYS), 81 SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
82 SAVE_ITEM(S5P_CLKGATE_IP_GPS), 82 SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
83 SAVE_ITEM(S5P_CLKGATE_IP_PERIL), 83 SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
84 SAVE_ITEM(S5P_CLKGATE_BLOCK), 84 SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
85 SAVE_ITEM(S5P_CLKSRC_MASK_DMC), 85 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
86 SAVE_ITEM(S5P_CLKSRC_DMC), 86 SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
87 SAVE_ITEM(S5P_CLKDIV_DMC0), 87 SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
88 SAVE_ITEM(S5P_CLKDIV_DMC1), 88 SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
89 SAVE_ITEM(S5P_CLKGATE_IP_DMC), 89 SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
90 SAVE_ITEM(S5P_CLKSRC_CPU), 90 SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
91 SAVE_ITEM(S5P_CLKDIV_CPU), 91 SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
92 SAVE_ITEM(S5P_CLKDIV_CPU + 0x4), 92 SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
93 SAVE_ITEM(S5P_CLKGATE_SCLKCPU), 93 SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
94 SAVE_ITEM(S5P_CLKGATE_IP_CPU), 94 SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
95}; 95};
96#endif 96#endif
97 97
98static struct clk clk_sclk_hdmi27m = { 98static struct clk exynos4_clk_sclk_hdmi27m = {
99 .name = "sclk_hdmi27m", 99 .name = "sclk_hdmi27m",
100 .rate = 27000000, 100 .rate = 27000000,
101}; 101};
102 102
103static struct clk clk_sclk_hdmiphy = { 103static struct clk exynos4_clk_sclk_hdmiphy = {
104 .name = "sclk_hdmiphy", 104 .name = "sclk_hdmiphy",
105}; 105};
106 106
107static struct clk clk_sclk_usbphy0 = { 107static struct clk exynos4_clk_sclk_usbphy0 = {
108 .name = "sclk_usbphy0", 108 .name = "sclk_usbphy0",
109 .rate = 27000000, 109 .rate = 27000000,
110}; 110};
111 111
112static struct clk clk_sclk_usbphy1 = { 112static struct clk exynos4_clk_sclk_usbphy1 = {
113 .name = "sclk_usbphy1", 113 .name = "sclk_usbphy1",
114}; 114};
115 115
@@ -120,82 +120,82 @@ static struct clk dummy_apb_pclk = {
120 120
121static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable) 121static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
122{ 122{
123 return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable); 123 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
124} 124}
125 125
126static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable) 126static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
127{ 127{
128 return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable); 128 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
129} 129}
130 130
131static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable) 131static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
132{ 132{
133 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable); 133 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
134} 134}
135 135
136int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable) 136int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
137{ 137{
138 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable); 138 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
139} 139}
140 140
141static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable) 141static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
142{ 142{
143 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable); 143 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
144} 144}
145 145
146static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable) 146static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
147{ 147{
148 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable); 148 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
149} 149}
150 150
151static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable) 151static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
152{ 152{
153 return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable); 153 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
154} 154}
155 155
156static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable) 156static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
157{ 157{
158 return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable); 158 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
159} 159}
160 160
161static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable) 161static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
162{ 162{
163 return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable); 163 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
164} 164}
165 165
166static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable) 166static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
167{ 167{
168 return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable); 168 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
169} 169}
170 170
171static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable) 171static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
172{ 172{
173 return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable); 173 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
174} 174}
175 175
176static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable) 176static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
177{ 177{
178 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable); 178 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
179} 179}
180 180
181int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable) 181int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
182{ 182{
183 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable); 183 return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
184} 184}
185 185
186int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable) 186int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
187{ 187{
188 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable); 188 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
189} 189}
190 190
191static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable) 191static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
192{ 192{
193 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable); 193 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
194} 194}
195 195
196static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable) 196static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
197{ 197{
198 return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable); 198 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
199} 199}
200 200
201static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable) 201static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
@@ -210,31 +210,31 @@ static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
210 210
211/* Core list of CMU_CPU side */ 211/* Core list of CMU_CPU side */
212 212
213static struct clksrc_clk clk_mout_apll = { 213static struct clksrc_clk exynos4_clk_mout_apll = {
214 .clk = { 214 .clk = {
215 .name = "mout_apll", 215 .name = "mout_apll",
216 }, 216 },
217 .sources = &clk_src_apll, 217 .sources = &clk_src_apll,
218 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 }, 218 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
219}; 219};
220 220
221static struct clksrc_clk clk_sclk_apll = { 221static struct clksrc_clk exynos4_clk_sclk_apll = {
222 .clk = { 222 .clk = {
223 .name = "sclk_apll", 223 .name = "sclk_apll",
224 .parent = &clk_mout_apll.clk, 224 .parent = &exynos4_clk_mout_apll.clk,
225 }, 225 },
226 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 }, 226 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
227}; 227};
228 228
229static struct clksrc_clk clk_mout_epll = { 229static struct clksrc_clk exynos4_clk_mout_epll = {
230 .clk = { 230 .clk = {
231 .name = "mout_epll", 231 .name = "mout_epll",
232 }, 232 },
233 .sources = &clk_src_epll, 233 .sources = &clk_src_epll,
234 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 }, 234 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
235}; 235};
236 236
237struct clksrc_clk clk_mout_mpll = { 237struct clksrc_clk exynos4_clk_mout_mpll = {
238 .clk = { 238 .clk = {
239 .name = "mout_mpll", 239 .name = "mout_mpll",
240 }, 240 },
@@ -243,221 +243,221 @@ struct clksrc_clk clk_mout_mpll = {
243 /* reg_src will be added in each SoCs' clock */ 243 /* reg_src will be added in each SoCs' clock */
244}; 244};
245 245
246static struct clk *clkset_moutcore_list[] = { 246static struct clk *exynos4_clkset_moutcore_list[] = {
247 [0] = &clk_mout_apll.clk, 247 [0] = &exynos4_clk_mout_apll.clk,
248 [1] = &clk_mout_mpll.clk, 248 [1] = &exynos4_clk_mout_mpll.clk,
249}; 249};
250 250
251static struct clksrc_sources clkset_moutcore = { 251static struct clksrc_sources exynos4_clkset_moutcore = {
252 .sources = clkset_moutcore_list, 252 .sources = exynos4_clkset_moutcore_list,
253 .nr_sources = ARRAY_SIZE(clkset_moutcore_list), 253 .nr_sources = ARRAY_SIZE(exynos4_clkset_moutcore_list),
254}; 254};
255 255
256static struct clksrc_clk clk_moutcore = { 256static struct clksrc_clk exynos4_clk_moutcore = {
257 .clk = { 257 .clk = {
258 .name = "moutcore", 258 .name = "moutcore",
259 }, 259 },
260 .sources = &clkset_moutcore, 260 .sources = &exynos4_clkset_moutcore,
261 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 }, 261 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
262}; 262};
263 263
264static struct clksrc_clk clk_coreclk = { 264static struct clksrc_clk exynos4_clk_coreclk = {
265 .clk = { 265 .clk = {
266 .name = "core_clk", 266 .name = "core_clk",
267 .parent = &clk_moutcore.clk, 267 .parent = &exynos4_clk_moutcore.clk,
268 }, 268 },
269 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 }, 269 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
270}; 270};
271 271
272static struct clksrc_clk clk_armclk = { 272static struct clksrc_clk exynos4_clk_armclk = {
273 .clk = { 273 .clk = {
274 .name = "armclk", 274 .name = "armclk",
275 .parent = &clk_coreclk.clk, 275 .parent = &exynos4_clk_coreclk.clk,
276 }, 276 },
277}; 277};
278 278
279static struct clksrc_clk clk_aclk_corem0 = { 279static struct clksrc_clk exynos4_clk_aclk_corem0 = {
280 .clk = { 280 .clk = {
281 .name = "aclk_corem0", 281 .name = "aclk_corem0",
282 .parent = &clk_coreclk.clk, 282 .parent = &exynos4_clk_coreclk.clk,
283 }, 283 },
284 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, 284 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
285}; 285};
286 286
287static struct clksrc_clk clk_aclk_cores = { 287static struct clksrc_clk exynos4_clk_aclk_cores = {
288 .clk = { 288 .clk = {
289 .name = "aclk_cores", 289 .name = "aclk_cores",
290 .parent = &clk_coreclk.clk, 290 .parent = &exynos4_clk_coreclk.clk,
291 }, 291 },
292 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, 292 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
293}; 293};
294 294
295static struct clksrc_clk clk_aclk_corem1 = { 295static struct clksrc_clk exynos4_clk_aclk_corem1 = {
296 .clk = { 296 .clk = {
297 .name = "aclk_corem1", 297 .name = "aclk_corem1",
298 .parent = &clk_coreclk.clk, 298 .parent = &exynos4_clk_coreclk.clk,
299 }, 299 },
300 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 }, 300 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
301}; 301};
302 302
303static struct clksrc_clk clk_periphclk = { 303static struct clksrc_clk exynos4_clk_periphclk = {
304 .clk = { 304 .clk = {
305 .name = "periphclk", 305 .name = "periphclk",
306 .parent = &clk_coreclk.clk, 306 .parent = &exynos4_clk_coreclk.clk,
307 }, 307 },
308 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 }, 308 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
309}; 309};
310 310
311/* Core list of CMU_CORE side */ 311/* Core list of CMU_CORE side */
312 312
313static struct clk *clkset_corebus_list[] = { 313static struct clk *exynos4_clkset_corebus_list[] = {
314 [0] = &clk_mout_mpll.clk, 314 [0] = &exynos4_clk_mout_mpll.clk,
315 [1] = &clk_sclk_apll.clk, 315 [1] = &exynos4_clk_sclk_apll.clk,
316}; 316};
317 317
318struct clksrc_sources clkset_mout_corebus = { 318struct clksrc_sources exynos4_clkset_mout_corebus = {
319 .sources = clkset_corebus_list, 319 .sources = exynos4_clkset_corebus_list,
320 .nr_sources = ARRAY_SIZE(clkset_corebus_list), 320 .nr_sources = ARRAY_SIZE(exynos4_clkset_corebus_list),
321}; 321};
322 322
323static struct clksrc_clk clk_mout_corebus = { 323static struct clksrc_clk exynos4_clk_mout_corebus = {
324 .clk = { 324 .clk = {
325 .name = "mout_corebus", 325 .name = "mout_corebus",
326 }, 326 },
327 .sources = &clkset_mout_corebus, 327 .sources = &exynos4_clkset_mout_corebus,
328 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 }, 328 .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
329}; 329};
330 330
331static struct clksrc_clk clk_sclk_dmc = { 331static struct clksrc_clk exynos4_clk_sclk_dmc = {
332 .clk = { 332 .clk = {
333 .name = "sclk_dmc", 333 .name = "sclk_dmc",
334 .parent = &clk_mout_corebus.clk, 334 .parent = &exynos4_clk_mout_corebus.clk,
335 }, 335 },
336 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 }, 336 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
337}; 337};
338 338
339static struct clksrc_clk clk_aclk_cored = { 339static struct clksrc_clk exynos4_clk_aclk_cored = {
340 .clk = { 340 .clk = {
341 .name = "aclk_cored", 341 .name = "aclk_cored",
342 .parent = &clk_sclk_dmc.clk, 342 .parent = &exynos4_clk_sclk_dmc.clk,
343 }, 343 },
344 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 }, 344 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
345}; 345};
346 346
347static struct clksrc_clk clk_aclk_corep = { 347static struct clksrc_clk exynos4_clk_aclk_corep = {
348 .clk = { 348 .clk = {
349 .name = "aclk_corep", 349 .name = "aclk_corep",
350 .parent = &clk_aclk_cored.clk, 350 .parent = &exynos4_clk_aclk_cored.clk,
351 }, 351 },
352 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 }, 352 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
353}; 353};
354 354
355static struct clksrc_clk clk_aclk_acp = { 355static struct clksrc_clk exynos4_clk_aclk_acp = {
356 .clk = { 356 .clk = {
357 .name = "aclk_acp", 357 .name = "aclk_acp",
358 .parent = &clk_mout_corebus.clk, 358 .parent = &exynos4_clk_mout_corebus.clk,
359 }, 359 },
360 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 }, 360 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
361}; 361};
362 362
363static struct clksrc_clk clk_pclk_acp = { 363static struct clksrc_clk exynos4_clk_pclk_acp = {
364 .clk = { 364 .clk = {
365 .name = "pclk_acp", 365 .name = "pclk_acp",
366 .parent = &clk_aclk_acp.clk, 366 .parent = &exynos4_clk_aclk_acp.clk,
367 }, 367 },
368 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 }, 368 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
369}; 369};
370 370
371/* Core list of CMU_TOP side */ 371/* Core list of CMU_TOP side */
372 372
373struct clk *clkset_aclk_top_list[] = { 373struct clk *exynos4_clkset_aclk_top_list[] = {
374 [0] = &clk_mout_mpll.clk, 374 [0] = &exynos4_clk_mout_mpll.clk,
375 [1] = &clk_sclk_apll.clk, 375 [1] = &exynos4_clk_sclk_apll.clk,
376}; 376};
377 377
378static struct clksrc_sources clkset_aclk = { 378static struct clksrc_sources exynos4_clkset_aclk = {
379 .sources = clkset_aclk_top_list, 379 .sources = exynos4_clkset_aclk_top_list,
380 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list), 380 .nr_sources = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
381}; 381};
382 382
383static struct clksrc_clk clk_aclk_200 = { 383static struct clksrc_clk exynos4_clk_aclk_200 = {
384 .clk = { 384 .clk = {
385 .name = "aclk_200", 385 .name = "aclk_200",
386 }, 386 },
387 .sources = &clkset_aclk, 387 .sources = &exynos4_clkset_aclk,
388 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 }, 388 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
389 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 }, 389 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
390}; 390};
391 391
392static struct clksrc_clk clk_aclk_100 = { 392static struct clksrc_clk exynos4_clk_aclk_100 = {
393 .clk = { 393 .clk = {
394 .name = "aclk_100", 394 .name = "aclk_100",
395 }, 395 },
396 .sources = &clkset_aclk, 396 .sources = &exynos4_clkset_aclk,
397 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 }, 397 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
398 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 }, 398 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
399}; 399};
400 400
401static struct clksrc_clk clk_aclk_160 = { 401static struct clksrc_clk exynos4_clk_aclk_160 = {
402 .clk = { 402 .clk = {
403 .name = "aclk_160", 403 .name = "aclk_160",
404 }, 404 },
405 .sources = &clkset_aclk, 405 .sources = &exynos4_clkset_aclk,
406 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 }, 406 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
407 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 }, 407 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
408}; 408};
409 409
410struct clksrc_clk clk_aclk_133 = { 410struct clksrc_clk exynos4_clk_aclk_133 = {
411 .clk = { 411 .clk = {
412 .name = "aclk_133", 412 .name = "aclk_133",
413 }, 413 },
414 .sources = &clkset_aclk, 414 .sources = &exynos4_clkset_aclk,
415 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 }, 415 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
416 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 }, 416 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
417}; 417};
418 418
419static struct clk *clkset_vpllsrc_list[] = { 419static struct clk *exynos4_clkset_vpllsrc_list[] = {
420 [0] = &clk_fin_vpll, 420 [0] = &clk_fin_vpll,
421 [1] = &clk_sclk_hdmi27m, 421 [1] = &exynos4_clk_sclk_hdmi27m,
422}; 422};
423 423
424static struct clksrc_sources clkset_vpllsrc = { 424static struct clksrc_sources exynos4_clkset_vpllsrc = {
425 .sources = clkset_vpllsrc_list, 425 .sources = exynos4_clkset_vpllsrc_list,
426 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list), 426 .nr_sources = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
427}; 427};
428 428
429static struct clksrc_clk clk_vpllsrc = { 429static struct clksrc_clk exynos4_clk_vpllsrc = {
430 .clk = { 430 .clk = {
431 .name = "vpll_src", 431 .name = "vpll_src",
432 .enable = exynos4_clksrc_mask_top_ctrl, 432 .enable = exynos4_clksrc_mask_top_ctrl,
433 .ctrlbit = (1 << 0), 433 .ctrlbit = (1 << 0),
434 }, 434 },
435 .sources = &clkset_vpllsrc, 435 .sources = &exynos4_clkset_vpllsrc,
436 .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 }, 436 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
437}; 437};
438 438
439static struct clk *clkset_sclk_vpll_list[] = { 439static struct clk *exynos4_clkset_sclk_vpll_list[] = {
440 [0] = &clk_vpllsrc.clk, 440 [0] = &exynos4_clk_vpllsrc.clk,
441 [1] = &clk_fout_vpll, 441 [1] = &clk_fout_vpll,
442}; 442};
443 443
444static struct clksrc_sources clkset_sclk_vpll = { 444static struct clksrc_sources exynos4_clkset_sclk_vpll = {
445 .sources = clkset_sclk_vpll_list, 445 .sources = exynos4_clkset_sclk_vpll_list,
446 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list), 446 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
447}; 447};
448 448
449static struct clksrc_clk clk_sclk_vpll = { 449static struct clksrc_clk exynos4_clk_sclk_vpll = {
450 .clk = { 450 .clk = {
451 .name = "sclk_vpll", 451 .name = "sclk_vpll",
452 }, 452 },
453 .sources = &clkset_sclk_vpll, 453 .sources = &exynos4_clkset_sclk_vpll,
454 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 }, 454 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
455}; 455};
456 456
457static struct clk init_clocks_off[] = { 457static struct clk exynos4_init_clocks_off[] = {
458 { 458 {
459 .name = "timers", 459 .name = "timers",
460 .parent = &clk_aclk_100.clk, 460 .parent = &exynos4_clk_aclk_100.clk,
461 .enable = exynos4_clk_ip_peril_ctrl, 461 .enable = exynos4_clk_ip_peril_ctrl,
462 .ctrlbit = (1<<24), 462 .ctrlbit = (1<<24),
463 }, { 463 }, {
@@ -498,30 +498,30 @@ static struct clk init_clocks_off[] = {
498 }, { 498 }, {
499 .name = "hsmmc", 499 .name = "hsmmc",
500 .devname = "s3c-sdhci.0", 500 .devname = "s3c-sdhci.0",
501 .parent = &clk_aclk_133.clk, 501 .parent = &exynos4_clk_aclk_133.clk,
502 .enable = exynos4_clk_ip_fsys_ctrl, 502 .enable = exynos4_clk_ip_fsys_ctrl,
503 .ctrlbit = (1 << 5), 503 .ctrlbit = (1 << 5),
504 }, { 504 }, {
505 .name = "hsmmc", 505 .name = "hsmmc",
506 .devname = "s3c-sdhci.1", 506 .devname = "s3c-sdhci.1",
507 .parent = &clk_aclk_133.clk, 507 .parent = &exynos4_clk_aclk_133.clk,
508 .enable = exynos4_clk_ip_fsys_ctrl, 508 .enable = exynos4_clk_ip_fsys_ctrl,
509 .ctrlbit = (1 << 6), 509 .ctrlbit = (1 << 6),
510 }, { 510 }, {
511 .name = "hsmmc", 511 .name = "hsmmc",
512 .devname = "s3c-sdhci.2", 512 .devname = "s3c-sdhci.2",
513 .parent = &clk_aclk_133.clk, 513 .parent = &exynos4_clk_aclk_133.clk,
514 .enable = exynos4_clk_ip_fsys_ctrl, 514 .enable = exynos4_clk_ip_fsys_ctrl,
515 .ctrlbit = (1 << 7), 515 .ctrlbit = (1 << 7),
516 }, { 516 }, {
517 .name = "hsmmc", 517 .name = "hsmmc",
518 .devname = "s3c-sdhci.3", 518 .devname = "s3c-sdhci.3",
519 .parent = &clk_aclk_133.clk, 519 .parent = &exynos4_clk_aclk_133.clk,
520 .enable = exynos4_clk_ip_fsys_ctrl, 520 .enable = exynos4_clk_ip_fsys_ctrl,
521 .ctrlbit = (1 << 8), 521 .ctrlbit = (1 << 8),
522 }, { 522 }, {
523 .name = "dwmmc", 523 .name = "dwmmc",
524 .parent = &clk_aclk_133.clk, 524 .parent = &exynos4_clk_aclk_133.clk,
525 .enable = exynos4_clk_ip_fsys_ctrl, 525 .enable = exynos4_clk_ip_fsys_ctrl,
526 .ctrlbit = (1 << 9), 526 .ctrlbit = (1 << 9),
527 }, { 527 }, {
@@ -568,7 +568,7 @@ static struct clk init_clocks_off[] = {
568 .ctrlbit = (1 << 15), 568 .ctrlbit = (1 << 15),
569 }, { 569 }, {
570 .name = "watchdog", 570 .name = "watchdog",
571 .parent = &clk_aclk_100.clk, 571 .parent = &exynos4_clk_aclk_100.clk,
572 .enable = exynos4_clk_ip_perir_ctrl, 572 .enable = exynos4_clk_ip_perir_ctrl,
573 .ctrlbit = (1 << 14), 573 .ctrlbit = (1 << 14),
574 }, { 574 }, {
@@ -626,55 +626,55 @@ static struct clk init_clocks_off[] = {
626 }, { 626 }, {
627 .name = "i2c", 627 .name = "i2c",
628 .devname = "s3c2440-i2c.0", 628 .devname = "s3c2440-i2c.0",
629 .parent = &clk_aclk_100.clk, 629 .parent = &exynos4_clk_aclk_100.clk,
630 .enable = exynos4_clk_ip_peril_ctrl, 630 .enable = exynos4_clk_ip_peril_ctrl,
631 .ctrlbit = (1 << 6), 631 .ctrlbit = (1 << 6),
632 }, { 632 }, {
633 .name = "i2c", 633 .name = "i2c",
634 .devname = "s3c2440-i2c.1", 634 .devname = "s3c2440-i2c.1",
635 .parent = &clk_aclk_100.clk, 635 .parent = &exynos4_clk_aclk_100.clk,
636 .enable = exynos4_clk_ip_peril_ctrl, 636 .enable = exynos4_clk_ip_peril_ctrl,
637 .ctrlbit = (1 << 7), 637 .ctrlbit = (1 << 7),
638 }, { 638 }, {
639 .name = "i2c", 639 .name = "i2c",
640 .devname = "s3c2440-i2c.2", 640 .devname = "s3c2440-i2c.2",
641 .parent = &clk_aclk_100.clk, 641 .parent = &exynos4_clk_aclk_100.clk,
642 .enable = exynos4_clk_ip_peril_ctrl, 642 .enable = exynos4_clk_ip_peril_ctrl,
643 .ctrlbit = (1 << 8), 643 .ctrlbit = (1 << 8),
644 }, { 644 }, {
645 .name = "i2c", 645 .name = "i2c",
646 .devname = "s3c2440-i2c.3", 646 .devname = "s3c2440-i2c.3",
647 .parent = &clk_aclk_100.clk, 647 .parent = &exynos4_clk_aclk_100.clk,
648 .enable = exynos4_clk_ip_peril_ctrl, 648 .enable = exynos4_clk_ip_peril_ctrl,
649 .ctrlbit = (1 << 9), 649 .ctrlbit = (1 << 9),
650 }, { 650 }, {
651 .name = "i2c", 651 .name = "i2c",
652 .devname = "s3c2440-i2c.4", 652 .devname = "s3c2440-i2c.4",
653 .parent = &clk_aclk_100.clk, 653 .parent = &exynos4_clk_aclk_100.clk,
654 .enable = exynos4_clk_ip_peril_ctrl, 654 .enable = exynos4_clk_ip_peril_ctrl,
655 .ctrlbit = (1 << 10), 655 .ctrlbit = (1 << 10),
656 }, { 656 }, {
657 .name = "i2c", 657 .name = "i2c",
658 .devname = "s3c2440-i2c.5", 658 .devname = "s3c2440-i2c.5",
659 .parent = &clk_aclk_100.clk, 659 .parent = &exynos4_clk_aclk_100.clk,
660 .enable = exynos4_clk_ip_peril_ctrl, 660 .enable = exynos4_clk_ip_peril_ctrl,
661 .ctrlbit = (1 << 11), 661 .ctrlbit = (1 << 11),
662 }, { 662 }, {
663 .name = "i2c", 663 .name = "i2c",
664 .devname = "s3c2440-i2c.6", 664 .devname = "s3c2440-i2c.6",
665 .parent = &clk_aclk_100.clk, 665 .parent = &exynos4_clk_aclk_100.clk,
666 .enable = exynos4_clk_ip_peril_ctrl, 666 .enable = exynos4_clk_ip_peril_ctrl,
667 .ctrlbit = (1 << 12), 667 .ctrlbit = (1 << 12),
668 }, { 668 }, {
669 .name = "i2c", 669 .name = "i2c",
670 .devname = "s3c2440-i2c.7", 670 .devname = "s3c2440-i2c.7",
671 .parent = &clk_aclk_100.clk, 671 .parent = &exynos4_clk_aclk_100.clk,
672 .enable = exynos4_clk_ip_peril_ctrl, 672 .enable = exynos4_clk_ip_peril_ctrl,
673 .ctrlbit = (1 << 13), 673 .ctrlbit = (1 << 13),
674 }, { 674 }, {
675 .name = "i2c", 675 .name = "i2c",
676 .devname = "s3c2440-hdmiphy-i2c", 676 .devname = "s3c2440-hdmiphy-i2c",
677 .parent = &clk_aclk_100.clk, 677 .parent = &exynos4_clk_aclk_100.clk,
678 .enable = exynos4_clk_ip_peril_ctrl, 678 .enable = exynos4_clk_ip_peril_ctrl,
679 .ctrlbit = (1 << 14), 679 .ctrlbit = (1 << 14),
680 }, { 680 }, {
@@ -736,7 +736,7 @@ static struct clk init_clocks_off[] = {
736 } 736 }
737}; 737};
738 738
739static struct clk init_clocks[] = { 739static struct clk exynos4_init_clocks_on[] = {
740 { 740 {
741 .name = "uart", 741 .name = "uart",
742 .devname = "s5pv210-uart.0", 742 .devname = "s5pv210-uart.0",
@@ -770,259 +770,259 @@ static struct clk init_clocks[] = {
770 } 770 }
771}; 771};
772 772
773static struct clk clk_pdma0 = { 773static struct clk exynos4_clk_pdma0 = {
774 .name = "dma", 774 .name = "dma",
775 .devname = "dma-pl330.0", 775 .devname = "dma-pl330.0",
776 .enable = exynos4_clk_ip_fsys_ctrl, 776 .enable = exynos4_clk_ip_fsys_ctrl,
777 .ctrlbit = (1 << 0), 777 .ctrlbit = (1 << 0),
778}; 778};
779 779
780static struct clk clk_pdma1 = { 780static struct clk exynos4_clk_pdma1 = {
781 .name = "dma", 781 .name = "dma",
782 .devname = "dma-pl330.1", 782 .devname = "dma-pl330.1",
783 .enable = exynos4_clk_ip_fsys_ctrl, 783 .enable = exynos4_clk_ip_fsys_ctrl,
784 .ctrlbit = (1 << 1), 784 .ctrlbit = (1 << 1),
785}; 785};
786 786
787struct clk *clkset_group_list[] = { 787struct clk *exynos4_clkset_group_list[] = {
788 [0] = &clk_ext_xtal_mux, 788 [0] = &clk_ext_xtal_mux,
789 [1] = &clk_xusbxti, 789 [1] = &clk_xusbxti,
790 [2] = &clk_sclk_hdmi27m, 790 [2] = &exynos4_clk_sclk_hdmi27m,
791 [3] = &clk_sclk_usbphy0, 791 [3] = &exynos4_clk_sclk_usbphy0,
792 [4] = &clk_sclk_usbphy1, 792 [4] = &exynos4_clk_sclk_usbphy1,
793 [5] = &clk_sclk_hdmiphy, 793 [5] = &exynos4_clk_sclk_hdmiphy,
794 [6] = &clk_mout_mpll.clk, 794 [6] = &exynos4_clk_mout_mpll.clk,
795 [7] = &clk_mout_epll.clk, 795 [7] = &exynos4_clk_mout_epll.clk,
796 [8] = &clk_sclk_vpll.clk, 796 [8] = &exynos4_clk_sclk_vpll.clk,
797}; 797};
798 798
799struct clksrc_sources clkset_group = { 799struct clksrc_sources exynos4_clkset_group = {
800 .sources = clkset_group_list, 800 .sources = exynos4_clkset_group_list,
801 .nr_sources = ARRAY_SIZE(clkset_group_list), 801 .nr_sources = ARRAY_SIZE(exynos4_clkset_group_list),
802}; 802};
803 803
804static struct clk *clkset_mout_g2d0_list[] = { 804static struct clk *exynos4_clkset_mout_g2d0_list[] = {
805 [0] = &clk_mout_mpll.clk, 805 [0] = &exynos4_clk_mout_mpll.clk,
806 [1] = &clk_sclk_apll.clk, 806 [1] = &exynos4_clk_sclk_apll.clk,
807}; 807};
808 808
809static struct clksrc_sources clkset_mout_g2d0 = { 809static struct clksrc_sources exynos4_clkset_mout_g2d0 = {
810 .sources = clkset_mout_g2d0_list, 810 .sources = exynos4_clkset_mout_g2d0_list,
811 .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list), 811 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
812}; 812};
813 813
814static struct clksrc_clk clk_mout_g2d0 = { 814static struct clksrc_clk exynos4_clk_mout_g2d0 = {
815 .clk = { 815 .clk = {
816 .name = "mout_g2d0", 816 .name = "mout_g2d0",
817 }, 817 },
818 .sources = &clkset_mout_g2d0, 818 .sources = &exynos4_clkset_mout_g2d0,
819 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 }, 819 .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
820}; 820};
821 821
822static struct clk *clkset_mout_g2d1_list[] = { 822static struct clk *exynos4_clkset_mout_g2d1_list[] = {
823 [0] = &clk_mout_epll.clk, 823 [0] = &exynos4_clk_mout_epll.clk,
824 [1] = &clk_sclk_vpll.clk, 824 [1] = &exynos4_clk_sclk_vpll.clk,
825}; 825};
826 826
827static struct clksrc_sources clkset_mout_g2d1 = { 827static struct clksrc_sources exynos4_clkset_mout_g2d1 = {
828 .sources = clkset_mout_g2d1_list, 828 .sources = exynos4_clkset_mout_g2d1_list,
829 .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list), 829 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
830}; 830};
831 831
832static struct clksrc_clk clk_mout_g2d1 = { 832static struct clksrc_clk exynos4_clk_mout_g2d1 = {
833 .clk = { 833 .clk = {
834 .name = "mout_g2d1", 834 .name = "mout_g2d1",
835 }, 835 },
836 .sources = &clkset_mout_g2d1, 836 .sources = &exynos4_clkset_mout_g2d1,
837 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 }, 837 .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
838}; 838};
839 839
840static struct clk *clkset_mout_g2d_list[] = { 840static struct clk *exynos4_clkset_mout_g2d_list[] = {
841 [0] = &clk_mout_g2d0.clk, 841 [0] = &exynos4_clk_mout_g2d0.clk,
842 [1] = &clk_mout_g2d1.clk, 842 [1] = &exynos4_clk_mout_g2d1.clk,
843}; 843};
844 844
845static struct clksrc_sources clkset_mout_g2d = { 845static struct clksrc_sources exynos4_clkset_mout_g2d = {
846 .sources = clkset_mout_g2d_list, 846 .sources = exynos4_clkset_mout_g2d_list,
847 .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list), 847 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d_list),
848}; 848};
849 849
850static struct clk *clkset_mout_mfc0_list[] = { 850static struct clk *exynos4_clkset_mout_mfc0_list[] = {
851 [0] = &clk_mout_mpll.clk, 851 [0] = &exynos4_clk_mout_mpll.clk,
852 [1] = &clk_sclk_apll.clk, 852 [1] = &exynos4_clk_sclk_apll.clk,
853}; 853};
854 854
855static struct clksrc_sources clkset_mout_mfc0 = { 855static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
856 .sources = clkset_mout_mfc0_list, 856 .sources = exynos4_clkset_mout_mfc0_list,
857 .nr_sources = ARRAY_SIZE(clkset_mout_mfc0_list), 857 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
858}; 858};
859 859
860static struct clksrc_clk clk_mout_mfc0 = { 860static struct clksrc_clk exynos4_clk_mout_mfc0 = {
861 .clk = { 861 .clk = {
862 .name = "mout_mfc0", 862 .name = "mout_mfc0",
863 }, 863 },
864 .sources = &clkset_mout_mfc0, 864 .sources = &exynos4_clkset_mout_mfc0,
865 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 }, 865 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
866}; 866};
867 867
868static struct clk *clkset_mout_mfc1_list[] = { 868static struct clk *exynos4_clkset_mout_mfc1_list[] = {
869 [0] = &clk_mout_epll.clk, 869 [0] = &exynos4_clk_mout_epll.clk,
870 [1] = &clk_sclk_vpll.clk, 870 [1] = &exynos4_clk_sclk_vpll.clk,
871}; 871};
872 872
873static struct clksrc_sources clkset_mout_mfc1 = { 873static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
874 .sources = clkset_mout_mfc1_list, 874 .sources = exynos4_clkset_mout_mfc1_list,
875 .nr_sources = ARRAY_SIZE(clkset_mout_mfc1_list), 875 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
876}; 876};
877 877
878static struct clksrc_clk clk_mout_mfc1 = { 878static struct clksrc_clk exynos4_clk_mout_mfc1 = {
879 .clk = { 879 .clk = {
880 .name = "mout_mfc1", 880 .name = "mout_mfc1",
881 }, 881 },
882 .sources = &clkset_mout_mfc1, 882 .sources = &exynos4_clkset_mout_mfc1,
883 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 }, 883 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
884}; 884};
885 885
886static struct clk *clkset_mout_mfc_list[] = { 886static struct clk *exynos4_clkset_mout_mfc_list[] = {
887 [0] = &clk_mout_mfc0.clk, 887 [0] = &exynos4_clk_mout_mfc0.clk,
888 [1] = &clk_mout_mfc1.clk, 888 [1] = &exynos4_clk_mout_mfc1.clk,
889}; 889};
890 890
891static struct clksrc_sources clkset_mout_mfc = { 891static struct clksrc_sources exynos4_clkset_mout_mfc = {
892 .sources = clkset_mout_mfc_list, 892 .sources = exynos4_clkset_mout_mfc_list,
893 .nr_sources = ARRAY_SIZE(clkset_mout_mfc_list), 893 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
894}; 894};
895 895
896static struct clk *clkset_sclk_dac_list[] = { 896static struct clk *exynos4_clkset_sclk_dac_list[] = {
897 [0] = &clk_sclk_vpll.clk, 897 [0] = &exynos4_clk_sclk_vpll.clk,
898 [1] = &clk_sclk_hdmiphy, 898 [1] = &exynos4_clk_sclk_hdmiphy,
899}; 899};
900 900
901static struct clksrc_sources clkset_sclk_dac = { 901static struct clksrc_sources exynos4_clkset_sclk_dac = {
902 .sources = clkset_sclk_dac_list, 902 .sources = exynos4_clkset_sclk_dac_list,
903 .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list), 903 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
904}; 904};
905 905
906static struct clksrc_clk clk_sclk_dac = { 906static struct clksrc_clk exynos4_clk_sclk_dac = {
907 .clk = { 907 .clk = {
908 .name = "sclk_dac", 908 .name = "sclk_dac",
909 .enable = exynos4_clksrc_mask_tv_ctrl, 909 .enable = exynos4_clksrc_mask_tv_ctrl,
910 .ctrlbit = (1 << 8), 910 .ctrlbit = (1 << 8),
911 }, 911 },
912 .sources = &clkset_sclk_dac, 912 .sources = &exynos4_clkset_sclk_dac,
913 .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 }, 913 .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
914}; 914};
915 915
916static struct clksrc_clk clk_sclk_pixel = { 916static struct clksrc_clk exynos4_clk_sclk_pixel = {
917 .clk = { 917 .clk = {
918 .name = "sclk_pixel", 918 .name = "sclk_pixel",
919 .parent = &clk_sclk_vpll.clk, 919 .parent = &exynos4_clk_sclk_vpll.clk,
920 }, 920 },
921 .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 }, 921 .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
922}; 922};
923 923
924static struct clk *clkset_sclk_hdmi_list[] = { 924static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
925 [0] = &clk_sclk_pixel.clk, 925 [0] = &exynos4_clk_sclk_pixel.clk,
926 [1] = &clk_sclk_hdmiphy, 926 [1] = &exynos4_clk_sclk_hdmiphy,
927}; 927};
928 928
929static struct clksrc_sources clkset_sclk_hdmi = { 929static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
930 .sources = clkset_sclk_hdmi_list, 930 .sources = exynos4_clkset_sclk_hdmi_list,
931 .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list), 931 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
932}; 932};
933 933
934static struct clksrc_clk clk_sclk_hdmi = { 934static struct clksrc_clk exynos4_clk_sclk_hdmi = {
935 .clk = { 935 .clk = {
936 .name = "sclk_hdmi", 936 .name = "sclk_hdmi",
937 .enable = exynos4_clksrc_mask_tv_ctrl, 937 .enable = exynos4_clksrc_mask_tv_ctrl,
938 .ctrlbit = (1 << 0), 938 .ctrlbit = (1 << 0),
939 }, 939 },
940 .sources = &clkset_sclk_hdmi, 940 .sources = &exynos4_clkset_sclk_hdmi,
941 .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 }, 941 .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
942}; 942};
943 943
944static struct clk *clkset_sclk_mixer_list[] = { 944static struct clk *exynos4_clkset_sclk_mixer_list[] = {
945 [0] = &clk_sclk_dac.clk, 945 [0] = &exynos4_clk_sclk_dac.clk,
946 [1] = &clk_sclk_hdmi.clk, 946 [1] = &exynos4_clk_sclk_hdmi.clk,
947}; 947};
948 948
949static struct clksrc_sources clkset_sclk_mixer = { 949static struct clksrc_sources exynos4_clkset_sclk_mixer = {
950 .sources = clkset_sclk_mixer_list, 950 .sources = exynos4_clkset_sclk_mixer_list,
951 .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list), 951 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
952}; 952};
953 953
954static struct clksrc_clk clk_sclk_mixer = { 954static struct clksrc_clk exynos4_clk_sclk_mixer = {
955 .clk = { 955 .clk = {
956 .name = "sclk_mixer", 956 .name = "sclk_mixer",
957 .enable = exynos4_clksrc_mask_tv_ctrl, 957 .enable = exynos4_clksrc_mask_tv_ctrl,
958 .ctrlbit = (1 << 4), 958 .ctrlbit = (1 << 4),
959 }, 959 },
960 .sources = &clkset_sclk_mixer, 960 .sources = &exynos4_clkset_sclk_mixer,
961 .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 }, 961 .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
962}; 962};
963 963
964static struct clksrc_clk *sclk_tv[] = { 964static struct clksrc_clk *exynos4_sclk_tv[] = {
965 &clk_sclk_dac, 965 &exynos4_clk_sclk_dac,
966 &clk_sclk_pixel, 966 &exynos4_clk_sclk_pixel,
967 &clk_sclk_hdmi, 967 &exynos4_clk_sclk_hdmi,
968 &clk_sclk_mixer, 968 &exynos4_clk_sclk_mixer,
969}; 969};
970 970
971static struct clksrc_clk clk_dout_mmc0 = { 971static struct clksrc_clk exynos4_clk_dout_mmc0 = {
972 .clk = { 972 .clk = {
973 .name = "dout_mmc0", 973 .name = "dout_mmc0",
974 }, 974 },
975 .sources = &clkset_group, 975 .sources = &exynos4_clkset_group,
976 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 }, 976 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
977 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 }, 977 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
978}; 978};
979 979
980static struct clksrc_clk clk_dout_mmc1 = { 980static struct clksrc_clk exynos4_clk_dout_mmc1 = {
981 .clk = { 981 .clk = {
982 .name = "dout_mmc1", 982 .name = "dout_mmc1",
983 }, 983 },
984 .sources = &clkset_group, 984 .sources = &exynos4_clkset_group,
985 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 }, 985 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
986 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 }, 986 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
987}; 987};
988 988
989static struct clksrc_clk clk_dout_mmc2 = { 989static struct clksrc_clk exynos4_clk_dout_mmc2 = {
990 .clk = { 990 .clk = {
991 .name = "dout_mmc2", 991 .name = "dout_mmc2",
992 }, 992 },
993 .sources = &clkset_group, 993 .sources = &exynos4_clkset_group,
994 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 }, 994 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
995 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 }, 995 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
996}; 996};
997 997
998static struct clksrc_clk clk_dout_mmc3 = { 998static struct clksrc_clk exynos4_clk_dout_mmc3 = {
999 .clk = { 999 .clk = {
1000 .name = "dout_mmc3", 1000 .name = "dout_mmc3",
1001 }, 1001 },
1002 .sources = &clkset_group, 1002 .sources = &exynos4_clkset_group,
1003 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 }, 1003 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
1004 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 }, 1004 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1005}; 1005};
1006 1006
1007static struct clksrc_clk clk_dout_mmc4 = { 1007static struct clksrc_clk exynos4_clk_dout_mmc4 = {
1008 .clk = { 1008 .clk = {
1009 .name = "dout_mmc4", 1009 .name = "dout_mmc4",
1010 }, 1010 },
1011 .sources = &clkset_group, 1011 .sources = &exynos4_clkset_group,
1012 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 }, 1012 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
1013 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 }, 1013 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1014}; 1014};
1015 1015
1016static struct clksrc_clk clksrcs[] = { 1016static struct clksrc_clk exynos4_clksrcs[] = {
1017 { 1017 {
1018 .clk = { 1018 .clk = {
1019 .name = "sclk_pwm", 1019 .name = "sclk_pwm",
1020 .enable = exynos4_clksrc_mask_peril0_ctrl, 1020 .enable = exynos4_clksrc_mask_peril0_ctrl,
1021 .ctrlbit = (1 << 24), 1021 .ctrlbit = (1 << 24),
1022 }, 1022 },
1023 .sources = &clkset_group, 1023 .sources = &exynos4_clkset_group,
1024 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 }, 1024 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1025 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 }, 1025 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1026 }, { 1026 }, {
1027 .clk = { 1027 .clk = {
1028 .name = "sclk_csis", 1028 .name = "sclk_csis",
@@ -1030,9 +1030,9 @@ static struct clksrc_clk clksrcs[] = {
1030 .enable = exynos4_clksrc_mask_cam_ctrl, 1030 .enable = exynos4_clksrc_mask_cam_ctrl,
1031 .ctrlbit = (1 << 24), 1031 .ctrlbit = (1 << 24),
1032 }, 1032 },
1033 .sources = &clkset_group, 1033 .sources = &exynos4_clkset_group,
1034 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 }, 1034 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
1035 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 }, 1035 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
1036 }, { 1036 }, {
1037 .clk = { 1037 .clk = {
1038 .name = "sclk_csis", 1038 .name = "sclk_csis",
@@ -1040,27 +1040,27 @@ static struct clksrc_clk clksrcs[] = {
1040 .enable = exynos4_clksrc_mask_cam_ctrl, 1040 .enable = exynos4_clksrc_mask_cam_ctrl,
1041 .ctrlbit = (1 << 28), 1041 .ctrlbit = (1 << 28),
1042 }, 1042 },
1043 .sources = &clkset_group, 1043 .sources = &exynos4_clkset_group,
1044 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 }, 1044 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
1045 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 }, 1045 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
1046 }, { 1046 }, {
1047 .clk = { 1047 .clk = {
1048 .name = "sclk_cam0", 1048 .name = "sclk_cam0",
1049 .enable = exynos4_clksrc_mask_cam_ctrl, 1049 .enable = exynos4_clksrc_mask_cam_ctrl,
1050 .ctrlbit = (1 << 16), 1050 .ctrlbit = (1 << 16),
1051 }, 1051 },
1052 .sources = &clkset_group, 1052 .sources = &exynos4_clkset_group,
1053 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 }, 1053 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
1054 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 }, 1054 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
1055 }, { 1055 }, {
1056 .clk = { 1056 .clk = {
1057 .name = "sclk_cam1", 1057 .name = "sclk_cam1",
1058 .enable = exynos4_clksrc_mask_cam_ctrl, 1058 .enable = exynos4_clksrc_mask_cam_ctrl,
1059 .ctrlbit = (1 << 20), 1059 .ctrlbit = (1 << 20),
1060 }, 1060 },
1061 .sources = &clkset_group, 1061 .sources = &exynos4_clkset_group,
1062 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 }, 1062 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
1063 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 }, 1063 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
1064 }, { 1064 }, {
1065 .clk = { 1065 .clk = {
1066 .name = "sclk_fimc", 1066 .name = "sclk_fimc",
@@ -1068,9 +1068,9 @@ static struct clksrc_clk clksrcs[] = {
1068 .enable = exynos4_clksrc_mask_cam_ctrl, 1068 .enable = exynos4_clksrc_mask_cam_ctrl,
1069 .ctrlbit = (1 << 0), 1069 .ctrlbit = (1 << 0),
1070 }, 1070 },
1071 .sources = &clkset_group, 1071 .sources = &exynos4_clkset_group,
1072 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 }, 1072 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
1073 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 }, 1073 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
1074 }, { 1074 }, {
1075 .clk = { 1075 .clk = {
1076 .name = "sclk_fimc", 1076 .name = "sclk_fimc",
@@ -1078,9 +1078,9 @@ static struct clksrc_clk clksrcs[] = {
1078 .enable = exynos4_clksrc_mask_cam_ctrl, 1078 .enable = exynos4_clksrc_mask_cam_ctrl,
1079 .ctrlbit = (1 << 4), 1079 .ctrlbit = (1 << 4),
1080 }, 1080 },
1081 .sources = &clkset_group, 1081 .sources = &exynos4_clkset_group,
1082 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 }, 1082 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
1083 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 }, 1083 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
1084 }, { 1084 }, {
1085 .clk = { 1085 .clk = {
1086 .name = "sclk_fimc", 1086 .name = "sclk_fimc",
@@ -1088,9 +1088,9 @@ static struct clksrc_clk clksrcs[] = {
1088 .enable = exynos4_clksrc_mask_cam_ctrl, 1088 .enable = exynos4_clksrc_mask_cam_ctrl,
1089 .ctrlbit = (1 << 8), 1089 .ctrlbit = (1 << 8),
1090 }, 1090 },
1091 .sources = &clkset_group, 1091 .sources = &exynos4_clkset_group,
1092 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 }, 1092 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
1093 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 }, 1093 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
1094 }, { 1094 }, {
1095 .clk = { 1095 .clk = {
1096 .name = "sclk_fimc", 1096 .name = "sclk_fimc",
@@ -1098,9 +1098,9 @@ static struct clksrc_clk clksrcs[] = {
1098 .enable = exynos4_clksrc_mask_cam_ctrl, 1098 .enable = exynos4_clksrc_mask_cam_ctrl,
1099 .ctrlbit = (1 << 12), 1099 .ctrlbit = (1 << 12),
1100 }, 1100 },
1101 .sources = &clkset_group, 1101 .sources = &exynos4_clkset_group,
1102 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 }, 1102 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
1103 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 }, 1103 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
1104 }, { 1104 }, {
1105 .clk = { 1105 .clk = {
1106 .name = "sclk_fimd", 1106 .name = "sclk_fimd",
@@ -1108,231 +1108,231 @@ static struct clksrc_clk clksrcs[] = {
1108 .enable = exynos4_clksrc_mask_lcd0_ctrl, 1108 .enable = exynos4_clksrc_mask_lcd0_ctrl,
1109 .ctrlbit = (1 << 0), 1109 .ctrlbit = (1 << 0),
1110 }, 1110 },
1111 .sources = &clkset_group, 1111 .sources = &exynos4_clkset_group,
1112 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 }, 1112 .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
1113 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 }, 1113 .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
1114 }, { 1114 }, {
1115 .clk = { 1115 .clk = {
1116 .name = "sclk_fimg2d", 1116 .name = "sclk_fimg2d",
1117 }, 1117 },
1118 .sources = &clkset_mout_g2d, 1118 .sources = &exynos4_clkset_mout_g2d,
1119 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 }, 1119 .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1120 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 }, 1120 .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1121 }, { 1121 }, {
1122 .clk = { 1122 .clk = {
1123 .name = "sclk_mfc", 1123 .name = "sclk_mfc",
1124 .devname = "s5p-mfc", 1124 .devname = "s5p-mfc",
1125 }, 1125 },
1126 .sources = &clkset_mout_mfc, 1126 .sources = &exynos4_clkset_mout_mfc,
1127 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 }, 1127 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
1128 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 }, 1128 .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
1129 }, { 1129 }, {
1130 .clk = { 1130 .clk = {
1131 .name = "sclk_dwmmc", 1131 .name = "sclk_dwmmc",
1132 .parent = &clk_dout_mmc4.clk, 1132 .parent = &exynos4_clk_dout_mmc4.clk,
1133 .enable = exynos4_clksrc_mask_fsys_ctrl, 1133 .enable = exynos4_clksrc_mask_fsys_ctrl,
1134 .ctrlbit = (1 << 16), 1134 .ctrlbit = (1 << 16),
1135 }, 1135 },
1136 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 }, 1136 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1137 } 1137 }
1138}; 1138};
1139 1139
1140static struct clksrc_clk clk_sclk_uart0 = { 1140static struct clksrc_clk exynos4_clk_sclk_uart0 = {
1141 .clk = { 1141 .clk = {
1142 .name = "uclk1", 1142 .name = "uclk1",
1143 .devname = "exynos4210-uart.0", 1143 .devname = "exynos4210-uart.0",
1144 .enable = exynos4_clksrc_mask_peril0_ctrl, 1144 .enable = exynos4_clksrc_mask_peril0_ctrl,
1145 .ctrlbit = (1 << 0), 1145 .ctrlbit = (1 << 0),
1146 }, 1146 },
1147 .sources = &clkset_group, 1147 .sources = &exynos4_clkset_group,
1148 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 }, 1148 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1149 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 }, 1149 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1150}; 1150};
1151 1151
1152static struct clksrc_clk clk_sclk_uart1 = { 1152static struct clksrc_clk exynos4_clk_sclk_uart1 = {
1153 .clk = { 1153 .clk = {
1154 .name = "uclk1", 1154 .name = "uclk1",
1155 .devname = "exynos4210-uart.1", 1155 .devname = "exynos4210-uart.1",
1156 .enable = exynos4_clksrc_mask_peril0_ctrl, 1156 .enable = exynos4_clksrc_mask_peril0_ctrl,
1157 .ctrlbit = (1 << 4), 1157 .ctrlbit = (1 << 4),
1158 }, 1158 },
1159 .sources = &clkset_group, 1159 .sources = &exynos4_clkset_group,
1160 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 }, 1160 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1161 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 }, 1161 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1162}; 1162};
1163 1163
1164static struct clksrc_clk clk_sclk_uart2 = { 1164static struct clksrc_clk exynos4_clk_sclk_uart2 = {
1165 .clk = { 1165 .clk = {
1166 .name = "uclk1", 1166 .name = "uclk1",
1167 .devname = "exynos4210-uart.2", 1167 .devname = "exynos4210-uart.2",
1168 .enable = exynos4_clksrc_mask_peril0_ctrl, 1168 .enable = exynos4_clksrc_mask_peril0_ctrl,
1169 .ctrlbit = (1 << 8), 1169 .ctrlbit = (1 << 8),
1170 }, 1170 },
1171 .sources = &clkset_group, 1171 .sources = &exynos4_clkset_group,
1172 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 }, 1172 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1173 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 }, 1173 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1174}; 1174};
1175 1175
1176static struct clksrc_clk clk_sclk_uart3 = { 1176static struct clksrc_clk exynos4_clk_sclk_uart3 = {
1177 .clk = { 1177 .clk = {
1178 .name = "uclk1", 1178 .name = "uclk1",
1179 .devname = "exynos4210-uart.3", 1179 .devname = "exynos4210-uart.3",
1180 .enable = exynos4_clksrc_mask_peril0_ctrl, 1180 .enable = exynos4_clksrc_mask_peril0_ctrl,
1181 .ctrlbit = (1 << 12), 1181 .ctrlbit = (1 << 12),
1182 }, 1182 },
1183 .sources = &clkset_group, 1183 .sources = &exynos4_clkset_group,
1184 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 }, 1184 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1185 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 }, 1185 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1186}; 1186};
1187 1187
1188static struct clksrc_clk clk_sclk_mmc0 = { 1188static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
1189 .clk = { 1189 .clk = {
1190 .name = "sclk_mmc", 1190 .name = "sclk_mmc",
1191 .devname = "s3c-sdhci.0", 1191 .devname = "s3c-sdhci.0",
1192 .parent = &clk_dout_mmc0.clk, 1192 .parent = &exynos4_clk_dout_mmc0.clk,
1193 .enable = exynos4_clksrc_mask_fsys_ctrl, 1193 .enable = exynos4_clksrc_mask_fsys_ctrl,
1194 .ctrlbit = (1 << 0), 1194 .ctrlbit = (1 << 0),
1195 }, 1195 },
1196 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 }, 1196 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1197}; 1197};
1198 1198
1199static struct clksrc_clk clk_sclk_mmc1 = { 1199static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
1200 .clk = { 1200 .clk = {
1201 .name = "sclk_mmc", 1201 .name = "sclk_mmc",
1202 .devname = "s3c-sdhci.1", 1202 .devname = "s3c-sdhci.1",
1203 .parent = &clk_dout_mmc1.clk, 1203 .parent = &exynos4_clk_dout_mmc1.clk,
1204 .enable = exynos4_clksrc_mask_fsys_ctrl, 1204 .enable = exynos4_clksrc_mask_fsys_ctrl,
1205 .ctrlbit = (1 << 4), 1205 .ctrlbit = (1 << 4),
1206 }, 1206 },
1207 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 }, 1207 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1208}; 1208};
1209 1209
1210static struct clksrc_clk clk_sclk_mmc2 = { 1210static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
1211 .clk = { 1211 .clk = {
1212 .name = "sclk_mmc", 1212 .name = "sclk_mmc",
1213 .devname = "s3c-sdhci.2", 1213 .devname = "s3c-sdhci.2",
1214 .parent = &clk_dout_mmc2.clk, 1214 .parent = &exynos4_clk_dout_mmc2.clk,
1215 .enable = exynos4_clksrc_mask_fsys_ctrl, 1215 .enable = exynos4_clksrc_mask_fsys_ctrl,
1216 .ctrlbit = (1 << 8), 1216 .ctrlbit = (1 << 8),
1217 }, 1217 },
1218 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 }, 1218 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1219}; 1219};
1220 1220
1221static struct clksrc_clk clk_sclk_mmc3 = { 1221static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
1222 .clk = { 1222 .clk = {
1223 .name = "sclk_mmc", 1223 .name = "sclk_mmc",
1224 .devname = "s3c-sdhci.3", 1224 .devname = "s3c-sdhci.3",
1225 .parent = &clk_dout_mmc3.clk, 1225 .parent = &exynos4_clk_dout_mmc3.clk,
1226 .enable = exynos4_clksrc_mask_fsys_ctrl, 1226 .enable = exynos4_clksrc_mask_fsys_ctrl,
1227 .ctrlbit = (1 << 12), 1227 .ctrlbit = (1 << 12),
1228 }, 1228 },
1229 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, 1229 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1230}; 1230};
1231 1231
1232static struct clksrc_clk clk_sclk_spi0 = { 1232static struct clksrc_clk exynos4_clk_sclk_spi0 = {
1233 .clk = { 1233 .clk = {
1234 .name = "sclk_spi", 1234 .name = "sclk_spi",
1235 .devname = "s3c64xx-spi.0", 1235 .devname = "s3c64xx-spi.0",
1236 .enable = exynos4_clksrc_mask_peril1_ctrl, 1236 .enable = exynos4_clksrc_mask_peril1_ctrl,
1237 .ctrlbit = (1 << 16), 1237 .ctrlbit = (1 << 16),
1238 }, 1238 },
1239 .sources = &clkset_group, 1239 .sources = &exynos4_clkset_group,
1240 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 }, 1240 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1241 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 }, 1241 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1242}; 1242};
1243 1243
1244static struct clksrc_clk clk_sclk_spi1 = { 1244static struct clksrc_clk exynos4_clk_sclk_spi1 = {
1245 .clk = { 1245 .clk = {
1246 .name = "sclk_spi", 1246 .name = "sclk_spi",
1247 .devname = "s3c64xx-spi.1", 1247 .devname = "s3c64xx-spi.1",
1248 .enable = exynos4_clksrc_mask_peril1_ctrl, 1248 .enable = exynos4_clksrc_mask_peril1_ctrl,
1249 .ctrlbit = (1 << 20), 1249 .ctrlbit = (1 << 20),
1250 }, 1250 },
1251 .sources = &clkset_group, 1251 .sources = &exynos4_clkset_group,
1252 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 }, 1252 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1253 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 }, 1253 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1254}; 1254};
1255 1255
1256static struct clksrc_clk clk_sclk_spi2 = { 1256static struct clksrc_clk exynos4_clk_sclk_spi2 = {
1257 .clk = { 1257 .clk = {
1258 .name = "sclk_spi", 1258 .name = "sclk_spi",
1259 .devname = "s3c64xx-spi.2", 1259 .devname = "s3c64xx-spi.2",
1260 .enable = exynos4_clksrc_mask_peril1_ctrl, 1260 .enable = exynos4_clksrc_mask_peril1_ctrl,
1261 .ctrlbit = (1 << 24), 1261 .ctrlbit = (1 << 24),
1262 }, 1262 },
1263 .sources = &clkset_group, 1263 .sources = &exynos4_clkset_group,
1264 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 }, 1264 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1265 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 }, 1265 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1266}; 1266};
1267 1267
1268/* Clock initialization code */ 1268/* Clock initialization code */
1269static struct clksrc_clk *sysclks[] = { 1269static struct clksrc_clk *exynos4_sysclks[] = {
1270 &clk_mout_apll, 1270 &exynos4_clk_mout_apll,
1271 &clk_sclk_apll, 1271 &exynos4_clk_sclk_apll,
1272 &clk_mout_epll, 1272 &exynos4_clk_mout_epll,
1273 &clk_mout_mpll, 1273 &exynos4_clk_mout_mpll,
1274 &clk_moutcore, 1274 &exynos4_clk_moutcore,
1275 &clk_coreclk, 1275 &exynos4_clk_coreclk,
1276 &clk_armclk, 1276 &exynos4_clk_armclk,
1277 &clk_aclk_corem0, 1277 &exynos4_clk_aclk_corem0,
1278 &clk_aclk_cores, 1278 &exynos4_clk_aclk_cores,
1279 &clk_aclk_corem1, 1279 &exynos4_clk_aclk_corem1,
1280 &clk_periphclk, 1280 &exynos4_clk_periphclk,
1281 &clk_mout_corebus, 1281 &exynos4_clk_mout_corebus,
1282 &clk_sclk_dmc, 1282 &exynos4_clk_sclk_dmc,
1283 &clk_aclk_cored, 1283 &exynos4_clk_aclk_cored,
1284 &clk_aclk_corep, 1284 &exynos4_clk_aclk_corep,
1285 &clk_aclk_acp, 1285 &exynos4_clk_aclk_acp,
1286 &clk_pclk_acp, 1286 &exynos4_clk_pclk_acp,
1287 &clk_vpllsrc, 1287 &exynos4_clk_vpllsrc,
1288 &clk_sclk_vpll, 1288 &exynos4_clk_sclk_vpll,
1289 &clk_aclk_200, 1289 &exynos4_clk_aclk_200,
1290 &clk_aclk_100, 1290 &exynos4_clk_aclk_100,
1291 &clk_aclk_160, 1291 &exynos4_clk_aclk_160,
1292 &clk_aclk_133, 1292 &exynos4_clk_aclk_133,
1293 &clk_dout_mmc0, 1293 &exynos4_clk_dout_mmc0,
1294 &clk_dout_mmc1, 1294 &exynos4_clk_dout_mmc1,
1295 &clk_dout_mmc2, 1295 &exynos4_clk_dout_mmc2,
1296 &clk_dout_mmc3, 1296 &exynos4_clk_dout_mmc3,
1297 &clk_dout_mmc4, 1297 &exynos4_clk_dout_mmc4,
1298 &clk_mout_mfc0, 1298 &exynos4_clk_mout_mfc0,
1299 &clk_mout_mfc1, 1299 &exynos4_clk_mout_mfc1,
1300}; 1300};
1301 1301
1302static struct clk *clk_cdev[] = { 1302static struct clk *exynos4_clk_cdev[] = {
1303 &clk_pdma0, 1303 &exynos4_clk_pdma0,
1304 &clk_pdma1, 1304 &exynos4_clk_pdma1,
1305}; 1305};
1306 1306
1307static struct clksrc_clk *clksrc_cdev[] = { 1307static struct clksrc_clk *exynos4_clksrc_cdev[] = {
1308 &clk_sclk_uart0, 1308 &exynos4_clk_sclk_uart0,
1309 &clk_sclk_uart1, 1309 &exynos4_clk_sclk_uart1,
1310 &clk_sclk_uart2, 1310 &exynos4_clk_sclk_uart2,
1311 &clk_sclk_uart3, 1311 &exynos4_clk_sclk_uart3,
1312 &clk_sclk_mmc0, 1312 &exynos4_clk_sclk_mmc0,
1313 &clk_sclk_mmc1, 1313 &exynos4_clk_sclk_mmc1,
1314 &clk_sclk_mmc2, 1314 &exynos4_clk_sclk_mmc2,
1315 &clk_sclk_mmc3, 1315 &exynos4_clk_sclk_mmc3,
1316 &clk_sclk_spi0, 1316 &exynos4_clk_sclk_spi0,
1317 &clk_sclk_spi1, 1317 &exynos4_clk_sclk_spi1,
1318 &clk_sclk_spi2, 1318 &exynos4_clk_sclk_spi2,
1319 1319
1320}; 1320};
1321 1321
1322static struct clk_lookup exynos4_clk_lookup[] = { 1322static struct clk_lookup exynos4_clk_lookup[] = {
1323 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &clk_sclk_uart0.clk), 1323 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
1324 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk), 1324 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
1325 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk), 1325 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
1326 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk), 1326 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
1327 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), 1327 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
1328 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), 1328 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
1329 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), 1329 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
1330 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), 1330 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
1331 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0), 1331 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
1332 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1), 1332 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
1333 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &clk_sclk_spi0.clk), 1333 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
1334 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &clk_sclk_spi1.clk), 1334 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
1335 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &clk_sclk_spi2.clk), 1335 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
1336}; 1336};
1337 1337
1338static int xtal_rate; 1338static int xtal_rate;
@@ -1340,10 +1340,10 @@ static int xtal_rate;
1340static unsigned long exynos4_fout_apll_get_rate(struct clk *clk) 1340static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1341{ 1341{
1342 if (soc_is_exynos4210()) 1342 if (soc_is_exynos4210())
1343 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), 1343 return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
1344 pll_4508); 1344 pll_4508);
1345 else if (soc_is_exynos4212() || soc_is_exynos4412()) 1345 else if (soc_is_exynos4212() || soc_is_exynos4412())
1346 return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0)); 1346 return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
1347 else 1347 else
1348 return 0; 1348 return 0;
1349} 1349}
@@ -1352,7 +1352,7 @@ static struct clk_ops exynos4_fout_apll_ops = {
1352 .get_rate = exynos4_fout_apll_get_rate, 1352 .get_rate = exynos4_fout_apll_get_rate,
1353}; 1353};
1354 1354
1355static u32 vpll_div[][8] = { 1355static u32 exynos4_vpll_div[][8] = {
1356 { 54000000, 3, 53, 3, 1024, 0, 17, 0 }, 1356 { 54000000, 3, 53, 3, 1024, 0, 17, 0 },
1357 { 108000000, 3, 53, 2, 1024, 0, 17, 0 }, 1357 { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1358}; 1358};
@@ -1371,41 +1371,41 @@ static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1371 if (clk->rate == rate) 1371 if (clk->rate == rate)
1372 return 0; 1372 return 0;
1373 1373
1374 vpll_con0 = __raw_readl(S5P_VPLL_CON0); 1374 vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
1375 vpll_con0 &= ~(0x1 << 27 | \ 1375 vpll_con0 &= ~(0x1 << 27 | \
1376 PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \ 1376 PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1377 PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \ 1377 PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1378 PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); 1378 PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1379 1379
1380 vpll_con1 = __raw_readl(S5P_VPLL_CON1); 1380 vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
1381 vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \ 1381 vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \
1382 PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \ 1382 PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1383 PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT); 1383 PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1384 1384
1385 for (i = 0; i < ARRAY_SIZE(vpll_div); i++) { 1385 for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
1386 if (vpll_div[i][0] == rate) { 1386 if (exynos4_vpll_div[i][0] == rate) {
1387 vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT; 1387 vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1388 vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT; 1388 vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1389 vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT; 1389 vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1390 vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT; 1390 vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1391 vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT; 1391 vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1392 vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT; 1392 vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1393 vpll_con0 |= vpll_div[i][7] << 27; 1393 vpll_con0 |= exynos4_vpll_div[i][7] << 27;
1394 break; 1394 break;
1395 } 1395 }
1396 } 1396 }
1397 1397
1398 if (i == ARRAY_SIZE(vpll_div)) { 1398 if (i == ARRAY_SIZE(exynos4_vpll_div)) {
1399 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n", 1399 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1400 __func__); 1400 __func__);
1401 return -EINVAL; 1401 return -EINVAL;
1402 } 1402 }
1403 1403
1404 __raw_writel(vpll_con0, S5P_VPLL_CON0); 1404 __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
1405 __raw_writel(vpll_con1, S5P_VPLL_CON1); 1405 __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
1406 1406
1407 /* Wait for VPLL lock */ 1407 /* Wait for VPLL lock */
1408 while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT))) 1408 while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1409 continue; 1409 continue;
1410 1410
1411 clk->rate = rate; 1411 clk->rate = rate;
@@ -1448,25 +1448,25 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
1448 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); 1448 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1449 1449
1450 if (soc_is_exynos4210()) { 1450 if (soc_is_exynos4210()) {
1451 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), 1451 apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
1452 pll_4508); 1452 pll_4508);
1453 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), 1453 mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
1454 pll_4508); 1454 pll_4508);
1455 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0), 1455 epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1456 __raw_readl(S5P_EPLL_CON1), pll_4600); 1456 __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
1457 1457
1458 vpllsrc = clk_get_rate(&clk_vpllsrc.clk); 1458 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1459 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), 1459 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1460 __raw_readl(S5P_VPLL_CON1), pll_4650c); 1460 __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
1461 } else if (soc_is_exynos4212() || soc_is_exynos4412()) { 1461 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1462 apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0)); 1462 apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
1463 mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0)); 1463 mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
1464 epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0), 1464 epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1465 __raw_readl(S5P_EPLL_CON1)); 1465 __raw_readl(EXYNOS4_EPLL_CON1));
1466 1466
1467 vpllsrc = clk_get_rate(&clk_vpllsrc.clk); 1467 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1468 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), 1468 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1469 __raw_readl(S5P_VPLL_CON1)); 1469 __raw_readl(EXYNOS4_VPLL_CON1));
1470 } else { 1470 } else {
1471 /* nothing */ 1471 /* nothing */
1472 } 1472 }
@@ -1480,13 +1480,13 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
1480 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", 1480 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1481 apll, mpll, epll, vpll); 1481 apll, mpll, epll, vpll);
1482 1482
1483 armclk = clk_get_rate(&clk_armclk.clk); 1483 armclk = clk_get_rate(&exynos4_clk_armclk.clk);
1484 sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk); 1484 sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
1485 1485
1486 aclk_200 = clk_get_rate(&clk_aclk_200.clk); 1486 aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
1487 aclk_100 = clk_get_rate(&clk_aclk_100.clk); 1487 aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
1488 aclk_160 = clk_get_rate(&clk_aclk_160.clk); 1488 aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
1489 aclk_133 = clk_get_rate(&clk_aclk_133.clk); 1489 aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
1490 1490
1491 printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n" 1491 printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1492 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n", 1492 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
@@ -1497,15 +1497,15 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
1497 clk_h.rate = sclk_dmc; 1497 clk_h.rate = sclk_dmc;
1498 clk_p.rate = aclk_100; 1498 clk_p.rate = aclk_100;
1499 1499
1500 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) 1500 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
1501 s3c_set_clksrc(&clksrcs[ptr], true); 1501 s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
1502} 1502}
1503 1503
1504static struct clk *clks[] __initdata = { 1504static struct clk *exynos4_clks[] __initdata = {
1505 &clk_sclk_hdmi27m, 1505 &exynos4_clk_sclk_hdmi27m,
1506 &clk_sclk_hdmiphy, 1506 &exynos4_clk_sclk_hdmiphy,
1507 &clk_sclk_usbphy0, 1507 &exynos4_clk_sclk_usbphy0,
1508 &clk_sclk_usbphy1, 1508 &exynos4_clk_sclk_usbphy1,
1509}; 1509};
1510 1510
1511#ifdef CONFIG_PM_SLEEP 1511#ifdef CONFIG_PM_SLEEP
@@ -1534,26 +1534,26 @@ void __init exynos4_register_clocks(void)
1534{ 1534{
1535 int ptr; 1535 int ptr;
1536 1536
1537 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); 1537 s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
1538 1538
1539 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) 1539 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
1540 s3c_register_clksrc(sysclks[ptr], 1); 1540 s3c_register_clksrc(exynos4_sysclks[ptr], 1);
1541 1541
1542 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++) 1542 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
1543 s3c_register_clksrc(sclk_tv[ptr], 1); 1543 s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
1544 1544
1545 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++) 1545 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
1546 s3c_register_clksrc(clksrc_cdev[ptr], 1); 1546 s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
1547 1547
1548 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 1548 s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
1549 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 1549 s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
1550 1550
1551 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev)); 1551 s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
1552 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++) 1552 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
1553 s3c_disable_clocks(clk_cdev[ptr], 1); 1553 s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
1554 1554
1555 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1555 s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1556 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1556 s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1557 clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup)); 1557 clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1558 1558
1559 register_syscore_ops(&exynos4_clock_syscore_ops); 1559 register_syscore_ops(&exynos4_clock_syscore_ops);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-17 04:38:58 -0400