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authorAndrew Lunn <andrew@lunn.ch>2012-05-14 05:28:43 -0400
committerAndrew Lunn <andrew@lunn.ch>2012-05-14 12:13:15 -0400
commitca2ac5cc9548e954b295de16158a5a7e3b97873b (patch)
tree6b04754efe124761ac5a126c3d898923d4fa25c7 /arch/arm/mach-dove
parent4d72cef17bb71a63526b6219bc06b7f31d86dde1 (diff)
Dove: Fix Section mismatch warnings
Add missing __init markups to GPIO and timer functions. Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Diffstat (limited to 'arch/arm/mach-dove')
-rw-r--r--arch/arm/mach-dove/common.c2
-rw-r--r--arch/arm/mach-dove/mpp.c8
2 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index bda7aca04ca0..42ab1e7c4ecc 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -181,7 +181,7 @@ static int get_tclk(void)
181 return 166666667; 181 return 166666667;
182} 182}
183 183
184static void dove_timer_init(void) 184static void __init dove_timer_init(void)
185{ 185{
186 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, 186 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
187 IRQ_DOVE_BRIDGE, get_tclk()); 187 IRQ_DOVE_BRIDGE, get_tclk());
diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c
index 51e0e411c9cb..7f70afc26f91 100644
--- a/arch/arm/mach-dove/mpp.c
+++ b/arch/arm/mach-dove/mpp.c
@@ -56,7 +56,7 @@ static void dove_mpp_gpio_mode(int start, int end, int gpio_mode)
56 56
57/* Dump all the extra MPP registers. The platform code will dump the 57/* Dump all the extra MPP registers. The platform code will dump the
58 registers for pins 0-23. */ 58 registers for pins 0-23. */
59static void dove_mpp_dump_regs(void) 59static void __init dove_mpp_dump_regs(void)
60{ 60{
61 pr_debug("PMU_CTRL4_CTRL: %08x\n", 61 pr_debug("PMU_CTRL4_CTRL: %08x\n",
62 readl(DOVE_MPP_CTRL4_VIRT_BASE)); 62 readl(DOVE_MPP_CTRL4_VIRT_BASE));
@@ -67,7 +67,7 @@ static void dove_mpp_dump_regs(void)
67 pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE)); 67 pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE));
68} 68}
69 69
70static void dove_mpp_cfg_nfc(int sel) 70static void __init dove_mpp_cfg_nfc(int sel)
71{ 71{
72 u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE); 72 u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE);
73 73
@@ -78,7 +78,7 @@ static void dove_mpp_cfg_nfc(int sel)
78 dove_mpp_gpio_mode(64, 71, GPIO_OUTPUT_OK); 78 dove_mpp_gpio_mode(64, 71, GPIO_OUTPUT_OK);
79} 79}
80 80
81static void dove_mpp_cfg_au1(int sel) 81static void __init dove_mpp_cfg_au1(int sel)
82{ 82{
83 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 83 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
84 u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1); 84 u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1);
@@ -118,7 +118,7 @@ static void dove_mpp_cfg_au1(int sel)
118 118
119/* Configure the group registers, enabling GPIO if sel indicates the 119/* Configure the group registers, enabling GPIO if sel indicates the
120 pin is to be used for GPIO */ 120 pin is to be used for GPIO */
121static void dove_mpp_conf_grp(unsigned int *mpp_grp_list) 121static void __init dove_mpp_conf_grp(unsigned int *mpp_grp_list)
122{ 122{
123 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 123 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
124 int gpio_mode; 124 int gpio_mode;