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authorMark Brown <broonie@opensource.wolfsonmicro.com>2012-12-15 09:56:43 -0500
committerMark Brown <broonie@opensource.wolfsonmicro.com>2012-12-15 09:56:43 -0500
commit326b06a8a9b09d6d9a276fd550b6b6bb138e9a47 (patch)
treeb9bdcb0bd635b91258cec09c981af2c5dcc0f683 /arch/arm/mach-dove/irq.c
parent92b2e81d6f95bcee386abac4c4389f5b950f7bb9 (diff)
parent9bffb1fb7c22c96d51d4ba06e2e023dd568a5872 (diff)
Merge remote-tracking branch 'asoc/topic/core' into asoc-next
Diffstat (limited to 'arch/arm/mach-dove/irq.c')
-rw-r--r--arch/arm/mach-dove/irq.c14
1 files changed, 13 insertions, 1 deletions
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
index 087711524e8a..bc4344aa1009 100644
--- a/arch/arm/mach-dove/irq.c
+++ b/arch/arm/mach-dove/irq.c
@@ -46,8 +46,20 @@ static void pmu_irq_ack(struct irq_data *d)
46 int pin = irq_to_pmu(d->irq); 46 int pin = irq_to_pmu(d->irq);
47 u32 u; 47 u32 u;
48 48
49 /*
50 * The PMU mask register is not RW0C: it is RW. This means that
51 * the bits take whatever value is written to them; if you write
52 * a '1', you will set the interrupt.
53 *
54 * Unfortunately this means there is NO race free way to clear
55 * these interrupts.
56 *
57 * So, let's structure the code so that the window is as small as
58 * possible.
59 */
49 u = ~(1 << (pin & 31)); 60 u = ~(1 << (pin & 31));
50 writel(u, PMU_INTERRUPT_CAUSE); 61 u &= readl_relaxed(PMU_INTERRUPT_CAUSE);
62 writel_relaxed(u, PMU_INTERRUPT_CAUSE);
51} 63}
52 64
53static struct irq_chip pmu_irq_chip = { 65static struct irq_chip pmu_irq_chip = {