Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6

Conflicts:
	drivers/scsi/fcoe/fcoe.c

33 files changed, 3561 insertions, 509 deletions

diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index bac988e7a4c3..a9c78bc72b84 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -4,19 +4,56 @@ menu "TI DaVinci Implementations"
 
 comment "DaVinci Core Type"
 
-config ARCH_DAVINCI644x
-        default y
+config ARCH_DAVINCI_DM644x
         bool "DaVinci 644x based system"
 
 comment "DaVinci Board Type"
 
 config MACH_DAVINCI_EVM
-        bool "TI DaVinci EVM"
+        bool "TI DM644x EVM"
         default y
-        depends on ARCH_DAVINCI644x
+        depends on ARCH_DAVINCI_DM644x
         help
           Configure this option to specify the whether the board used
-          for development is a DaVinci EVM
+          for development is a DM644x EVM
+
+
+config DAVINCI_MUX
+        bool "DAVINCI multiplexing support"
+        depends on ARCH_DAVINCI
+        default y
+        help
+          Pin multiplexing support for DAVINCI boards. If your bootloader
+          sets the multiplexing correctly, say N. Otherwise, or if unsure,
+          say Y.
+
+config DAVINCI_MUX_DEBUG
+        bool "Multiplexing debug output"
+        depends on DAVINCI_MUX
+        help
+          Makes the multiplexing functions print out a lot of debug info.
+          This is useful if you want to find out the correct values of the
+          multiplexing registers.
+
+config DAVINCI_MUX_WARNINGS
+        bool "Warn about pins the bootloader didn't set up"
+        depends on DAVINCI_MUX
+        help
+          Choose Y here to warn whenever driver initialization logic needs
+          to change the pin multiplexing setup.  When there are no warnings
+          printed, it's safe to deselect DAVINCI_MUX for your product.
+
+config DAVINCI_RESET_CLOCKS
+        bool "Reset unused clocks during boot"
+        depends on ARCH_DAVINCI
+        help
+          Say Y if you want to reset unused clocks during boot.
+          This option saves power, but assumes all drivers are
+          using the clock framework. Broken drivers that do not
+          yet use clock framework may not work with this option.
+          If you are booting from another operating system, you
+          probably do not want this option enabled until your
+          device drivers work properly.
 
 endmenu
 
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 4dc458597f40..1674661942f3 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -5,7 +5,12 @@
 
 # Common objects
 obj-y                   := time.o irq.o clock.o serial.o io.o id.o psc.o \
-                           gpio.o mux.o devices.o usb.o
+                           gpio.o devices.o dma.o usb.o
+
+obj-$(CONFIG_DAVINCI_MUX)               += mux.o
+
+# Chip specific
+obj-$(CONFIG_ARCH_DAVINCI_DM644x)       += dm644x.o
 
 # Board specific
-obj-$(CONFIG_MACH_DAVINCI_EVM)  += board-evm.o
+obj-$(CONFIG_MACH_DAVINCI_EVM)          += board-dm644x-evm.o
diff --git a/arch/arm/mach-davinci/board-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 0b97a528902b..b2e7f9c63bc5 100644
--- a/arch/arm/mach-davinci/board-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -15,15 +15,20 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
+#include <linux/memory.h>
+#include <linux/etherdevice.h>
 
 #include <linux/i2c.h>
 #include <linux/i2c/pcf857x.h>
 #include <linux/i2c/at24.h>
 
 #include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
 #include <linux/io.h>
+#include <linux/phy.h>
+#include <linux/clk.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -32,25 +37,34 @@
 #include <asm/mach/map.h>
 #include <asm/mach/flash.h>
 
-#include <mach/hardware.h>
+#include <mach/dm644x.h>
 #include <mach/common.h>
 #include <mach/i2c.h>
+#include <mach/serial.h>
+#include <mach/mux.h>
+#include <mach/psc.h>
+#include <mach/nand.h>
 
-/* other misc. init functions */
-void __init davinci_psc_init(void);
-void __init davinci_irq_init(void);
-void __init davinci_map_common_io(void);
-void __init davinci_init_common_hw(void);
+#define DM644X_EVM_PHY_MASK             (0x2)
+#define DM644X_EVM_MDIO_FREQUENCY       (2200000) /* PHY bus frequency */
 
-#if defined(CONFIG_MTD_PHYSMAP) || \
-    defined(CONFIG_MTD_PHYSMAP_MODULE)
+#define DAVINCI_CFC_ATA_BASE              0x01C66000
+
+#define DAVINCI_ASYNC_EMIF_CONTROL_BASE   0x01e00000
+#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE  0x02000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE  0x04000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE  0x06000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE  0x08000000
+
+#define LXT971_PHY_ID   (0x001378e2)
+#define LXT971_PHY_MASK (0xfffffff0)
 
 static struct mtd_partition davinci_evm_norflash_partitions[] = {
-        /* bootloader (U-Boot, etc) in first 4 sectors */
+        /* bootloader (UBL, U-Boot, etc) in first 5 sectors */
         {
                 .name           = "bootloader",
                 .offset         = 0,
-                .size           = 4 * SZ_64K,
+                .size           = 5 * SZ_64K,
                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
         },
         /* bootloader params in the next 1 sectors */
@@ -100,10 +114,89 @@ static struct platform_device davinci_evm_norflash_device = {
         .resource       = &davinci_evm_norflash_resource,
 };
 
-#endif
+/* DM644x EVM includes a 64 MByte small-page NAND flash (16K blocks).
+ * It may used instead of the (default) NOR chip to boot, using TI's
+ * tools to install the secondary boot loader (UBL) and U-Boot.
+ */
+struct mtd_partition davinci_evm_nandflash_partition[] = {
+        /* Bootloader layout depends on whose u-boot is installed, but we
+         * can hide all the details.
+         *  - block 0 for u-boot environment ... in mainline u-boot
+         *  - block 1 for UBL (plus up to four backup copies in blocks 2..5)
+         *  - blocks 6...? for u-boot
+         *  - blocks 16..23 for u-boot environment ... in TI's u-boot
+         */
+        {
+                .name           = "bootloader",
+                .offset         = 0,
+                .size           = SZ_256K + SZ_128K,
+                .mask_flags     = MTD_WRITEABLE,        /* force read-only */
+        },
+        /* Kernel */
+        {
+                .name           = "kernel",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_4M,
+                .mask_flags     = 0,
+        },
+        /* File system (older GIT kernels started this on the 5MB mark) */
+        {
+                .name           = "filesystem",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+                .mask_flags     = 0,
+        }
+        /* A few blocks at end hold a flash BBT ... created by TI's CCS
+         * using flashwriter_nand.out, but ignored by TI's versions of
+         * Linux and u-boot.  We boot faster by using them.
+         */
+};
 
-#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
-    defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
+static struct davinci_nand_pdata davinci_evm_nandflash_data = {
+        .parts          = davinci_evm_nandflash_partition,
+        .nr_parts       = ARRAY_SIZE(davinci_evm_nandflash_partition),
+        .ecc_mode       = NAND_ECC_HW,
+        .options        = NAND_USE_FLASH_BBT,
+};
+
+static struct resource davinci_evm_nandflash_resource[] = {
+        {
+                .start          = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
+                .end            = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
+                .end            = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device davinci_evm_nandflash_device = {
+        .name           = "davinci_nand",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &davinci_evm_nandflash_data,
+        },
+        .num_resources  = ARRAY_SIZE(davinci_evm_nandflash_resource),
+        .resource       = davinci_evm_nandflash_resource,
+};
+
+static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
+
+static struct platform_device davinci_fb_device = {
+        .name           = "davincifb",
+        .id             = -1,
+        .dev = {
+                .dma_mask               = &davinci_fb_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .num_resources = 0,
+};
+
+static struct platform_device rtc_dev = {
+        .name           = "rtc_davinci_evm",
+        .id             = -1,
+};
 
 static struct resource ide_resources[] = {
         {
@@ -131,8 +224,6 @@ static struct platform_device ide_dev = {
         },
 };
 
-#endif
-
 /*----------------------------------------------------------------------*/
 
 /*
@@ -311,7 +402,9 @@ evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
         gpio_request(gpio + 7, "nCF_SEL");
         gpio_direction_output(gpio + 7, 1);
 
-        /* irlml6401 sustains over 3A, switches 5V in under 8 msec */
+        /* irlml6401 switches over 1A, in under 8 msec;
+         * now it can be managed by nDRV_VBUS ...
+         */
         setup_usb(500, 8);
 
         return 0;
@@ -343,14 +436,120 @@ static struct pcf857x_platform_data pcf_data_u35 = {
  *  - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL)
  *  - ... newer boards may have more
  */
+static struct memory_accessor *at24_mem_acc;
+
+static void at24_setup(struct memory_accessor *mem_acc, void *context)
+{
+        DECLARE_MAC_BUF(mac_str);
+        char mac_addr[6];
+
+        at24_mem_acc = mem_acc;
+
+        /* Read MAC addr from EEPROM */
+        if (at24_mem_acc->read(at24_mem_acc, mac_addr, 0x7f00, 6) == 6) {
+                printk(KERN_INFO "Read MAC addr from EEPROM: %s\n",
+                       print_mac(mac_str, mac_addr));
+        }
+}
+
 static struct at24_platform_data eeprom_info = {
         .byte_len       = (256*1024) / 8,
         .page_size      = 64,
         .flags          = AT24_FLAG_ADDR16,
+        .setup          = at24_setup,
 };
 
+int dm6446evm_eeprom_read(void *buf, off_t off, size_t count)
+{
+        if (at24_mem_acc)
+                return at24_mem_acc->read(at24_mem_acc, buf, off, count);
+        return -ENODEV;
+}
+EXPORT_SYMBOL(dm6446evm_eeprom_read);
+
+int dm6446evm_eeprom_write(void *buf, off_t off, size_t count)
+{
+        if (at24_mem_acc)
+                return at24_mem_acc->write(at24_mem_acc, buf, off, count);
+        return -ENODEV;
+}
+EXPORT_SYMBOL(dm6446evm_eeprom_write);
+
+/*
+ * MSP430 supports RTC, card detection, input from IR remote, and
+ * a bit more.  It triggers interrupts on GPIO(7) from pressing
+ * buttons on the IR remote, and for card detect switches.
+ */
+static struct i2c_client *dm6446evm_msp;
+
+static int dm6446evm_msp_probe(struct i2c_client *client,
+                const struct i2c_device_id *id)
+{
+        dm6446evm_msp = client;
+        return 0;
+}
+
+static int dm6446evm_msp_remove(struct i2c_client *client)
+{
+        dm6446evm_msp = NULL;
+        return 0;
+}
+
+static const struct i2c_device_id dm6446evm_msp_ids[] = {
+        { "dm6446evm_msp", 0, },
+        { /* end of list */ },
+};
+
+static struct i2c_driver dm6446evm_msp_driver = {
+        .driver.name    = "dm6446evm_msp",
+        .id_table       = dm6446evm_msp_ids,
+        .probe          = dm6446evm_msp_probe,
+        .remove         = dm6446evm_msp_remove,
+};
+
+static int dm6444evm_msp430_get_pins(void)
+{
+        static const char txbuf[2] = { 2, 4, };
+        char buf[4];
+        struct i2c_msg msg[2] = {
+                {
+                        .addr = dm6446evm_msp->addr,
+                        .flags = 0,
+                        .len = 2,
+                        .buf = (void __force *)txbuf,
+                },
+                {
+                        .addr = dm6446evm_msp->addr,
+                        .flags = I2C_M_RD,
+                        .len = 4,
+                        .buf = buf,
+                },
+        };
+        int status;
+
+        if (!dm6446evm_msp)
+                return -ENXIO;
+
+        /* Command 4 == get input state, returns port 2 and port3 data
+         *   S Addr W [A] len=2 [A] cmd=4 [A]
+         *   RS Addr R [A] [len=4] A [cmd=4] A [port2] A [port3] N P
+         */
+        status = i2c_transfer(dm6446evm_msp->adapter, msg, 2);
+        if (status < 0)
+                return status;
+
+        dev_dbg(&dm6446evm_msp->dev,
+                "PINS: %02x %02x %02x %02x\n",
+                buf[0], buf[1], buf[2], buf[3]);
+
+        return (buf[3] << 8) | buf[2];
+}
+
 static struct i2c_board_info __initdata i2c_info[] =  {
         {
+                I2C_BOARD_INFO("dm6446evm_msp", 0x23),
+        },
+        {
                 I2C_BOARD_INFO("pcf8574", 0x38),
                 .platform_data  = &pcf_data_u2,
         },
@@ -368,7 +567,6 @@ static struct i2c_board_info __initdata i2c_info[] =  {
         },
         /* ALSO:
          * - tvl320aic33 audio codec (0x1b)
-         * - msp430 microcontroller (0x23)
          * - tvp5146 video decoder (0x5d)
          */
 };
@@ -384,51 +582,109 @@ static struct davinci_i2c_platform_data i2c_pdata = {
 static void __init evm_init_i2c(void)
 {
         davinci_init_i2c(&i2c_pdata);
+        i2c_add_driver(&dm6446evm_msp_driver);
         i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
 }
 
 static struct platform_device *davinci_evm_devices[] __initdata = {
-#if defined(CONFIG_MTD_PHYSMAP) || \
-    defined(CONFIG_MTD_PHYSMAP_MODULE)
-        &davinci_evm_norflash_device,
-#endif
-#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
-    defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
-        &ide_dev,
-#endif
+        &davinci_fb_device,
+        &rtc_dev,
+};
+
+static struct davinci_uart_config uart_config __initdata = {
+        .enabled_uarts = (1 << 0),
 };
 
 static void __init
 davinci_evm_map_io(void)
 {
         davinci_map_common_io();
+        dm644x_init();
 }
 
-static __init void davinci_evm_init(void)
+static int davinci_phy_fixup(struct phy_device *phydev)
 {
-        davinci_psc_init();
+        unsigned int control;
+        /* CRITICAL: Fix for increasing PHY signal drive strength for
+         * TX lockup issue. On DaVinci EVM, the Intel LXT971 PHY
+         * signal strength was low causing  TX to fail randomly. The
+         * fix is to Set bit 11 (Increased MII drive strength) of PHY
+         * register 26 (Digital Config register) on this phy. */
+        control = phy_read(phydev, 26);
+        phy_write(phydev, 26, (control | 0x800));
+        return 0;
+}
 
 #if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
     defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
+#define HAS_ATA 1
+#else
+#define HAS_ATA 0
+#endif
+
 #if defined(CONFIG_MTD_PHYSMAP) || \
     defined(CONFIG_MTD_PHYSMAP_MODULE)
-        printk(KERN_WARNING "WARNING: both IDE and NOR flash are enabled, "
-               "but share pins.\n\t Disable IDE for NOR support.\n");
+#define HAS_NOR 1
+#else
+#define HAS_NOR 0
 #endif
+
+#if defined(CONFIG_MTD_NAND_DAVINCI) || \
+    defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
+#define HAS_NAND 1
+#else
+#define HAS_NAND 0
 #endif
 
+static __init void davinci_evm_init(void)
+{
+        struct clk *aemif_clk;
+
+        aemif_clk = clk_get(NULL, "aemif");
+        clk_enable(aemif_clk);
+
+        if (HAS_ATA) {
+                if (HAS_NAND || HAS_NOR)
+                        pr_warning("WARNING: both IDE and Flash are "
+                                "enabled, but they share AEMIF pins.\n"
+                                "\tDisable IDE for NAND/NOR support.\n");
+                davinci_cfg_reg(DM644X_HPIEN_DISABLE);
+                davinci_cfg_reg(DM644X_ATAEN);
+                davinci_cfg_reg(DM644X_HDIREN);
+                platform_device_register(&ide_dev);
+        } else if (HAS_NAND || HAS_NOR) {
+                davinci_cfg_reg(DM644X_HPIEN_DISABLE);
+                davinci_cfg_reg(DM644X_ATAEN_DISABLE);
+
+                /* only one device will be jumpered and detected */
+                if (HAS_NAND) {
+                        platform_device_register(&davinci_evm_nandflash_device);
+                        evm_leds[7].default_trigger = "nand-disk";
+                        if (HAS_NOR)
+                                pr_warning("WARNING: both NAND and NOR flash "
+                                        "are enabled; disable one of them.\n");
+                } else if (HAS_NOR)
+                        platform_device_register(&davinci_evm_norflash_device);
+        }
+
         platform_add_devices(davinci_evm_devices,
                              ARRAY_SIZE(davinci_evm_devices));
         evm_init_i2c();
+
+        davinci_serial_init(&uart_config);
+
+        /* Register the fixup for PHY on DaVinci */
+        phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
+                                        davinci_phy_fixup);
+
 }
 
 static __init void davinci_evm_irq_init(void)
 {
-        davinci_init_common_hw();
         davinci_irq_init();
 }
 
-MACHINE_START(DAVINCI_EVM, "DaVinci EVM")
+MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
         /* Maintainer: MontaVista Software <source@mvista.com> */
         .phys_io      = IO_PHYS,
         .io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index abb92b7eca0c..f0baaa15a57e 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -1,7 +1,8 @@
 /*
- * TI DaVinci clock config file
+ * Clock and PLL control for DaVinci devices
  *
- * Copyright (C) 2006 Texas Instruments.
+ * Copyright (C) 2006-2007 Texas Instruments.
+ * Copyright (C) 2008-2009 Deep Root Systems, LLC
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -13,6 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/errno.h>
+#include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/mutex.h>
 #include <linux/platform_device.h>
@@ -21,98 +23,50 @@
 #include <mach/hardware.h>
 
 #include <mach/psc.h>
+#include <mach/cputype.h>
 #include "clock.h"
 
-/* PLL/Reset register offsets */
-#define PLLM            0x110
-
 static LIST_HEAD(clocks);
 static DEFINE_MUTEX(clocks_mutex);
 static DEFINE_SPINLOCK(clockfw_lock);
 
-static unsigned int commonrate;
-static unsigned int armrate;
-static unsigned int fixedrate = 27000000;       /* 27 MHZ */
-
-extern void davinci_psc_config(unsigned int domain, unsigned int id, char enable);
-
-/*
- * Returns a clock. Note that we first try to use device id on the bus
- * and clock name. If this fails, we try to use clock name only.
- */
-struct clk *clk_get(struct device *dev, const char *id)
+static unsigned psc_domain(struct clk *clk)
 {
-        struct clk *p, *clk = ERR_PTR(-ENOENT);
-        int idno;
-
-        if (dev == NULL || dev->bus != &platform_bus_type)
-                idno = -1;
-        else
-                idno = to_platform_device(dev)->id;
-
-        mutex_lock(&clocks_mutex);
-
-        list_for_each_entry(p, &clocks, node) {
-                if (p->id == idno &&
-                    strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
-                        clk = p;
-                        goto found;
-                }
-        }
-
-        list_for_each_entry(p, &clocks, node) {
-                if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
-                        clk = p;
-                        break;
-                }
-        }
-
-found:
-        mutex_unlock(&clocks_mutex);
-
-        return clk;
+        return (clk->flags & PSC_DSP)
+                ? DAVINCI_GPSC_DSPDOMAIN
+                : DAVINCI_GPSC_ARMDOMAIN;
 }
-EXPORT_SYMBOL(clk_get);
 
-void clk_put(struct clk *clk)
+static void __clk_enable(struct clk *clk)
 {
-        if (clk && !IS_ERR(clk))
-                module_put(clk->owner);
-}
-EXPORT_SYMBOL(clk_put);
-
-static int __clk_enable(struct clk *clk)
-{
-        if (clk->flags & ALWAYS_ENABLED)
-                return 0;
-
-        davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, clk->lpsc, 1);
-        return 0;
+        if (clk->parent)
+                __clk_enable(clk->parent);
+        if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
+                davinci_psc_config(psc_domain(clk), clk->lpsc, 1);
 }
 
 static void __clk_disable(struct clk *clk)
 {
-        if (clk->usecount)
+        if (WARN_ON(clk->usecount == 0))
                 return;
-
-        davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, clk->lpsc, 0);
+        if (--clk->usecount == 0 && !(clk->flags & CLK_PLL))
+                davinci_psc_config(psc_domain(clk), clk->lpsc, 0);
+        if (clk->parent)
+                __clk_disable(clk->parent);
 }
 
 int clk_enable(struct clk *clk)
 {
         unsigned long flags;
-        int ret = 0;
 
         if (clk == NULL || IS_ERR(clk))
                 return -EINVAL;
 
-        if (clk->usecount++ == 0) {
-                spin_lock_irqsave(&clockfw_lock, flags);
-                ret = __clk_enable(clk);
-                spin_unlock_irqrestore(&clockfw_lock, flags);
-        }
+        spin_lock_irqsave(&clockfw_lock, flags);
+        __clk_enable(clk);
+        spin_unlock_irqrestore(&clockfw_lock, flags);
 
-        return ret;
+        return 0;
 }
 EXPORT_SYMBOL(clk_enable);
 
@@ -123,11 +77,9 @@ void clk_disable(struct clk *clk)
         if (clk == NULL || IS_ERR(clk))
                 return;
 
-        if (clk->usecount > 0 && !(--clk->usecount)) {
-                spin_lock_irqsave(&clockfw_lock, flags);
-                __clk_disable(clk);
-                spin_unlock_irqrestore(&clockfw_lock, flags);
-        }
+        spin_lock_irqsave(&clockfw_lock, flags);
+        __clk_disable(clk);
+        spin_unlock_irqrestore(&clockfw_lock, flags);
 }
 EXPORT_SYMBOL(clk_disable);
 
@@ -136,7 +88,7 @@ unsigned long clk_get_rate(struct clk *clk)
         if (clk == NULL || IS_ERR(clk))
                 return -EINVAL;
 
-        return *(clk->rate);
+        return clk->rate;
 }
 EXPORT_SYMBOL(clk_get_rate);
 
@@ -145,7 +97,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
         if (clk == NULL || IS_ERR(clk))
                 return -EINVAL;
 
-        return *(clk->rate);
+        return clk->rate;
 }
 EXPORT_SYMBOL(clk_round_rate);
 
@@ -164,10 +116,23 @@ int clk_register(struct clk *clk)
         if (clk == NULL || IS_ERR(clk))
                 return -EINVAL;
 
+        if (WARN(clk->parent && !clk->parent->rate,
+                        "CLK: %s parent %s has no rate!\n",
+                        clk->name, clk->parent->name))
+                return -EINVAL;
+
         mutex_lock(&clocks_mutex);
-        list_add(&clk->node, &clocks);
+        list_add_tail(&clk->node, &clocks);
         mutex_unlock(&clocks_mutex);
 
+        /* If rate is already set, use it */
+        if (clk->rate)
+                return 0;
+
+        /* Otherwise, default to parent rate */
+        if (clk->parent)
+                clk->rate = clk->parent->rate;
+
         return 0;
 }
 EXPORT_SYMBOL(clk_register);
@@ -183,84 +148,150 @@ void clk_unregister(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_unregister);
 
-static struct clk davinci_clks[] = {
-        {
-                .name = "ARMCLK",
-                .rate = &armrate,
-                .lpsc = -1,
-                .flags = ALWAYS_ENABLED,
-        },
-        {
-                .name = "UART",
-                .rate = &fixedrate,
-                .lpsc = DAVINCI_LPSC_UART0,
-        },
-        {
-                .name = "EMACCLK",
-                .rate = &commonrate,
-                .lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
-        },
-        {
-                .name = "I2CCLK",
-                .rate = &fixedrate,
-                .lpsc = DAVINCI_LPSC_I2C,
-        },
-        {
-                .name = "IDECLK",
-                .rate = &commonrate,
-                .lpsc = DAVINCI_LPSC_ATA,
-        },
-        {
-                .name = "McBSPCLK",
-                .rate = &commonrate,
-                .lpsc = DAVINCI_LPSC_McBSP,
-        },
-        {
-                .name = "MMCSDCLK",
-                .rate = &commonrate,
-                .lpsc = DAVINCI_LPSC_MMC_SD,
-        },
-        {
-                .name = "SPICLK",
-                .rate = &commonrate,
-                .lpsc = DAVINCI_LPSC_SPI,
-        },
-        {
-                .name = "gpio",
-                .rate = &commonrate,
-                .lpsc = DAVINCI_LPSC_GPIO,
-        },
-        {
-                .name = "usb",
-                .rate = &commonrate,
-                .lpsc = DAVINCI_LPSC_USB,
-        },
-        {
-                .name = "AEMIFCLK",
-                .rate = &commonrate,
-                .lpsc = DAVINCI_LPSC_AEMIF,
-                .usecount = 1,
+#ifdef CONFIG_DAVINCI_RESET_CLOCKS
+/*
+ * Disable any unused clocks left on by the bootloader
+ */
+static int __init clk_disable_unused(void)
+{
+        struct clk *ck;
+
+        spin_lock_irq(&clockfw_lock);
+        list_for_each_entry(ck, &clocks, node) {
+                if (ck->usecount > 0)
+                        continue;
+                if (!(ck->flags & CLK_PSC))
+                        continue;
+
+                /* ignore if in Disabled or SwRstDisable states */
+                if (!davinci_psc_is_clk_active(ck->lpsc))
+                        continue;
+
+                pr_info("Clocks: disable unused %s\n", ck->name);
+                davinci_psc_config(psc_domain(ck), ck->lpsc, 0);
         }
-};
+        spin_unlock_irq(&clockfw_lock);
+
+        return 0;
+}
+late_initcall(clk_disable_unused);
+#endif
 
-int __init davinci_clk_init(void)
+static void clk_sysclk_recalc(struct clk *clk)
 {
-        struct clk *clkp;
-        int count = 0;
-        u32 pll_mult;
-
-        pll_mult = davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLM);
-        commonrate = ((pll_mult + 1) * 27000000) / 6;
-        armrate = ((pll_mult + 1) * 27000000) / 2;
-
-        for (clkp = davinci_clks; count < ARRAY_SIZE(davinci_clks);
-             count++, clkp++) {
-                clk_register(clkp);
-
-                /* Turn on clocks that have been enabled in the
-                 * table above */
-                if (clkp->usecount)
-                        clk_enable(clkp);
+        u32 v, plldiv;
+        struct pll_data *pll;
+
+        /* If this is the PLL base clock, no more calculations needed */
+        if (clk->pll_data)
+                return;
+
+        if (WARN_ON(!clk->parent))
+                return;
+
+        clk->rate = clk->parent->rate;
+
+        /* Otherwise, the parent must be a PLL */
+        if (WARN_ON(!clk->parent->pll_data))
+                return;
+
+        pll = clk->parent->pll_data;
+
+        /* If pre-PLL, source clock is before the multiplier and divider(s) */
+        if (clk->flags & PRE_PLL)
+                clk->rate = pll->input_rate;
+
+        if (!clk->div_reg)
+                return;
+
+        v = __raw_readl(pll->base + clk->div_reg);
+        if (v & PLLDIV_EN) {
+                plldiv = (v & PLLDIV_RATIO_MASK) + 1;
+                if (plldiv)
+                        clk->rate /= plldiv;
+        }
+}
+
+static void __init clk_pll_init(struct clk *clk)
+{
+        u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
+        u8 bypass;
+        struct pll_data *pll = clk->pll_data;
+
+        pll->base = IO_ADDRESS(pll->phys_base);
+        ctrl = __raw_readl(pll->base + PLLCTL);
+        clk->rate = pll->input_rate = clk->parent->rate;
+
+        if (ctrl & PLLCTL_PLLEN) {
+                bypass = 0;
+                mult = __raw_readl(pll->base + PLLM);
+                mult = (mult & PLLM_PLLM_MASK) + 1;
+        } else
+                bypass = 1;
+
+        if (pll->flags & PLL_HAS_PREDIV) {
+                prediv = __raw_readl(pll->base + PREDIV);
+                if (prediv & PLLDIV_EN)
+                        prediv = (prediv & PLLDIV_RATIO_MASK) + 1;
+                else
+                        prediv = 1;
+        }
+
+        /* pre-divider is fixed, but (some?) chips won't report that */
+        if (cpu_is_davinci_dm355() && pll->num == 1)
+                prediv = 8;
+
+        if (pll->flags & PLL_HAS_POSTDIV) {
+                postdiv = __raw_readl(pll->base + POSTDIV);
+                if (postdiv & PLLDIV_EN)
+                        postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1;
+                else
+                        postdiv = 1;
+        }
+
+        if (!bypass) {
+                clk->rate /= prediv;
+                clk->rate *= mult;
+                clk->rate /= postdiv;
+        }
+
+        pr_debug("PLL%d: input = %lu MHz [ ",
+                 pll->num, clk->parent->rate / 1000000);
+        if (bypass)
+                pr_debug("bypass ");
+        if (prediv > 1)
+                pr_debug("/ %d ", prediv);
+        if (mult > 1)
+                pr_debug("* %d ", mult);
+        if (postdiv > 1)
+                pr_debug("/ %d ", postdiv);
+        pr_debug("] --> %lu MHz output.\n", clk->rate / 1000000);
+}
+
+int __init davinci_clk_init(struct davinci_clk *clocks)
+  {
+        struct davinci_clk *c;
+        struct clk *clk;
+
+        for (c = clocks; c->lk.clk; c++) {
+                clk = c->lk.clk;
+
+                if (clk->pll_data)
+                        clk_pll_init(clk);
+
+                /* Calculate rates for PLL-derived clocks */
+                else if (clk->flags & CLK_PLL)
+                        clk_sysclk_recalc(clk);
+
+                if (clk->lpsc)
+                        clk->flags |= CLK_PSC;
+
+                clkdev_add(&c->lk);
+                clk_register(clk);
+
+                /* Turn on clocks that Linux doesn't otherwise manage */
+                if (clk->flags & ALWAYS_ENABLED)
+                        clk_enable(clk);
         }
 
         return 0;
@@ -285,12 +316,52 @@ static void davinci_ck_stop(struct seq_file *m, void *v)
 {
 }
 
-static int davinci_ck_show(struct seq_file *m, void *v)
+#define CLKNAME_MAX     10              /* longest clock name */
+#define NEST_DELTA      2
+#define NEST_MAX        4
+
+static void
+dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
 {
-        struct clk *cp;
+        char            *state;
+        char            buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
+        struct clk      *clk;
+        unsigned        i;
+
+        if (parent->flags & CLK_PLL)
+                state = "pll";
+        else if (parent->flags & CLK_PSC)
+                state = "psc";
+        else
+                state = "";
+
+        /* <nest spaces> name <pad to end> */
+        memset(buf, ' ', sizeof(buf) - 1);
+        buf[sizeof(buf) - 1] = 0;
+        i = strlen(parent->name);
+        memcpy(buf + nest, parent->name,
+                        min(i, (unsigned)(sizeof(buf) - 1 - nest)));
+
+        seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
+                   buf, parent->usecount, state, clk_get_rate(parent));
+        /* REVISIT show device associations too */
+
+        /* cost is now small, but not linear... */
+        list_for_each_entry(clk, &clocks, node) {
+                if (clk->parent == parent)
+                        dump_clock(s, nest + NEST_DELTA, clk);
+        }
+}
 
-        list_for_each_entry(cp, &clocks, node)
-                seq_printf(m,"%s %d %d\n", cp->name, *(cp->rate), cp->usecount);
+static int davinci_ck_show(struct seq_file *m, void *v)
+{
+        /* Show clock tree; we know the main oscillator is first.
+         * We trust nonzero usecounts equate to PSC enables...
+         */
+        mutex_lock(&clocks_mutex);
+        if (!list_empty(&clocks))
+                dump_clock(m, 0, list_first_entry(&clocks, struct clk, node));
+        mutex_unlock(&clocks_mutex);
 
         return 0;
 }
@@ -321,4 +392,4 @@ static int __init davinci_ck_proc_init(void)
 
 }
 __initcall(davinci_ck_proc_init);
-#endif  /* CONFIG_DEBUG_PROC_FS */
+#endif /* CONFIG_DEBUG_PROC_FS */
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index ed47079a52e4..35736ec202f8 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -1,7 +1,8 @@
 /*
  * TI DaVinci clock definitions
  *
- * Copyright (C) 2006 Texas Instruments.
+ * Copyright (C) 2006-2007 Texas Instruments.
+ * Copyright (C) 2008-2009 Deep Root Systems, LLC
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -11,23 +12,85 @@
 #ifndef __ARCH_ARM_DAVINCI_CLOCK_H
 #define __ARCH_ARM_DAVINCI_CLOCK_H
 
+#include <linux/list.h>
+#include <asm/clkdev.h>
+
+#define DAVINCI_PLL1_BASE 0x01c40800
+#define DAVINCI_PLL2_BASE 0x01c40c00
+#define MAX_PLL 2
+
+/* PLL/Reset register offsets */
+#define PLLCTL          0x100
+#define PLLCTL_PLLEN    BIT(0)
+#define PLLCTL_CLKMODE  BIT(8)
+
+#define PLLM            0x110
+#define PLLM_PLLM_MASK  0xff
+
+#define PREDIV          0x114
+#define PLLDIV1         0x118
+#define PLLDIV2         0x11c
+#define PLLDIV3         0x120
+#define POSTDIV         0x128
+#define BPDIV           0x12c
+#define PLLCMD          0x138
+#define PLLSTAT         0x13c
+#define PLLALNCTL       0x140
+#define PLLDCHANGE      0x144
+#define PLLCKEN         0x148
+#define PLLCKSTAT       0x14c
+#define PLLSYSTAT       0x150
+#define PLLDIV4         0x160
+#define PLLDIV5         0x164
+#define PLLDIV6         0x168
+#define PLLDIV7         0x16c
+#define PLLDIV8         0x170
+#define PLLDIV9         0x174
+#define PLLDIV_EN       BIT(15)
+#define PLLDIV_RATIO_MASK 0x1f
+
+struct pll_data {
+        u32 phys_base;
+        void __iomem *base;
+        u32 num;
+        u32 flags;
+        u32 input_rate;
+};
+#define PLL_HAS_PREDIV          0x01
+#define PLL_HAS_POSTDIV         0x02
+
 struct clk {
         struct list_head        node;
         struct module           *owner;
         const char              *name;
-        unsigned int            *rate;
-        int                     id;
-        __s8                    usecount;
-        __u8                    flags;
-        __u8                    lpsc;
+        unsigned long           rate;
+        u8                      usecount;
+        u8                      flags;
+        u8                      lpsc;
+        struct clk              *parent;
+        struct pll_data         *pll_data;
+        u32                     div_reg;
 };
 
 /* Clock flags */
-#define RATE_CKCTL              1
-#define RATE_FIXED              2
-#define RATE_PROPAGATES         4
-#define VIRTUAL_CLOCK           8
-#define ALWAYS_ENABLED          16
-#define ENABLE_REG_32BIT        32
+#define ALWAYS_ENABLED          BIT(1)
+#define CLK_PSC                 BIT(2)
+#define PSC_DSP                 BIT(3) /* PSC uses DSP domain, not ARM */
+#define CLK_PLL                 BIT(4) /* PLL-derived clock */
+#define PRE_PLL                 BIT(5) /* source is before PLL mult/div */
+
+struct davinci_clk {
+        struct clk_lookup lk;
+};
+
+#define CLK(dev, con, ck)               \
+        {                               \
+                .lk = {                 \
+                        .dev_id = dev,  \
+                        .con_id = con,  \
+                        .clk = ck,      \
+                },                      \
+        }
 
+int davinci_clk_init(struct davinci_clk *clocks);
 #endif
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 808633f9f03c..a31370b93dd2 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -21,6 +21,10 @@
 #include <mach/hardware.h>
 #include <mach/i2c.h>
 #include <mach/irqs.h>
+#include <mach/cputype.h>
+#include <mach/mux.h>
+
+#define DAVINCI_I2C_BASE             0x01C21000
 
 static struct resource i2c_resources[] = {
         {
@@ -43,6 +47,9 @@ static struct platform_device davinci_i2c_device = {
 
 void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata)
 {
+        if (cpu_is_davinci_dm644x())
+                davinci_cfg_reg(DM644X_I2C);
+
         davinci_i2c_device.dev.platform_data = pdata;
         (void) platform_device_register(&davinci_i2c_device);
 }
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
new file mode 100644
index 000000000000..d428ef192eac
--- /dev/null
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -0,0 +1,461 @@
+/*
+ * TI DaVinci DM644x chip specific setup
+ *
+ * Author: Kevin Hilman, Deep Root Systems, LLC
+ *
+ * 2007 (c) Deep Root Systems, LLC. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+
+#include <mach/dm644x.h>
+#include <mach/clock.h>
+#include <mach/cputype.h>
+#include <mach/edma.h>
+#include <mach/irqs.h>
+#include <mach/psc.h>
+#include <mach/mux.h>
+
+#include "clock.h"
+#include "mux.h"
+
+/*
+ * Device specific clocks
+ */
+#define DM644X_REF_FREQ         27000000
+
+static struct pll_data pll1_data = {
+        .num       = 1,
+        .phys_base = DAVINCI_PLL1_BASE,
+};
+
+static struct pll_data pll2_data = {
+        .num       = 2,
+        .phys_base = DAVINCI_PLL2_BASE,
+};
+
+static struct clk ref_clk = {
+        .name = "ref_clk",
+        .rate = DM644X_REF_FREQ,
+};
+
+static struct clk pll1_clk = {
+        .name = "pll1",
+        .parent = &ref_clk,
+        .pll_data = &pll1_data,
+        .flags = CLK_PLL,
+};
+
+static struct clk pll1_sysclk1 = {
+        .name = "pll1_sysclk1",
+        .parent = &pll1_clk,
+        .flags = CLK_PLL,
+        .div_reg = PLLDIV1,
+};
+
+static struct clk pll1_sysclk2 = {
+        .name = "pll1_sysclk2",
+        .parent = &pll1_clk,
+        .flags = CLK_PLL,
+        .div_reg = PLLDIV2,
+};
+
+static struct clk pll1_sysclk3 = {
+        .name = "pll1_sysclk3",
+        .parent = &pll1_clk,
+        .flags = CLK_PLL,
+        .div_reg = PLLDIV3,
+};
+
+static struct clk pll1_sysclk5 = {
+        .name = "pll1_sysclk5",
+        .parent = &pll1_clk,
+        .flags = CLK_PLL,
+        .div_reg = PLLDIV5,
+};
+
+static struct clk pll1_aux_clk = {
+        .name = "pll1_aux_clk",
+        .parent = &pll1_clk,
+        .flags = CLK_PLL | PRE_PLL,
+};
+
+static struct clk pll1_sysclkbp = {
+        .name = "pll1_sysclkbp",
+        .parent = &pll1_clk,
+        .flags = CLK_PLL | PRE_PLL,
+        .div_reg = BPDIV
+};
+
+static struct clk pll2_clk = {
+        .name = "pll2",
+        .parent = &ref_clk,
+        .pll_data = &pll2_data,
+        .flags = CLK_PLL,
+};
+
+static struct clk pll2_sysclk1 = {
+        .name = "pll2_sysclk1",
+        .parent = &pll2_clk,
+        .flags = CLK_PLL,
+        .div_reg = PLLDIV1,
+};
+
+static struct clk pll2_sysclk2 = {
+        .name = "pll2_sysclk2",
+        .parent = &pll2_clk,
+        .flags = CLK_PLL,
+        .div_reg = PLLDIV2,
+};
+
+static struct clk pll2_sysclkbp = {
+        .name = "pll2_sysclkbp",
+        .parent = &pll2_clk,
+        .flags = CLK_PLL | PRE_PLL,
+        .div_reg = BPDIV
+};
+
+static struct clk dsp_clk = {
+        .name = "dsp",
+        .parent = &pll1_sysclk1,
+        .lpsc = DAVINCI_LPSC_GEM,
+        .flags = PSC_DSP,
+        .usecount = 1,                  /* REVISIT how to disable? */
+};
+
+static struct clk arm_clk = {
+        .name = "arm",
+        .parent = &pll1_sysclk2,
+        .lpsc = DAVINCI_LPSC_ARM,
+        .flags = ALWAYS_ENABLED,
+};
+
+static struct clk vicp_clk = {
+        .name = "vicp",
+        .parent = &pll1_sysclk2,
+        .lpsc = DAVINCI_LPSC_IMCOP,
+        .flags = PSC_DSP,
+        .usecount = 1,                  /* REVISIT how to disable? */
+};
+
+static struct clk vpss_master_clk = {
+        .name = "vpss_master",
+        .parent = &pll1_sysclk3,
+        .lpsc = DAVINCI_LPSC_VPSSMSTR,
+        .flags = CLK_PSC,
+};
+
+static struct clk vpss_slave_clk = {
+        .name = "vpss_slave",
+        .parent = &pll1_sysclk3,
+        .lpsc = DAVINCI_LPSC_VPSSSLV,
+};
+
+static struct clk uart0_clk = {
+        .name = "uart0",
+        .parent = &pll1_aux_clk,
+        .lpsc = DAVINCI_LPSC_UART0,
+};
+
+static struct clk uart1_clk = {
+        .name = "uart1",
+        .parent = &pll1_aux_clk,
+        .lpsc = DAVINCI_LPSC_UART1,
+};
+
+static struct clk uart2_clk = {
+        .name = "uart2",
+        .parent = &pll1_aux_clk,
+        .lpsc = DAVINCI_LPSC_UART2,
+};
+
+static struct clk emac_clk = {
+        .name = "emac",
+        .parent = &pll1_sysclk5,
+        .lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
+};
+
+static struct clk i2c_clk = {
+        .name = "i2c",
+        .parent = &pll1_aux_clk,
+        .lpsc = DAVINCI_LPSC_I2C,
+};
+
+static struct clk ide_clk = {
+        .name = "ide",
+        .parent = &pll1_sysclk5,
+        .lpsc = DAVINCI_LPSC_ATA,
+};
+
+static struct clk asp_clk = {
+        .name = "asp0",
+        .parent = &pll1_sysclk5,
+        .lpsc = DAVINCI_LPSC_McBSP,
+};
+
+static struct clk mmcsd_clk = {
+        .name = "mmcsd",
+        .parent = &pll1_sysclk5,
+        .lpsc = DAVINCI_LPSC_MMC_SD,
+};
+
+static struct clk spi_clk = {
+        .name = "spi",
+        .parent = &pll1_sysclk5,
+        .lpsc = DAVINCI_LPSC_SPI,
+};
+
+static struct clk gpio_clk = {
+        .name = "gpio",
+        .parent = &pll1_sysclk5,
+        .lpsc = DAVINCI_LPSC_GPIO,
+};
+
+static struct clk usb_clk = {
+        .name = "usb",
+        .parent = &pll1_sysclk5,
+        .lpsc = DAVINCI_LPSC_USB,
+};
+
+static struct clk vlynq_clk = {
+        .name = "vlynq",
+        .parent = &pll1_sysclk5,
+        .lpsc = DAVINCI_LPSC_VLYNQ,
+};
+
+static struct clk aemif_clk = {
+        .name = "aemif",
+        .parent = &pll1_sysclk5,
+        .lpsc = DAVINCI_LPSC_AEMIF,
+};
+
+static struct clk pwm0_clk = {
+        .name = "pwm0",
+        .parent = &pll1_aux_clk,
+        .lpsc = DAVINCI_LPSC_PWM0,
+};
+
+static struct clk pwm1_clk = {
+        .name = "pwm1",
+        .parent = &pll1_aux_clk,
+        .lpsc = DAVINCI_LPSC_PWM1,
+};
+
+static struct clk pwm2_clk = {
+        .name = "pwm2",
+        .parent = &pll1_aux_clk,
+        .lpsc = DAVINCI_LPSC_PWM2,
+};
+
+static struct clk timer0_clk = {
+        .name = "timer0",
+        .parent = &pll1_aux_clk,
+        .lpsc = DAVINCI_LPSC_TIMER0,
+};
+
+static struct clk timer1_clk = {
+        .name = "timer1",
+        .parent = &pll1_aux_clk,
+        .lpsc = DAVINCI_LPSC_TIMER1,
+};
+
+static struct clk timer2_clk = {
+        .name = "timer2",
+        .parent = &pll1_aux_clk,
+        .lpsc = DAVINCI_LPSC_TIMER2,
+        .usecount = 1,              /* REVISIT: why cant' this be disabled? */
+};
+
+struct davinci_clk dm644x_clks[] = {
+        CLK(NULL, "ref", &ref_clk),
+        CLK(NULL, "pll1", &pll1_clk),
+        CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
+        CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
+        CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
+        CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
+        CLK(NULL, "pll1_aux", &pll1_aux_clk),
+        CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
+        CLK(NULL, "pll2", &pll2_clk),
+        CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
+        CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
+        CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
+        CLK(NULL, "dsp", &dsp_clk),
+        CLK(NULL, "arm", &arm_clk),
+        CLK(NULL, "vicp", &vicp_clk),
+        CLK(NULL, "vpss_master", &vpss_master_clk),
+        CLK(NULL, "vpss_slave", &vpss_slave_clk),
+        CLK(NULL, "arm", &arm_clk),
+        CLK(NULL, "uart0", &uart0_clk),
+        CLK(NULL, "uart1", &uart1_clk),
+        CLK(NULL, "uart2", &uart2_clk),
+        CLK("davinci_emac.1", NULL, &emac_clk),
+        CLK("i2c_davinci.1", NULL, &i2c_clk),
+        CLK("palm_bk3710", NULL, &ide_clk),
+        CLK("soc-audio.0", NULL, &asp_clk),
+        CLK("davinci_mmc.0", NULL, &mmcsd_clk),
+        CLK(NULL, "spi", &spi_clk),
+        CLK(NULL, "gpio", &gpio_clk),
+        CLK(NULL, "usb", &usb_clk),
+        CLK(NULL, "vlynq", &vlynq_clk),
+        CLK(NULL, "aemif", &aemif_clk),
+        CLK(NULL, "pwm0", &pwm0_clk),
+        CLK(NULL, "pwm1", &pwm1_clk),
+        CLK(NULL, "pwm2", &pwm2_clk),
+        CLK(NULL, "timer0", &timer0_clk),
+        CLK(NULL, "timer1", &timer1_clk),
+        CLK("watchdog", NULL, &timer2_clk),
+        CLK(NULL, NULL, NULL),
+};
+
+#if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
+
+static struct resource dm644x_emac_resources[] = {
+        {
+                .start  = DM644X_EMAC_BASE,
+                .end    = DM644X_EMAC_BASE + 0x47ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_EMACINT,
+                .end   = IRQ_EMACINT,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device dm644x_emac_device = {
+       .name            = "davinci_emac",
+       .id              = 1,
+       .num_resources   = ARRAY_SIZE(dm644x_emac_resources),
+       .resource        = dm644x_emac_resources,
+};
+
+#endif
+
+/*
+ * Device specific mux setup
+ *
+ *      soc     description     mux  mode   mode  mux    dbg
+ *                              reg  offset mask  mode
+ */
+static const struct mux_config dm644x_pins[] = {
+MUX_CFG(DM644X, HDIREN,         0,   16,    1,    1,     true)
+MUX_CFG(DM644X, ATAEN,          0,   17,    1,    1,     true)
+MUX_CFG(DM644X, ATAEN_DISABLE,  0,   17,    1,    0,     true)
+
+MUX_CFG(DM644X, HPIEN_DISABLE,  0,   29,    1,    0,     true)
+
+MUX_CFG(DM644X, AEAW,           0,   0,     31,   31,    true)
+
+MUX_CFG(DM644X, MSTK,           1,   9,     1,    0,     false)
+
+MUX_CFG(DM644X, I2C,            1,   7,     1,    1,     false)
+
+MUX_CFG(DM644X, MCBSP,          1,   10,    1,    1,     false)
+
+MUX_CFG(DM644X, UART1,          1,   1,     1,    1,     true)
+MUX_CFG(DM644X, UART2,          1,   2,     1,    1,     true)
+
+MUX_CFG(DM644X, PWM0,           1,   4,     1,    1,     false)
+
+MUX_CFG(DM644X, PWM1,           1,   5,     1,    1,     false)
+
+MUX_CFG(DM644X, PWM2,           1,   6,     1,    1,     false)
+
+MUX_CFG(DM644X, VLYNQEN,        0,   15,    1,    1,     false)
+MUX_CFG(DM644X, VLSCREN,        0,   14,    1,    1,     false)
+MUX_CFG(DM644X, VLYNQWD,        0,   12,    3,    3,     false)
+
+MUX_CFG(DM644X, EMACEN,         0,   31,    1,    1,     true)
+
+MUX_CFG(DM644X, GPIO3V,         0,   31,    1,    0,     true)
+
+MUX_CFG(DM644X, GPIO0,          0,   24,    1,    0,     true)
+MUX_CFG(DM644X, GPIO3,          0,   25,    1,    0,     false)
+MUX_CFG(DM644X, GPIO43_44,      1,   7,     1,    0,     false)
+MUX_CFG(DM644X, GPIO46_47,      0,   22,    1,    0,     true)
+
+MUX_CFG(DM644X, RGB666,         0,   22,    1,    1,     true)
+
+MUX_CFG(DM644X, LOEEN,          0,   24,    1,    1,     true)
+MUX_CFG(DM644X, LFLDEN,         0,   25,    1,    1,     false)
+};
+
+
+/*----------------------------------------------------------------------*/
+
+static const s8 dma_chan_dm644x_no_event[] = {
+         0,  1, 12, 13, 14,
+        15, 25, 30, 31, 45,
+        46, 47, 55, 56, 57,
+        58, 59, 60, 61, 62,
+        63,
+        -1
+};
+
+static struct edma_soc_info dm644x_edma_info = {
+        .n_channel      = 64,
+        .n_region       = 4,
+        .n_slot         = 128,
+        .n_tc           = 2,
+        .noevent        = dma_chan_dm644x_no_event,
+};
+
+static struct resource edma_resources[] = {
+        {
+                .name   = "edma_cc",
+                .start  = 0x01c00000,
+                .end    = 0x01c00000 + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "edma_tc0",
+                .start  = 0x01c10000,
+                .end    = 0x01c10000 + SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "edma_tc1",
+                .start  = 0x01c10400,
+                .end    = 0x01c10400 + SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = IRQ_CCINT0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_CCERRINT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        /* not using TC*_ERR */
+};
+
+static struct platform_device dm644x_edma_device = {
+        .name                   = "edma",
+        .id                     = -1,
+        .dev.platform_data      = &dm644x_edma_info,
+        .num_resources          = ARRAY_SIZE(edma_resources),
+        .resource               = edma_resources,
+};
+
+/*----------------------------------------------------------------------*/
+void __init dm644x_init(void)
+{
+        davinci_clk_init(dm644x_clks);
+        davinci_mux_register(dm644x_pins, ARRAY_SIZE(dm644x_pins));
+}
+
+static int __init dm644x_init_devices(void)
+{
+        if (!cpu_is_davinci_dm644x())
+                return 0;
+
+        platform_device_register(&dm644x_edma_device);
+        return 0;
+}
+postcore_initcall(dm644x_init_devices);
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
new file mode 100644
index 000000000000..15e9eb158bb7
--- /dev/null
+++ b/arch/arm/mach-davinci/dma.c
@@ -0,0 +1,1135 @@
+/*
+ * EDMA3 support for DaVinci
+ *
+ * Copyright (C) 2006-2009 Texas Instruments.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/compiler.h>
+#include <linux/io.h>
+
+#include <mach/cputype.h>
+#include <mach/memory.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <mach/edma.h>
+#include <mach/mux.h>
+
+
+/* Offsets matching "struct edmacc_param" */
+#define PARM_OPT                0x00
+#define PARM_SRC                0x04
+#define PARM_A_B_CNT            0x08
+#define PARM_DST                0x0c
+#define PARM_SRC_DST_BIDX       0x10
+#define PARM_LINK_BCNTRLD       0x14
+#define PARM_SRC_DST_CIDX       0x18
+#define PARM_CCNT               0x1c
+
+#define PARM_SIZE               0x20
+
+/* Offsets for EDMA CC global channel registers and their shadows */
+#define SH_ER           0x00    /* 64 bits */
+#define SH_ECR          0x08    /* 64 bits */
+#define SH_ESR          0x10    /* 64 bits */
+#define SH_CER          0x18    /* 64 bits */
+#define SH_EER          0x20    /* 64 bits */
+#define SH_EECR         0x28    /* 64 bits */
+#define SH_EESR         0x30    /* 64 bits */
+#define SH_SER          0x38    /* 64 bits */
+#define SH_SECR         0x40    /* 64 bits */
+#define SH_IER          0x50    /* 64 bits */
+#define SH_IECR         0x58    /* 64 bits */
+#define SH_IESR         0x60    /* 64 bits */
+#define SH_IPR          0x68    /* 64 bits */
+#define SH_ICR          0x70    /* 64 bits */
+#define SH_IEVAL        0x78
+#define SH_QER          0x80
+#define SH_QEER         0x84
+#define SH_QEECR        0x88
+#define SH_QEESR        0x8c
+#define SH_QSER         0x90
+#define SH_QSECR        0x94
+#define SH_SIZE         0x200
+
+/* Offsets for EDMA CC global registers */
+#define EDMA_REV        0x0000
+#define EDMA_CCCFG      0x0004
+#define EDMA_QCHMAP     0x0200  /* 8 registers */
+#define EDMA_DMAQNUM    0x0240  /* 8 registers (4 on OMAP-L1xx) */
+#define EDMA_QDMAQNUM   0x0260
+#define EDMA_QUETCMAP   0x0280
+#define EDMA_QUEPRI     0x0284
+#define EDMA_EMR        0x0300  /* 64 bits */
+#define EDMA_EMCR       0x0308  /* 64 bits */
+#define EDMA_QEMR       0x0310
+#define EDMA_QEMCR      0x0314
+#define EDMA_CCERR      0x0318
+#define EDMA_CCERRCLR   0x031c
+#define EDMA_EEVAL      0x0320
+#define EDMA_DRAE       0x0340  /* 4 x 64 bits*/
+#define EDMA_QRAE       0x0380  /* 4 registers */
+#define EDMA_QUEEVTENTRY        0x0400  /* 2 x 16 registers */
+#define EDMA_QSTAT      0x0600  /* 2 registers */
+#define EDMA_QWMTHRA    0x0620
+#define EDMA_QWMTHRB    0x0624
+#define EDMA_CCSTAT     0x0640
+
+#define EDMA_M          0x1000  /* global channel registers */
+#define EDMA_ECR        0x1008
+#define EDMA_ECRH       0x100C
+#define EDMA_SHADOW0    0x2000  /* 4 regions shadowing global channels */
+#define EDMA_PARM       0x4000  /* 128 param entries */
+
+#define DAVINCI_DMA_3PCC_BASE   0x01C00000
+
+#define PARM_OFFSET(param_no)   (EDMA_PARM + ((param_no) << 5))
+
+#define EDMA_MAX_DMACH           64
+#define EDMA_MAX_PARAMENTRY     512
+#define EDMA_MAX_EVQUE            2     /* FIXME too small */
+
+
+/*****************************************************************************/
+
+static void __iomem *edmacc_regs_base;
+
+static inline unsigned int edma_read(int offset)
+{
+        return (unsigned int)__raw_readl(edmacc_regs_base + offset);
+}
+
+static inline void edma_write(int offset, int val)
+{
+        __raw_writel(val, edmacc_regs_base + offset);
+}
+static inline void edma_modify(int offset, unsigned and, unsigned or)
+{
+        unsigned val = edma_read(offset);
+        val &= and;
+        val |= or;
+        edma_write(offset, val);
+}
+static inline void edma_and(int offset, unsigned and)
+{
+        unsigned val = edma_read(offset);
+        val &= and;
+        edma_write(offset, val);
+}
+static inline void edma_or(int offset, unsigned or)
+{
+        unsigned val = edma_read(offset);
+        val |= or;
+        edma_write(offset, val);
+}
+static inline unsigned int edma_read_array(int offset, int i)
+{
+        return edma_read(offset + (i << 2));
+}
+static inline void edma_write_array(int offset, int i, unsigned val)
+{
+        edma_write(offset + (i << 2), val);
+}
+static inline void edma_modify_array(int offset, int i,
+                unsigned and, unsigned or)
+{
+        edma_modify(offset + (i << 2), and, or);
+}
+static inline void edma_or_array(int offset, int i, unsigned or)
+{
+        edma_or(offset + (i << 2), or);
+}
+static inline void edma_or_array2(int offset, int i, int j, unsigned or)
+{
+        edma_or(offset + ((i*2 + j) << 2), or);
+}
+static inline void edma_write_array2(int offset, int i, int j, unsigned val)
+{
+        edma_write(offset + ((i*2 + j) << 2), val);
+}
+static inline unsigned int edma_shadow0_read(int offset)
+{
+        return edma_read(EDMA_SHADOW0 + offset);
+}
+static inline unsigned int edma_shadow0_read_array(int offset, int i)
+{
+        return edma_read(EDMA_SHADOW0 + offset + (i << 2));
+}
+static inline void edma_shadow0_write(int offset, unsigned val)
+{
+        edma_write(EDMA_SHADOW0 + offset, val);
+}
+static inline void edma_shadow0_write_array(int offset, int i, unsigned val)
+{
+        edma_write(EDMA_SHADOW0 + offset + (i << 2), val);
+}
+static inline unsigned int edma_parm_read(int offset, int param_no)
+{
+        return edma_read(EDMA_PARM + offset + (param_no << 5));
+}
+static inline void edma_parm_write(int offset, int param_no, unsigned val)
+{
+        edma_write(EDMA_PARM + offset + (param_no << 5), val);
+}
+static inline void edma_parm_modify(int offset, int param_no,
+                unsigned and, unsigned or)
+{
+        edma_modify(EDMA_PARM + offset + (param_no << 5), and, or);
+}
+static inline void edma_parm_and(int offset, int param_no, unsigned and)
+{
+        edma_and(EDMA_PARM + offset + (param_no << 5), and);
+}
+static inline void edma_parm_or(int offset, int param_no, unsigned or)
+{
+        edma_or(EDMA_PARM + offset + (param_no << 5), or);
+}
+
+/*****************************************************************************/
+
+/* actual number of DMA channels and slots on this silicon */
+static unsigned num_channels;
+static unsigned num_slots;
+
+static struct dma_interrupt_data {
+        void (*callback)(unsigned channel, unsigned short ch_status,
+                         void *data);
+        void *data;
+} intr_data[EDMA_MAX_DMACH];
+
+/* The edma_inuse bit for each PaRAM slot is clear unless the
+ * channel is in use ... by ARM or DSP, for QDMA, or whatever.
+ */
+static DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
+
+/* The edma_noevent bit for each channel is clear unless
+ * it doesn't trigger DMA events on this platform.  It uses a
+ * bit of SOC-specific initialization code.
+ */
+static DECLARE_BITMAP(edma_noevent, EDMA_MAX_DMACH);
+
+/* dummy param set used to (re)initialize parameter RAM slots */
+static const struct edmacc_param dummy_paramset = {
+        .link_bcntrld = 0xffff,
+        .ccnt = 1,
+};
+
+static const int __initconst
+queue_tc_mapping[EDMA_MAX_EVQUE + 1][2] = {
+/* {event queue no, TC no} */
+        {0, 0},
+        {1, 1},
+        {-1, -1}
+};
+
+static const int __initconst
+queue_priority_mapping[EDMA_MAX_EVQUE + 1][2] = {
+        /* {event queue no, Priority} */
+        {0, 3},
+        {1, 7},
+        {-1, -1}
+};
+
+/*****************************************************************************/
+
+static void map_dmach_queue(unsigned ch_no, enum dma_event_q queue_no)
+{
+        int bit = (ch_no & 0x7) * 4;
+
+        /* default to low priority queue */
+        if (queue_no == EVENTQ_DEFAULT)
+                queue_no = EVENTQ_1;
+
+        queue_no &= 7;
+        edma_modify_array(EDMA_DMAQNUM, (ch_no >> 3),
+                        ~(0x7 << bit), queue_no << bit);
+}
+
+static void __init map_queue_tc(int queue_no, int tc_no)
+{
+        int bit = queue_no * 4;
+        edma_modify(EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit));
+}
+
+static void __init assign_priority_to_queue(int queue_no, int priority)
+{
+        int bit = queue_no * 4;
+        edma_modify(EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit));
+}
+
+static inline void
+setup_dma_interrupt(unsigned lch,
+        void (*callback)(unsigned channel, u16 ch_status, void *data),
+        void *data)
+{
+        if (!callback) {
+                edma_shadow0_write_array(SH_IECR, lch >> 5,
+                                (1 << (lch & 0x1f)));
+        }
+
+        intr_data[lch].callback = callback;
+        intr_data[lch].data = data;
+
+        if (callback) {
+                edma_shadow0_write_array(SH_ICR, lch >> 5,
+                                (1 << (lch & 0x1f)));
+                edma_shadow0_write_array(SH_IESR, lch >> 5,
+                                (1 << (lch & 0x1f)));
+        }
+}
+
+/******************************************************************************
+ *
+ * DMA interrupt handler
+ *
+ *****************************************************************************/
+static irqreturn_t dma_irq_handler(int irq, void *data)
+{
+        int i;
+        unsigned int cnt = 0;
+
+        dev_dbg(data, "dma_irq_handler\n");
+
+        if ((edma_shadow0_read_array(SH_IPR, 0) == 0)
+            && (edma_shadow0_read_array(SH_IPR, 1) == 0))
+                return IRQ_NONE;
+
+        while (1) {
+                int j;
+                if (edma_shadow0_read_array(SH_IPR, 0))
+                        j = 0;
+                else if (edma_shadow0_read_array(SH_IPR, 1))
+                        j = 1;
+                else
+                        break;
+                dev_dbg(data, "IPR%d %08x\n", j,
+                                edma_shadow0_read_array(SH_IPR, j));
+                for (i = 0; i < 32; i++) {
+                        int k = (j << 5) + i;
+                        if (edma_shadow0_read_array(SH_IPR, j) & (1 << i)) {
+                                /* Clear the corresponding IPR bits */
+                                edma_shadow0_write_array(SH_ICR, j, (1 << i));
+                                if (intr_data[k].callback) {
+                                        intr_data[k].callback(k, DMA_COMPLETE,
+                                                intr_data[k].data);
+                                }
+                        }
+                }
+                cnt++;
+                if (cnt > 10)
+                        break;
+        }
+        edma_shadow0_write(SH_IEVAL, 1);
+        return IRQ_HANDLED;
+}
+
+/******************************************************************************
+ *
+ * DMA error interrupt handler
+ *
+ *****************************************************************************/
+static irqreturn_t dma_ccerr_handler(int irq, void *data)
+{
+        int i;
+        unsigned int cnt = 0;
+
+        dev_dbg(data, "dma_ccerr_handler\n");
+
+        if ((edma_read_array(EDMA_EMR, 0) == 0) &&
+            (edma_read_array(EDMA_EMR, 1) == 0) &&
+            (edma_read(EDMA_QEMR) == 0) && (edma_read(EDMA_CCERR) == 0))
+                return IRQ_NONE;
+
+        while (1) {
+                int j = -1;
+                if (edma_read_array(EDMA_EMR, 0))
+                        j = 0;
+                else if (edma_read_array(EDMA_EMR, 1))
+                        j = 1;
+                if (j >= 0) {
+                        dev_dbg(data, "EMR%d %08x\n", j,
+                                        edma_read_array(EDMA_EMR, j));
+                        for (i = 0; i < 32; i++) {
+                                int k = (j << 5) + i;
+                                if (edma_read_array(EDMA_EMR, j) & (1 << i)) {
+                                        /* Clear the corresponding EMR bits */
+                                        edma_write_array(EDMA_EMCR, j, 1 << i);
+                                        /* Clear any SER */
+                                        edma_shadow0_write_array(SH_SECR, j,
+                                                        (1 << i));
+                                        if (intr_data[k].callback) {
+                                                intr_data[k].callback(k,
+                                                                DMA_CC_ERROR,
+                                                                intr_data
+                                                                [k].data);
+                                        }
+                                }
+                        }
+                } else if (edma_read(EDMA_QEMR)) {
+                        dev_dbg(data, "QEMR %02x\n",
+                                edma_read(EDMA_QEMR));
+                        for (i = 0; i < 8; i++) {
+                                if (edma_read(EDMA_QEMR) & (1 << i)) {
+                                        /* Clear the corresponding IPR bits */
+                                        edma_write(EDMA_QEMCR, 1 << i);
+                                        edma_shadow0_write(SH_QSECR, (1 << i));
+
+                                        /* NOTE:  not reported!! */
+                                }
+                        }
+                } else if (edma_read(EDMA_CCERR)) {
+                        dev_dbg(data, "CCERR %08x\n",
+                                edma_read(EDMA_CCERR));
+                        /* FIXME:  CCERR.BIT(16) ignored!  much better
+                         * to just write CCERRCLR with CCERR value...
+                         */
+                        for (i = 0; i < 8; i++) {
+                                if (edma_read(EDMA_CCERR) & (1 << i)) {
+                                        /* Clear the corresponding IPR bits */
+                                        edma_write(EDMA_CCERRCLR, 1 << i);
+
+                                        /* NOTE:  not reported!! */
+                                }
+                        }
+                }
+                if ((edma_read_array(EDMA_EMR, 0) == 0)
+                    && (edma_read_array(EDMA_EMR, 1) == 0)
+                    && (edma_read(EDMA_QEMR) == 0)
+                    && (edma_read(EDMA_CCERR) == 0)) {
+                        break;
+                }
+                cnt++;
+                if (cnt > 10)
+                        break;
+        }
+        edma_write(EDMA_EEVAL, 1);
+        return IRQ_HANDLED;
+}
+
+/******************************************************************************
+ *
+ * Transfer controller error interrupt handlers
+ *
+ *****************************************************************************/
+
+#define tc_errs_handled false   /* disabled as long as they're NOPs */
+
+static irqreturn_t dma_tc0err_handler(int irq, void *data)
+{
+        dev_dbg(data, "dma_tc0err_handler\n");
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t dma_tc1err_handler(int irq, void *data)
+{
+        dev_dbg(data, "dma_tc1err_handler\n");
+        return IRQ_HANDLED;
+}
+
+/*-----------------------------------------------------------------------*/
+
+/* Resource alloc/free:  dma channels, parameter RAM slots */
+
+/**
+ * edma_alloc_channel - allocate DMA channel and paired parameter RAM
+ * @channel: specific channel to allocate; negative for "any unmapped channel"
+ * @callback: optional; to be issued on DMA completion or errors
+ * @data: passed to callback
+ * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
+ *      Controller (TC) executes requests using this channel.  Use
+ *      EVENTQ_DEFAULT unless you really need a high priority queue.
+ *
+ * This allocates a DMA channel and its associated parameter RAM slot.
+ * The parameter RAM is initialized to hold a dummy transfer.
+ *
+ * Normal use is to pass a specific channel number as @channel, to make
+ * use of hardware events mapped to that channel.  When the channel will
+ * be used only for software triggering or event chaining, channels not
+ * mapped to hardware events (or mapped to unused events) are preferable.
+ *
+ * DMA transfers start from a channel using edma_start(), or by
+ * chaining.  When the transfer described in that channel's parameter RAM
+ * slot completes, that slot's data may be reloaded through a link.
+ *
+ * DMA errors are only reported to the @callback associated with the
+ * channel driving that transfer, but transfer completion callbacks can
+ * be sent to another channel under control of the TCC field in
+ * the option word of the transfer's parameter RAM set.  Drivers must not
+ * use DMA transfer completion callbacks for channels they did not allocate.
+ * (The same applies to TCC codes used in transfer chaining.)
+ *
+ * Returns the number of the channel, else negative errno.
+ */
+int edma_alloc_channel(int channel,
+                void (*callback)(unsigned channel, u16 ch_status, void *data),
+                void *data,
+                enum dma_event_q eventq_no)
+{
+        if (channel < 0) {
+                channel = 0;
+                for (;;) {
+                        channel = find_next_bit(edma_noevent,
+                                        num_channels, channel);
+                        if (channel == num_channels)
+                                return -ENOMEM;
+                        if (!test_and_set_bit(channel, edma_inuse))
+                                break;
+                        channel++;
+                }
+        } else if (channel >= num_channels) {
+                return -EINVAL;
+        } else if (test_and_set_bit(channel, edma_inuse)) {
+                return -EBUSY;
+        }
+
+        /* ensure access through shadow region 0 */
+        edma_or_array2(EDMA_DRAE, 0, channel >> 5, 1 << (channel & 0x1f));
+
+        /* ensure no events are pending */
+        edma_stop(channel);
+        memcpy_toio(edmacc_regs_base + PARM_OFFSET(channel),
+                        &dummy_paramset, PARM_SIZE);
+
+        if (callback)
+                setup_dma_interrupt(channel, callback, data);
+
+        map_dmach_queue(channel, eventq_no);
+
+        return channel;
+}
+EXPORT_SYMBOL(edma_alloc_channel);
+
+
+/**
+ * edma_free_channel - deallocate DMA channel
+ * @channel: dma channel returned from edma_alloc_channel()
+ *
+ * This deallocates the DMA channel and associated parameter RAM slot
+ * allocated by edma_alloc_channel().
+ *
+ * Callers are responsible for ensuring the channel is inactive, and
+ * will not be reactivated by linking, chaining, or software calls to
+ * edma_start().
+ */
+void edma_free_channel(unsigned channel)
+{
+        if (channel >= num_channels)
+                return;
+
+        setup_dma_interrupt(channel, NULL, NULL);
+        /* REVISIT should probably take out of shadow region 0 */
+
+        memcpy_toio(edmacc_regs_base + PARM_OFFSET(channel),
+                        &dummy_paramset, PARM_SIZE);
+        clear_bit(channel, edma_inuse);
+}
+EXPORT_SYMBOL(edma_free_channel);
+
+/**
+ * edma_alloc_slot - allocate DMA parameter RAM
+ * @slot: specific slot to allocate; negative for "any unused slot"
+ *
+ * This allocates a parameter RAM slot, initializing it to hold a
+ * dummy transfer.  Slots allocated using this routine have not been
+ * mapped to a hardware DMA channel, and will normally be used by
+ * linking to them from a slot associated with a DMA channel.
+ *
+ * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
+ * slots may be allocated on behalf of DSP firmware.
+ *
+ * Returns the number of the slot, else negative errno.
+ */
+int edma_alloc_slot(int slot)
+{
+        if (slot < 0) {
+                slot = num_channels;
+                for (;;) {
+                        slot = find_next_zero_bit(edma_inuse,
+                                        num_slots, slot);
+                        if (slot == num_slots)
+                                return -ENOMEM;
+                        if (!test_and_set_bit(slot, edma_inuse))
+                                break;
+                }
+        } else if (slot < num_channels || slot >= num_slots) {
+                return -EINVAL;
+        } else if (test_and_set_bit(slot, edma_inuse)) {
+                return -EBUSY;
+        }
+
+        memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot),
+                        &dummy_paramset, PARM_SIZE);
+
+        return slot;
+}
+EXPORT_SYMBOL(edma_alloc_slot);
+
+/**
+ * edma_free_slot - deallocate DMA parameter RAM
+ * @slot: parameter RAM slot returned from edma_alloc_slot()
+ *
+ * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
+ * Callers are responsible for ensuring the slot is inactive, and will
+ * not be activated.
+ */
+void edma_free_slot(unsigned slot)
+{
+        if (slot < num_channels || slot >= num_slots)
+                return;
+
+        memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot),
+                        &dummy_paramset, PARM_SIZE);
+        clear_bit(slot, edma_inuse);
+}
+EXPORT_SYMBOL(edma_free_slot);
+
+/*-----------------------------------------------------------------------*/
+
+/* Parameter RAM operations (i) -- read/write partial slots */
+
+/**
+ * edma_set_src - set initial DMA source address in parameter RAM slot
+ * @slot: parameter RAM slot being configured
+ * @src_port: physical address of source (memory, controller FIFO, etc)
+ * @addressMode: INCR, except in very rare cases
+ * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
+ *      width to use when addressing the fifo (e.g. W8BIT, W32BIT)
+ *
+ * Note that the source address is modified during the DMA transfer
+ * according to edma_set_src_index().
+ */
+void edma_set_src(unsigned slot, dma_addr_t src_port,
+                                enum address_mode mode, enum fifo_width width)
+{
+        if (slot < num_slots) {
+                unsigned int i = edma_parm_read(PARM_OPT, slot);
+
+                if (mode) {
+                        /* set SAM and program FWID */
+                        i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8));
+                } else {
+                        /* clear SAM */
+                        i &= ~SAM;
+                }
+                edma_parm_write(PARM_OPT, slot, i);
+
+                /* set the source port address
+                   in source register of param structure */
+                edma_parm_write(PARM_SRC, slot, src_port);
+        }
+}
+EXPORT_SYMBOL(edma_set_src);
+
+/**
+ * edma_set_dest - set initial DMA destination address in parameter RAM slot
+ * @slot: parameter RAM slot being configured
+ * @dest_port: physical address of destination (memory, controller FIFO, etc)
+ * @addressMode: INCR, except in very rare cases
+ * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
+ *      width to use when addressing the fifo (e.g. W8BIT, W32BIT)
+ *
+ * Note that the destination address is modified during the DMA transfer
+ * according to edma_set_dest_index().
+ */
+void edma_set_dest(unsigned slot, dma_addr_t dest_port,
+                                 enum address_mode mode, enum fifo_width width)
+{
+        if (slot < num_slots) {
+                unsigned int i = edma_parm_read(PARM_OPT, slot);
+
+                if (mode) {
+                        /* set DAM and program FWID */
+                        i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8));
+                } else {
+                        /* clear DAM */
+                        i &= ~DAM;
+                }
+                edma_parm_write(PARM_OPT, slot, i);
+                /* set the destination port address
+                   in dest register of param structure */
+                edma_parm_write(PARM_DST, slot, dest_port);
+        }
+}
+EXPORT_SYMBOL(edma_set_dest);
+
+/**
+ * edma_get_position - returns the current transfer points
+ * @slot: parameter RAM slot being examined
+ * @src: pointer to source port position
+ * @dst: pointer to destination port position
+ *
+ * Returns current source and destination addresses for a particular
+ * parameter RAM slot.  Its channel should not be active when this is called.
+ */
+void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst)
+{
+        struct edmacc_param temp;
+
+        edma_read_slot(slot, &temp);
+        if (src != NULL)
+                *src = temp.src;
+        if (dst != NULL)
+                *dst = temp.dst;
+}
+EXPORT_SYMBOL(edma_get_position);
+
+/**
+ * edma_set_src_index - configure DMA source address indexing
+ * @slot: parameter RAM slot being configured
+ * @src_bidx: byte offset between source arrays in a frame
+ * @src_cidx: byte offset between source frames in a block
+ *
+ * Offsets are specified to support either contiguous or discontiguous
+ * memory transfers, or repeated access to a hardware register, as needed.
+ * When accessing hardware registers, both offsets are normally zero.
+ */
+void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
+{
+        if (slot < num_slots) {
+                edma_parm_modify(PARM_SRC_DST_BIDX, slot,
+                                0xffff0000, src_bidx);
+                edma_parm_modify(PARM_SRC_DST_CIDX, slot,
+                                0xffff0000, src_cidx);
+        }
+}
+EXPORT_SYMBOL(edma_set_src_index);
+
+/**
+ * edma_set_dest_index - configure DMA destination address indexing
+ * @slot: parameter RAM slot being configured
+ * @dest_bidx: byte offset between destination arrays in a frame
+ * @dest_cidx: byte offset between destination frames in a block
+ *
+ * Offsets are specified to support either contiguous or discontiguous
+ * memory transfers, or repeated access to a hardware register, as needed.
+ * When accessing hardware registers, both offsets are normally zero.
+ */
+void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
+{
+        if (slot < num_slots) {
+                edma_parm_modify(PARM_SRC_DST_BIDX, slot,
+                                0x0000ffff, dest_bidx << 16);
+                edma_parm_modify(PARM_SRC_DST_CIDX, slot,
+                                0x0000ffff, dest_cidx << 16);
+        }
+}
+EXPORT_SYMBOL(edma_set_dest_index);
+
+/**
+ * edma_set_transfer_params - configure DMA transfer parameters
+ * @slot: parameter RAM slot being configured
+ * @acnt: how many bytes per array (at least one)
+ * @bcnt: how many arrays per frame (at least one)
+ * @ccnt: how many frames per block (at least one)
+ * @bcnt_rld: used only for A-Synchronized transfers; this specifies
+ *      the value to reload into bcnt when it decrements to zero
+ * @sync_mode: ASYNC or ABSYNC
+ *
+ * See the EDMA3 documentation to understand how to configure and link
+ * transfers using the fields in PaRAM slots.  If you are not doing it
+ * all at once with edma_write_slot(), you will use this routine
+ * plus two calls each for source and destination, setting the initial
+ * address and saying how to index that address.
+ *
+ * An example of an A-Synchronized transfer is a serial link using a
+ * single word shift register.  In that case, @acnt would be equal to
+ * that word size; the serial controller issues a DMA synchronization
+ * event to transfer each word, and memory access by the DMA transfer
+ * controller will be word-at-a-time.
+ *
+ * An example of an AB-Synchronized transfer is a device using a FIFO.
+ * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
+ * The controller with the FIFO issues DMA synchronization events when
+ * the FIFO threshold is reached, and the DMA transfer controller will
+ * transfer one frame to (or from) the FIFO.  It will probably use
+ * efficient burst modes to access memory.
+ */
+void edma_set_transfer_params(unsigned slot,
+                u16 acnt, u16 bcnt, u16 ccnt,
+                u16 bcnt_rld, enum sync_dimension sync_mode)
+{
+        if (slot < num_slots) {
+                edma_parm_modify(PARM_LINK_BCNTRLD, slot,
+                                0x0000ffff, bcnt_rld << 16);
+                if (sync_mode == ASYNC)
+                        edma_parm_and(PARM_OPT, slot, ~SYNCDIM);
+                else
+                        edma_parm_or(PARM_OPT, slot, SYNCDIM);
+                /* Set the acount, bcount, ccount registers */
+                edma_parm_write(PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
+                edma_parm_write(PARM_CCNT, slot, ccnt);
+        }
+}
+EXPORT_SYMBOL(edma_set_transfer_params);
+
+/**
+ * edma_link - link one parameter RAM slot to another
+ * @from: parameter RAM slot originating the link
+ * @to: parameter RAM slot which is the link target
+ *
+ * The originating slot should not be part of any active DMA transfer.
+ */
+void edma_link(unsigned from, unsigned to)
+{
+        if (from >= num_slots)
+                return;
+        if (to >= num_slots)
+                return;
+        edma_parm_modify(PARM_LINK_BCNTRLD, from, 0xffff0000, PARM_OFFSET(to));
+}
+EXPORT_SYMBOL(edma_link);
+
+/**
+ * edma_unlink - cut link from one parameter RAM slot
+ * @from: parameter RAM slot originating the link
+ *
+ * The originating slot should not be part of any active DMA transfer.
+ * Its link is set to 0xffff.
+ */
+void edma_unlink(unsigned from)
+{
+        if (from >= num_slots)
+                return;
+        edma_parm_or(PARM_LINK_BCNTRLD, from, 0xffff);
+}
+EXPORT_SYMBOL(edma_unlink);
+
+/*-----------------------------------------------------------------------*/
+
+/* Parameter RAM operations (ii) -- read/write whole parameter sets */
+
+/**
+ * edma_write_slot - write parameter RAM data for slot
+ * @slot: number of parameter RAM slot being modified
+ * @param: data to be written into parameter RAM slot
+ *
+ * Use this to assign all parameters of a transfer at once.  This
+ * allows more efficient setup of transfers than issuing multiple
+ * calls to set up those parameters in small pieces, and provides
+ * complete control over all transfer options.
+ */
+void edma_write_slot(unsigned slot, const struct edmacc_param *param)
+{
+        if (slot >= num_slots)
+                return;
+        memcpy_toio(edmacc_regs_base + PARM_OFFSET(slot), param, PARM_SIZE);
+}
+EXPORT_SYMBOL(edma_write_slot);
+
+/**
+ * edma_read_slot - read parameter RAM data from slot
+ * @slot: number of parameter RAM slot being copied
+ * @param: where to store copy of parameter RAM data
+ *
+ * Use this to read data from a parameter RAM slot, perhaps to
+ * save them as a template for later reuse.
+ */
+void edma_read_slot(unsigned slot, struct edmacc_param *param)
+{
+        if (slot >= num_slots)
+                return;
+        memcpy_fromio(param, edmacc_regs_base + PARM_OFFSET(slot), PARM_SIZE);
+}
+EXPORT_SYMBOL(edma_read_slot);
+
+/*-----------------------------------------------------------------------*/
+
+/* Various EDMA channel control operations */
+
+/**
+ * edma_pause - pause dma on a channel
+ * @channel: on which edma_start() has been called
+ *
+ * This temporarily disables EDMA hardware events on the specified channel,
+ * preventing them from triggering new transfers on its behalf
+ */
+void edma_pause(unsigned channel)
+{
+        if (channel < num_channels) {
+                unsigned int mask = (1 << (channel & 0x1f));
+
+                edma_shadow0_write_array(SH_EECR, channel >> 5, mask);
+        }
+}
+EXPORT_SYMBOL(edma_pause);
+
+/**
+ * edma_resume - resumes dma on a paused channel
+ * @channel: on which edma_pause() has been called
+ *
+ * This re-enables EDMA hardware events on the specified channel.
+ */
+void edma_resume(unsigned channel)
+{
+        if (channel < num_channels) {
+                unsigned int mask = (1 << (channel & 0x1f));
+
+                edma_shadow0_write_array(SH_EESR, channel >> 5, mask);
+        }
+}
+EXPORT_SYMBOL(edma_resume);
+
+/**
+ * edma_start - start dma on a channel
+ * @channel: channel being activated
+ *
+ * Channels with event associations will be triggered by their hardware
+ * events, and channels without such associations will be triggered by
+ * software.  (At this writing there is no interface for using software
+ * triggers except with channels that don't support hardware triggers.)
+ *
+ * Returns zero on success, else negative errno.
+ */
+int edma_start(unsigned channel)
+{
+        if (channel < num_channels) {
+                int j = channel >> 5;
+                unsigned int mask = (1 << (channel & 0x1f));
+
+                /* EDMA channels without event association */
+                if (test_bit(channel, edma_noevent)) {
+                        pr_debug("EDMA: ESR%d %08x\n", j,
+                                edma_shadow0_read_array(SH_ESR, j));
+                        edma_shadow0_write_array(SH_ESR, j, mask);
+                        return 0;
+                }
+
+                /* EDMA channel with event association */
+                pr_debug("EDMA: ER%d %08x\n", j,
+                        edma_shadow0_read_array(SH_ER, j));
+                /* Clear any pending error */
+                edma_write_array(EDMA_EMCR, j, mask);
+                /* Clear any SER */
+                edma_shadow0_write_array(SH_SECR, j, mask);
+                edma_shadow0_write_array(SH_EESR, j, mask);
+                pr_debug("EDMA: EER%d %08x\n", j,
+                        edma_shadow0_read_array(SH_EER, j));
+                return 0;
+        }
+
+        return -EINVAL;
+}
+EXPORT_SYMBOL(edma_start);
+
+/**
+ * edma_stop - stops dma on the channel passed
+ * @channel: channel being deactivated
+ *
+ * When @lch is a channel, any active transfer is paused and
+ * all pending hardware events are cleared.  The current transfer
+ * may not be resumed, and the channel's Parameter RAM should be
+ * reinitialized before being reused.
+ */
+void edma_stop(unsigned channel)
+{
+        if (channel < num_channels) {
+                int j = channel >> 5;
+                unsigned int mask = (1 << (channel & 0x1f));
+
+                edma_shadow0_write_array(SH_EECR, j, mask);
+                edma_shadow0_write_array(SH_ECR, j, mask);
+                edma_shadow0_write_array(SH_SECR, j, mask);
+                edma_write_array(EDMA_EMCR, j, mask);
+
+                pr_debug("EDMA: EER%d %08x\n", j,
+                                edma_shadow0_read_array(SH_EER, j));
+
+                /* REVISIT:  consider guarding against inappropriate event
+                 * chaining by overwriting with dummy_paramset.
+                 */
+        }
+}
+EXPORT_SYMBOL(edma_stop);
+
+/******************************************************************************
+ *
+ * It cleans ParamEntry qand bring back EDMA to initial state if media has
+ * been removed before EDMA has finished.It is usedful for removable media.
+ * Arguments:
+ *      ch_no     - channel no
+ *
+ * Return: zero on success, or corresponding error no on failure
+ *
+ * FIXME this should not be needed ... edma_stop() should suffice.
+ *
+ *****************************************************************************/
+
+void edma_clean_channel(unsigned channel)
+{
+        if (channel < num_channels) {
+                int j = (channel >> 5);
+                unsigned int mask = 1 << (channel & 0x1f);
+
+                pr_debug("EDMA: EMR%d %08x\n", j,
+                                edma_read_array(EDMA_EMR, j));
+                edma_shadow0_write_array(SH_ECR, j, mask);
+                /* Clear the corresponding EMR bits */
+                edma_write_array(EDMA_EMCR, j, mask);
+                /* Clear any SER */
+                edma_shadow0_write_array(SH_SECR, j, mask);
+                edma_write(EDMA_CCERRCLR, (1 << 16) | 0x3);
+        }
+}
+EXPORT_SYMBOL(edma_clean_channel);
+
+/*
+ * edma_clear_event - clear an outstanding event on the DMA channel
+ * Arguments:
+ *      channel - channel number
+ */
+void edma_clear_event(unsigned channel)
+{
+        if (channel >= num_channels)
+                return;
+        if (channel < 32)
+                edma_write(EDMA_ECR, 1 << channel);
+        else
+                edma_write(EDMA_ECRH, 1 << (channel - 32));
+}
+EXPORT_SYMBOL(edma_clear_event);
+
+/*-----------------------------------------------------------------------*/
+
+static int __init edma_probe(struct platform_device *pdev)
+{
+        struct edma_soc_info    *info = pdev->dev.platform_data;
+        int                     i;
+        int                     status;
+        const s8                *noevent;
+        int                     irq = 0, err_irq = 0;
+        struct resource         *r;
+        resource_size_t         len;
+
+        if (!info)
+                return -ENODEV;
+
+        r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma_cc");
+        if (!r)
+                return -ENODEV;
+
+        len = r->end - r->start + 1;
+
+        r = request_mem_region(r->start, len, r->name);
+        if (!r)
+                return -EBUSY;
+
+        edmacc_regs_base = ioremap(r->start, len);
+        if (!edmacc_regs_base) {
+                status = -EBUSY;
+                goto fail1;
+        }
+
+        num_channels = min_t(unsigned, info->n_channel, EDMA_MAX_DMACH);
+        num_slots = min_t(unsigned, info->n_slot, EDMA_MAX_PARAMENTRY);
+
+        dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n", edmacc_regs_base);
+
+        for (i = 0; i < num_slots; i++)
+                memcpy_toio(edmacc_regs_base + PARM_OFFSET(i),
+                                &dummy_paramset, PARM_SIZE);
+
+        noevent = info->noevent;
+        if (noevent) {
+                while (*noevent != -1)
+                        set_bit(*noevent++, edma_noevent);
+        }
+
+        irq = platform_get_irq(pdev, 0);
+        status = request_irq(irq, dma_irq_handler, 0, "edma", &pdev->dev);
+        if (status < 0) {
+                dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
+                        irq, status);
+                goto fail;
+        }
+
+        err_irq = platform_get_irq(pdev, 1);
+        status = request_irq(err_irq, dma_ccerr_handler, 0,
+                                "edma_error", &pdev->dev);
+        if (status < 0) {
+                dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
+                        err_irq, status);
+                goto fail;
+        }
+
+        if (tc_errs_handled) {
+                status = request_irq(IRQ_TCERRINT0, dma_tc0err_handler, 0,
+                                        "edma_tc0", &pdev->dev);
+                if (status < 0) {
+                        dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
+                                IRQ_TCERRINT0, status);
+                        return status;
+                }
+                status = request_irq(IRQ_TCERRINT, dma_tc1err_handler, 0,
+                                        "edma_tc1", &pdev->dev);
+                if (status < 0) {
+                        dev_dbg(&pdev->dev, "request_irq %d --> %d\n",
+                                IRQ_TCERRINT, status);
+                        return status;
+                }
+        }
+
+        /* Everything lives on transfer controller 1 until otherwise specified.
+         * This way, long transfers on the low priority queue
+         * started by the codec engine will not cause audio defects.
+         */
+        for (i = 0; i < num_channels; i++)
+                map_dmach_queue(i, EVENTQ_1);
+
+        /* Event queue to TC mapping */
+        for (i = 0; queue_tc_mapping[i][0] != -1; i++)
+                map_queue_tc(queue_tc_mapping[i][0], queue_tc_mapping[i][1]);
+
+        /* Event queue priority mapping */
+        for (i = 0; queue_priority_mapping[i][0] != -1; i++)
+                assign_priority_to_queue(queue_priority_mapping[i][0],
+                                         queue_priority_mapping[i][1]);
+
+        for (i = 0; i < info->n_region; i++) {
+                edma_write_array2(EDMA_DRAE, i, 0, 0x0);
+                edma_write_array2(EDMA_DRAE, i, 1, 0x0);
+                edma_write_array(EDMA_QRAE, i, 0x0);
+        }
+
+        return 0;
+
+fail:
+        if (err_irq)
+                free_irq(err_irq, NULL);
+        if (irq)
+                free_irq(irq, NULL);
+        iounmap(edmacc_regs_base);
+fail1:
+        release_mem_region(r->start, len);
+        return status;
+}
+
+
+static struct platform_driver edma_driver = {
+        .driver.name    = "edma",
+};
+
+static int __init edma_init(void)
+{
+        return platform_driver_probe(&edma_driver, edma_probe);
+}
+arch_initcall(edma_init);
+
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index b49e9d092aab..1aba41c6351e 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -20,6 +20,7 @@
 #include <linux/irq.h>
 #include <linux/bitops.h>
 
+#include <mach/cputype.h>
 #include <mach/irqs.h>
 #include <mach/hardware.h>
 #include <mach/gpio.h>
@@ -36,9 +37,10 @@ struct davinci_gpio {
 
 static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
 
+static unsigned __initdata ngpio;
 
 /* create a non-inlined version */
-static struct gpio_controller *__iomem __init gpio2controller(unsigned gpio)
+static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio)
 {
         return __gpio_to_controller(gpio);
 }
@@ -114,9 +116,30 @@ static int __init davinci_gpio_setup(void)
 {
         int i, base;
 
-        for (i = 0, base = 0;
-                        i < ARRAY_SIZE(chips);
-                        i++, base += 32) {
+        /* The gpio banks conceptually expose a segmented bitmap,
+         * and "ngpio" is one more than the largest zero-based
+         * bit index that's valid.
+         */
+        if (cpu_is_davinci_dm355()) {           /* or dm335() */
+                ngpio = 104;
+        } else if (cpu_is_davinci_dm644x()) {   /* or dm337() */
+                ngpio = 71;
+        } else if (cpu_is_davinci_dm646x()) {
+                /* NOTE:  each bank has several "reserved" bits,
+                 * unusable as GPIOs.  Only 33 of the GPIO numbers
+                 * are usable, and we're not rejecting the others.
+                 */
+                ngpio = 43;
+        } else {
+                /* if cpu_is_davinci_dm643x() ngpio = 111 */
+                pr_err("GPIO setup:  how many GPIOs?\n");
+                return -EINVAL;
+        }
+
+        if (WARN_ON(DAVINCI_N_GPIO < ngpio))
+                ngpio = DAVINCI_N_GPIO;
+
+        for (i = 0, base = 0; base < ngpio; i++, base += 32) {
                 chips[i].chip.label = "DaVinci";
 
                 chips[i].chip.direction_input = davinci_direction_in;
@@ -125,7 +148,7 @@ static int __init davinci_gpio_setup(void)
                 chips[i].chip.set = davinci_gpio_set;
 
                 chips[i].chip.base = base;
-                chips[i].chip.ngpio = DAVINCI_N_GPIO - base;
+                chips[i].chip.ngpio = ngpio - base;
                 if (chips[i].chip.ngpio > 32)
                         chips[i].chip.ngpio = 32;
 
@@ -143,11 +166,11 @@ pure_initcall(davinci_gpio_setup);
  * We expect irqs will normally be set up as input pins, but they can also be
  * used as output pins ... which is convenient for testing.
  *
- * NOTE:  GPIO0..GPIO7 also have direct INTC hookups, which work in addition
- * to their GPIOBNK0 irq (but with a bit less overhead).  But we don't have
- * a good way to hook those up ...
+ * NOTE:  The first few GPIOs also have direct INTC hookups in addition
+ * to their GPIOBNK0 irq, with a bit less overhead but less flexibility
+ * on triggering (e.g. no edge options).  We don't try to use those.
  *
- * All those INTC hookups (GPIO0..GPIO7 plus five IRQ banks) can also
+ * All those INTC hookups (direct, plus several IRQ banks) can also
  * serve as EDMA event triggers.
  */
 
@@ -235,29 +258,42 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 }
 
 /*
- * NOTE:  for suspend/resume, probably best to make a sysdev (and class)
- * with its suspend/resume calls hooking into the results of the set_wake()
+ * NOTE:  for suspend/resume, probably best to make a platform_device with
+ * suspend_late/resume_resume calls hooking into results of the set_wake()
  * calls ... so if no gpios are wakeup events the clock can be disabled,
  * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
- * can be set appropriately for GPIOV33 pins.
+ * (dm6446) can be set appropriately for GPIOV33 pins.
  */
 
 static int __init davinci_gpio_irq_setup(void)
 {
         unsigned        gpio, irq, bank;
+        unsigned        bank_irq;
         struct clk      *clk;
+        u32             binten = 0;
+
+        if (cpu_is_davinci_dm355()) {           /* or dm335() */
+                bank_irq = IRQ_DM355_GPIOBNK0;
+        } else if (cpu_is_davinci_dm644x()) {
+                bank_irq = IRQ_GPIOBNK0;
+        } else if (cpu_is_davinci_dm646x()) {
+                bank_irq = IRQ_DM646X_GPIOBNK0;
+        } else {
+                printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
+                return -EINVAL;
+        }
 
         clk = clk_get(NULL, "gpio");
         if (IS_ERR(clk)) {
                 printk(KERN_ERR "Error %ld getting gpio clock?\n",
                        PTR_ERR(clk));
-                return 0;
+                return PTR_ERR(clk);
         }
-
         clk_enable(clk);
 
-        for (gpio = 0, irq = gpio_to_irq(0), bank = IRQ_GPIOBNK0;
-             gpio < DAVINCI_N_GPIO; bank++) {
+        for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
+                        gpio < ngpio;
+                        bank++, bank_irq++) {
                 struct gpio_controller  *__iomem g = gpio2controller(gpio);
                 unsigned                i;
 
@@ -265,28 +301,28 @@ static int __init davinci_gpio_irq_setup(void)
                 __raw_writel(~0, &g->clr_rising);
 
                 /* set up all irqs in this bank */
-                set_irq_chained_handler(bank, gpio_irq_handler);
-                set_irq_chip_data(bank, g);
-                set_irq_data(bank, (void *)irq);
+                set_irq_chained_handler(bank_irq, gpio_irq_handler);
+                set_irq_chip_data(bank_irq, g);
+                set_irq_data(bank_irq, (void *)irq);
 
-                for (i = 0; i < 16 && gpio < DAVINCI_N_GPIO;
-                     i++, irq++, gpio++) {
+                for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
                         set_irq_chip(irq, &gpio_irqchip);
                         set_irq_chip_data(irq, g);
                         set_irq_handler(irq, handle_simple_irq);
                         set_irq_flags(irq, IRQF_VALID);
                 }
+
+                binten |= BIT(bank);
         }
 
         /* BINTEN -- per-bank interrupt enable. genirq would also let these
          * bits be set/cleared dynamically.
          */
-        __raw_writel(0x1f, (void *__iomem)
+        __raw_writel(binten, (void *__iomem)
                      IO_ADDRESS(DAVINCI_GPIO_BASE + 0x08));
 
         printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
 
         return 0;
 }
-
 arch_initcall(davinci_gpio_irq_setup);
diff --git a/arch/arm/mach-davinci/id.c b/arch/arm/mach-davinci/id.c
index bf067d604918..018b994cd794 100644
--- a/arch/arm/mach-davinci/id.c
+++ b/arch/arm/mach-davinci/id.c
@@ -15,7 +15,9 @@
 #include <linux/init.h>
 #include <linux/io.h>
 
-#define JTAG_ID_BASE            0x01c40028
+#define JTAG_ID_BASE            IO_ADDRESS(0x01c40028)
+
+static unsigned int davinci_revision;
 
 struct davinci_id {
         u8      variant;        /* JTAG ID bits 31:28 */
@@ -33,6 +35,20 @@ static struct davinci_id davinci_ids[] __initdata = {
                 .manufacturer = 0x017,
                 .type         = 0x64460000,
         },
+        {
+                /* DM646X */
+                .part_no      = 0xb770,
+                .variant      = 0x0,
+                .manufacturer = 0x017,
+                .type         = 0x64670000,
+        },
+        {
+                /* DM355 */
+                .part_no        = 0xb73b,
+                .variant        = 0x0,
+                .manufacturer   = 0x00f,
+                .type           = 0x03550000,
+        },
 };
 
 /*
@@ -42,7 +58,7 @@ static u16 __init davinci_get_part_no(void)
 {
         u32 dev_id, part_no;
 
-        dev_id = davinci_readl(JTAG_ID_BASE);
+        dev_id = __raw_readl(JTAG_ID_BASE);
 
         part_no = ((dev_id >> 12) & 0xffff);
 
@@ -56,13 +72,19 @@ static u8 __init davinci_get_variant(void)
 {
         u32 variant;
 
-        variant = davinci_readl(JTAG_ID_BASE);
+        variant = __raw_readl(JTAG_ID_BASE);
 
         variant = (variant >> 28) & 0xf;
 
         return variant;
 }
 
+unsigned int davinci_rev(void)
+{
+        return davinci_revision >> 16;
+}
+EXPORT_SYMBOL(davinci_rev);
+
 void __init davinci_check_revision(void)
 {
         int i;
@@ -75,7 +97,7 @@ void __init davinci_check_revision(void)
         /* First check only the major version in a safe way */
         for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) {
                 if (part_no == (davinci_ids[i].part_no)) {
-                        system_rev = davinci_ids[i].type;
+                        davinci_revision = davinci_ids[i].type;
                         break;
                 }
         }
@@ -84,10 +106,11 @@ void __init davinci_check_revision(void)
         for (i = 0; i < ARRAY_SIZE(davinci_ids); i++) {
                 if (part_no == davinci_ids[i].part_no &&
                     variant == davinci_ids[i].variant) {
-                        system_rev = davinci_ids[i].type;
+                        davinci_revision = davinci_ids[i].type;
                         break;
                 }
         }
 
-        printk("DaVinci DM%04x variant 0x%x\n", system_rev >> 16, variant);
+        printk(KERN_INFO "DaVinci DM%04x variant 0x%x\n",
+               davinci_rev(), variant);
 }
diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h
new file mode 100644
index 000000000000..e0abc437d796
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/asp.h
@@ -0,0 +1,25 @@
+/*
+ * <mach/asp.h> - DaVinci Audio Serial Port support
+ */
+#ifndef __ASM_ARCH_DAVINCI_ASP_H
+#define __ASM_ARCH_DAVINCI_ASP_H
+
+#include <mach/irqs.h>
+
+/* Bases of register banks */
+#define DAVINCI_ASP0_BASE       0x01E02000
+#define DAVINCI_ASP1_BASE       0x01E04000
+
+/* EDMA channels */
+#define DAVINCI_DMA_ASP0_TX     2
+#define DAVINCI_DMA_ASP0_RX     3
+#define DAVINCI_DMA_ASP1_TX     8
+#define DAVINCI_DMA_ASP1_RX     9
+
+/* Interrupts */
+#define DAVINCI_ASP0_RX_INT     IRQ_MBRINT
+#define DAVINCI_ASP0_TX_INT     IRQ_MBXINT
+#define DAVINCI_ASP1_RX_INT     IRQ_MBRINT
+#define DAVINCI_ASP1_TX_INT     IRQ_MBXINT
+
+#endif /* __ASM_ARCH_DAVINCI_ASP_H */
diff --git a/arch/arm/mach-davinci/include/mach/board-dm6446evm.h b/arch/arm/mach-davinci/include/mach/board-dm6446evm.h
new file mode 100644
index 000000000000..3216f21c1238
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/board-dm6446evm.h
@@ -0,0 +1,20 @@
+/*
+ * DaVinci DM6446 EVM board specific headers
+ *
+ * Author: Kevin Hilman, Deep Root Systems, LLC
+ *
+ * 2007 (c) Deep Root Systems, LLC. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or ifndef.
+ */
+
+#ifndef _MACH_DAVINCI_DM6446EVM_H
+#define _MACH_DAVINCI_DM6446EVM_H
+
+#include <linux/types.h>
+
+int dm6446evm_eeprom_read(char *buf, off_t off, size_t count);
+int dm6446evm_eeprom_write(char *buf, off_t off, size_t count);
+
+#endif
diff --git a/arch/arm/mach-davinci/include/mach/clkdev.h b/arch/arm/mach-davinci/include/mach/clkdev.h
new file mode 100644
index 000000000000..730c49d1ebd8
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/clkdev.h
@@ -0,0 +1,13 @@
+#ifndef __MACH_CLKDEV_H
+#define __MACH_CLKDEV_H
+
+static inline int __clk_get(struct clk *clk)
+{
+        return 1;
+}
+
+static inline void __clk_put(struct clk *clk)
+{
+}
+
+#endif
diff --git a/arch/arm/mach-davinci/include/mach/clock.h b/arch/arm/mach-davinci/include/mach/clock.h
index 38bdd49bc181..a3b040219876 100644
--- a/arch/arm/mach-davinci/include/mach/clock.h
+++ b/arch/arm/mach-davinci/include/mach/clock.h
@@ -17,6 +17,5 @@ struct clk;
 
 extern int clk_register(struct clk *clk);
 extern void clk_unregister(struct clk *clk);
-extern int davinci_clk_init(void);
 
 #endif
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 4b522e5c70ec..191770976250 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -16,6 +16,12 @@ struct sys_timer;
 
 extern struct sys_timer davinci_timer;
 
+extern void davinci_irq_init(void);
+extern void davinci_map_common_io(void);
+
+/* parameters describe VBUS sourcing for host mode */
+extern void setup_usb(unsigned mA, unsigned potpgt_msec);
+
 /* parameters describe VBUS sourcing for host mode */
 extern void setup_usb(unsigned mA, unsigned potpgt_msec);
 
diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
new file mode 100644
index 000000000000..27cfb1b3a662
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/cputype.h
@@ -0,0 +1,49 @@
+/*
+ * DaVinci CPU type detection
+ *
+ * Author: Kevin Hilman, Deep Root Systems, LLC
+ *
+ * Defines the cpu_is_*() macros for runtime detection of DaVinci
+ * device type.  In addtion, if support for a given device is not
+ * compiled in to the kernel, the macros return 0 so that
+ * resulting code can be optimized out.
+ *
+ * 2009 (c) Deep Root Systems, LLC. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef _ASM_ARCH_CPU_H
+#define _ASM_ARCH_CPU_H
+
+extern unsigned int davinci_rev(void);
+
+#define IS_DAVINCI_CPU(type, id)                        \
+static inline int is_davinci_dm ##type(void)            \
+{                                                       \
+        return (davinci_rev() == (id)) ? 1 : 0;         \
+}
+
+IS_DAVINCI_CPU(644x, 0x6446)
+IS_DAVINCI_CPU(646x, 0x6467)
+IS_DAVINCI_CPU(355, 0x355)
+
+#ifdef CONFIG_ARCH_DAVINCI_DM644x
+#define cpu_is_davinci_dm644x() is_davinci_dm644x()
+#else
+#define cpu_is_davinci_dm644x() 0
+#endif
+
+#ifdef CONFIG_ARCH_DAVINCI_DM646x
+#define cpu_is_davinci_dm646x() is_davinci_dm646x()
+#else
+#define cpu_is_davinci_dm646x() 0
+#endif
+
+#ifdef CONFIG_ARCH_DAVINCI_DM355
+#define cpu_is_davinci_dm355() is_davinci_dm355()
+#else
+#define cpu_is_davinci_dm355() 0
+#endif
+
+#endif
diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h
new file mode 100644
index 000000000000..3dcb9f4e58b4
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/dm644x.h
@@ -0,0 +1,37 @@
+/*
+ * This file contains the processor specific definitions
+ * of the TI DM644x.
+ *
+ * Copyright (C) 2008 Texas Instruments.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+#ifndef __ASM_ARCH_DM644X_H
+#define __ASM_ARCH_DM644X_H
+
+#include <linux/platform_device.h>
+#include <mach/hardware.h>
+
+#define DM644X_EMAC_BASE                (0x01C80000)
+#define DM644X_EMAC_CNTRL_OFFSET        (0x0000)
+#define DM644X_EMAC_CNTRL_MOD_OFFSET    (0x1000)
+#define DM644X_EMAC_CNTRL_RAM_OFFSET    (0x2000)
+#define DM644X_EMAC_MDIO_OFFSET         (0x4000)
+#define DM644X_EMAC_CNTRL_RAM_SIZE      (0x2000)
+
+void __init dm644x_init(void);
+
+#endif /* __ASM_ARCH_DM644X_H */
diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h
new file mode 100644
index 000000000000..f6fc5396dafc
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/edma.h
@@ -0,0 +1,228 @@
+/*
+ *  TI DAVINCI dma definitions
+ *
+ *  Copyright (C) 2006-2009 Texas Instruments.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+/*
+ * This EDMA3 programming framework exposes two basic kinds of resource:
+ *
+ *  Channel     Triggers transfers, usually from a hardware event but
+ *              also manually or by "chaining" from DMA completions.
+ *              Each channel is coupled to a Parameter RAM (PaRAM) slot.
+ *
+ *  Slot        Each PaRAM slot holds a DMA transfer descriptor (PaRAM
+ *              "set"), source and destination addresses, a link to a
+ *              next PaRAM slot (if any), options for the transfer, and
+ *              instructions for updating those addresses.  There are
+ *              more than twice as many slots as event channels.
+ *
+ * Each PaRAM set describes a sequence of transfers, either for one large
+ * buffer or for several discontiguous smaller buffers.  An EDMA transfer
+ * is driven only from a channel, which performs the transfers specified
+ * in its PaRAM slot until there are no more transfers.  When that last
+ * transfer completes, the "link" field may be used to reload the channel's
+ * PaRAM slot with a new transfer descriptor.
+ *
+ * The EDMA Channel Controller (CC) maps requests from channels into physical
+ * Transfer Controller (TC) requests when the channel triggers (by hardware
+ * or software events, or by chaining).  The two physical DMA channels provided
+ * by the TCs are thus shared by many logical channels.
+ *
+ * DaVinci hardware also has a "QDMA" mechanism which is not currently
+ * supported through this interface.  (DSP firmware uses it though.)
+ */
+
+#ifndef EDMA_H_
+#define EDMA_H_
+
+/* PaRAM slots are laid out like this */
+struct edmacc_param {
+        unsigned int opt;
+        unsigned int src;
+        unsigned int a_b_cnt;
+        unsigned int dst;
+        unsigned int src_dst_bidx;
+        unsigned int link_bcntrld;
+        unsigned int src_dst_cidx;
+        unsigned int ccnt;
+};
+
+#define CCINT0_INTERRUPT     16
+#define CCERRINT_INTERRUPT   17
+#define TCERRINT0_INTERRUPT   18
+#define TCERRINT1_INTERRUPT   19
+
+/* fields in edmacc_param.opt */
+#define SAM             BIT(0)
+#define DAM             BIT(1)
+#define SYNCDIM         BIT(2)
+#define STATIC          BIT(3)
+#define EDMA_FWID       (0x07 << 8)
+#define TCCMODE         BIT(11)
+#define EDMA_TCC(t)     ((t) << 12)
+#define TCINTEN         BIT(20)
+#define ITCINTEN        BIT(21)
+#define TCCHEN          BIT(22)
+#define ITCCHEN         BIT(23)
+
+#define TRWORD (0x7<<2)
+#define PAENTRY (0x1ff<<5)
+
+/* Drivers should avoid using these symbolic names for dm644x
+ * channels, and use platform_device IORESOURCE_DMA resources
+ * instead.  (Other DaVinci chips have different peripherals
+ * and thus have different DMA channel mappings.)
+ */
+#define DAVINCI_DMA_MCBSP_TX              2
+#define DAVINCI_DMA_MCBSP_RX              3
+#define DAVINCI_DMA_VPSS_HIST             4
+#define DAVINCI_DMA_VPSS_H3A              5
+#define DAVINCI_DMA_VPSS_PRVU             6
+#define DAVINCI_DMA_VPSS_RSZ              7
+#define DAVINCI_DMA_IMCOP_IMXINT          8
+#define DAVINCI_DMA_IMCOP_VLCDINT         9
+#define DAVINCI_DMA_IMCO_PASQINT         10
+#define DAVINCI_DMA_IMCOP_DSQINT         11
+#define DAVINCI_DMA_SPI_SPIX             16
+#define DAVINCI_DMA_SPI_SPIR             17
+#define DAVINCI_DMA_UART0_URXEVT0        18
+#define DAVINCI_DMA_UART0_UTXEVT0        19
+#define DAVINCI_DMA_UART1_URXEVT1        20
+#define DAVINCI_DMA_UART1_UTXEVT1        21
+#define DAVINCI_DMA_UART2_URXEVT2        22
+#define DAVINCI_DMA_UART2_UTXEVT2        23
+#define DAVINCI_DMA_MEMSTK_MSEVT         24
+#define DAVINCI_DMA_MMCRXEVT             26
+#define DAVINCI_DMA_MMCTXEVT             27
+#define DAVINCI_DMA_I2C_ICREVT           28
+#define DAVINCI_DMA_I2C_ICXEVT           29
+#define DAVINCI_DMA_GPIO_GPINT0          32
+#define DAVINCI_DMA_GPIO_GPINT1          33
+#define DAVINCI_DMA_GPIO_GPINT2          34
+#define DAVINCI_DMA_GPIO_GPINT3          35
+#define DAVINCI_DMA_GPIO_GPINT4          36
+#define DAVINCI_DMA_GPIO_GPINT5          37
+#define DAVINCI_DMA_GPIO_GPINT6          38
+#define DAVINCI_DMA_GPIO_GPINT7          39
+#define DAVINCI_DMA_GPIO_GPBNKINT0       40
+#define DAVINCI_DMA_GPIO_GPBNKINT1       41
+#define DAVINCI_DMA_GPIO_GPBNKINT2       42
+#define DAVINCI_DMA_GPIO_GPBNKINT3       43
+#define DAVINCI_DMA_GPIO_GPBNKINT4       44
+#define DAVINCI_DMA_TIMER0_TINT0         48
+#define DAVINCI_DMA_TIMER1_TINT1         49
+#define DAVINCI_DMA_TIMER2_TINT2         50
+#define DAVINCI_DMA_TIMER3_TINT3         51
+#define DAVINCI_DMA_PWM0                 52
+#define DAVINCI_DMA_PWM1                 53
+#define DAVINCI_DMA_PWM2                 54
+
+/*ch_status paramater of callback function possible values*/
+#define DMA_COMPLETE 1
+#define DMA_CC_ERROR 2
+#define DMA_TC1_ERROR 3
+#define DMA_TC2_ERROR 4
+
+enum address_mode {
+        INCR = 0,
+        FIFO = 1
+};
+
+enum fifo_width {
+        W8BIT = 0,
+        W16BIT = 1,
+        W32BIT = 2,
+        W64BIT = 3,
+        W128BIT = 4,
+        W256BIT = 5
+};
+
+enum dma_event_q {
+        EVENTQ_0 = 0,
+        EVENTQ_1 = 1,
+        EVENTQ_DEFAULT = -1
+};
+
+enum sync_dimension {
+        ASYNC = 0,
+        ABSYNC = 1
+};
+
+#define EDMA_CHANNEL_ANY                -1      /* for edma_alloc_channel() */
+#define EDMA_SLOT_ANY                   -1      /* for edma_alloc_slot() */
+
+/* alloc/free DMA channels and their dedicated parameter RAM slots */
+int edma_alloc_channel(int channel,
+        void (*callback)(unsigned channel, u16 ch_status, void *data),
+        void *data, enum dma_event_q);
+void edma_free_channel(unsigned channel);
+
+/* alloc/free parameter RAM slots */
+int edma_alloc_slot(int slot);
+void edma_free_slot(unsigned slot);
+
+/* calls that operate on part of a parameter RAM slot */
+void edma_set_src(unsigned slot, dma_addr_t src_port,
+                                enum address_mode mode, enum fifo_width);
+void edma_set_dest(unsigned slot, dma_addr_t dest_port,
+                                 enum address_mode mode, enum fifo_width);
+void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst);
+void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
+void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
+void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
+                u16 bcnt_rld, enum sync_dimension sync_mode);
+void edma_link(unsigned from, unsigned to);
+void edma_unlink(unsigned from);
+
+/* calls that operate on an entire parameter RAM slot */
+void edma_write_slot(unsigned slot, const struct edmacc_param *params);
+void edma_read_slot(unsigned slot, struct edmacc_param *params);
+
+/* channel control operations */
+int edma_start(unsigned channel);
+void edma_stop(unsigned channel);
+void edma_clean_channel(unsigned channel);
+void edma_clear_event(unsigned channel);
+void edma_pause(unsigned channel);
+void edma_resume(unsigned channel);
+
+/* UNRELATED TO DMA */
+int davinci_alloc_iram(unsigned size);
+void davinci_free_iram(unsigned addr, unsigned size);
+
+/* platform_data for EDMA driver */
+struct edma_soc_info {
+
+        /* how many dma resources of each type */
+        unsigned        n_channel;
+        unsigned        n_region;
+        unsigned        n_slot;
+        unsigned        n_tc;
+
+        /* list of channels with no even trigger; terminated by "-1" */
+        const s8        *noevent;
+};
+
+#endif
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index b456f079f43f..efe3281364e6 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -15,9 +15,11 @@
 
 #include <linux/io.h>
 #include <asm-generic/gpio.h>
-#include <mach/hardware.h>
+
 #include <mach/irqs.h>
 
+#define DAVINCI_GPIO_BASE 0x01C67000
+
 /*
  * basic gpio routines
  *
@@ -26,23 +28,18 @@
  * go through boot loaders.
  *
  * the gpio clock will be turned on when gpios are used, and you may also
- * need to pay attention to PINMUX0 and PINMUX1 to be sure those pins are
+ * need to pay attention to PINMUX registers to be sure those pins are
  * used as gpios, not with other peripherals.
  *
  * On-chip GPIOs are numbered 0..(DAVINCI_N_GPIO-1).  For documentation,
- * and maybe for later updates, code should write GPIO(N) or:
- *  - GPIOV18(N) for 1.8V pins, N in 0..53; same as GPIO(0)..GPIO(53)
- *  - GPIOV33(N) for 3.3V pins, N in 0..17; same as GPIO(54)..GPIO(70)
- *
- * For GPIO IRQs use gpio_to_irq(GPIO(N)) or gpio_to_irq(GPIOV33(N)) etc
- * for now, that's != GPIO(N)
+ * and maybe for later updates, code may write GPIO(N).  These may be
+ * all 1.8V signals, all 3.3V ones, or a mix of the two.  A given chip
+ * may not support all the GPIOs in that range.
  *
  * GPIOs can also be on external chips, numbered after the ones built-in
  * to the DaVinci chip.  For now, they won't be usable as IRQ sources.
  */
-#define GPIO(X)         (X)             /* 0 <= X <= 70 */
-#define GPIOV18(X)      (X)             /* 1.8V i/o; 0 <= X <= 53 */
-#define GPIOV33(X)      ((X)+54)        /* 3.3V i/o; 0 <= X <= 17 */
+#define GPIO(X)         (X)             /* 0 <= X <= (DAVINCI_N_GPIO - 1) */
 
 struct gpio_controller {
         u32     dir;
@@ -71,12 +68,14 @@ __gpio_to_controller(unsigned gpio)
 {
         void *__iomem ptr;
 
-        if (gpio < 32)
+        if (gpio < 32 * 1)
                 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10);
-        else if (gpio < 64)
+        else if (gpio < 32 * 2)
                 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38);
-        else if (gpio < DAVINCI_N_GPIO)
+        else if (gpio < 32 * 3)
                 ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60);
+        else if (gpio < 32 * 4)
+                ptr = IO_ADDRESS(DAVINCI_GPIO_BASE + 0x88);
         else
                 ptr = NULL;
         return ptr;
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h
index a2e8969afaca..48c77934d519 100644
--- a/arch/arm/mach-davinci/include/mach/hardware.h
+++ b/arch/arm/mach-davinci/include/mach/hardware.h
@@ -1,9 +1,9 @@
 /*
- * Common hardware definitions
+ * Hardware definitions common to all DaVinci family processors
  *
- * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
+ * Author: Kevin Hilman, Deep Root Systems, LLC
  *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * 2007 (c) Deep Root Systems, LLC. This file is licensed under
  * the terms of the GNU General Public License version 2. This program
  * is licensed "as is" without any warranty of any kind, whether express
  * or implied.
@@ -12,41 +12,16 @@
 #define __ASM_ARCH_HARDWARE_H
 
 /*
- * Base register addresses
+ * Before you add anything to ths file:
+ *
+ * This header is for defines common to ALL DaVinci family chips.
+ * Anything that is chip specific should go in <chipname>.h,
+ * and the chip/board init code should then explicitly include
+ * <chipname>.h
  */
-#define DAVINCI_DMA_3PCC_BASE                   (0x01C00000)
-#define DAVINCI_DMA_3PTC0_BASE                  (0x01C10000)
-#define DAVINCI_DMA_3PTC1_BASE                  (0x01C10400)
-#define DAVINCI_I2C_BASE                        (0x01C21000)
-#define DAVINCI_PWM0_BASE                       (0x01C22000)
-#define DAVINCI_PWM1_BASE                       (0x01C22400)
-#define DAVINCI_PWM2_BASE                       (0x01C22800)
-#define DAVINCI_SYSTEM_MODULE_BASE              (0x01C40000)
-#define DAVINCI_PLL_CNTRL0_BASE                 (0x01C40800)
-#define DAVINCI_PLL_CNTRL1_BASE                 (0x01C40C00)
-#define DAVINCI_PWR_SLEEP_CNTRL_BASE            (0x01C41000)
-#define DAVINCI_SYSTEM_DFT_BASE                 (0x01C42000)
-#define DAVINCI_IEEE1394_BASE                   (0x01C60000)
-#define DAVINCI_USB_OTG_BASE                    (0x01C64000)
-#define DAVINCI_CFC_ATA_BASE                    (0x01C66000)
-#define DAVINCI_SPI_BASE                        (0x01C66800)
-#define DAVINCI_GPIO_BASE                       (0x01C67000)
-#define DAVINCI_UHPI_BASE                       (0x01C67800)
-#define DAVINCI_VPSS_REGS_BASE                  (0x01C70000)
-#define DAVINCI_EMAC_CNTRL_REGS_BASE            (0x01C80000)
-#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE    (0x01C81000)
-#define DAVINCI_EMAC_WRAPPER_RAM_BASE           (0x01C82000)
-#define DAVINCI_MDIO_CNTRL_REGS_BASE            (0x01C84000)
-#define DAVINCI_IMCOP_BASE                      (0x01CC0000)
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE           (0x01E00000)
-#define DAVINCI_VLYNQ_BASE                      (0x01E01000)
-#define DAVINCI_MCBSP_BASE                      (0x01E02000)
-#define DAVINCI_MMC_SD_BASE                     (0x01E10000)
-#define DAVINCI_MS_BASE                         (0x01E20000)
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE        (0x02000000)
-#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE        (0x04000000)
-#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE        (0x06000000)
-#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE        (0x08000000)
-#define DAVINCI_VLYNQ_REMOTE_BASE               (0x0C000000)
+#define DAVINCI_SYSTEM_MODULE_BASE        0x01C40000
+
+/* System control register offsets */
+#define DM64XX_VDD3P3V_PWDN     0x48
 
 #endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h
index a48795fd2417..2479785405af 100644
--- a/arch/arm/mach-davinci/include/mach/io.h
+++ b/arch/arm/mach-davinci/include/mach/io.h
@@ -40,22 +40,12 @@
 #else
 #define IOMEM(x)                ((void __force __iomem *)(x))
 
-/*
- * Functions to access the DaVinci IO region
- *
- * NOTE: - Use davinci_read/write[bwl] for physical register addresses
- *       - Use __raw_read/write[bwl]() for virtual register addresses
- *       - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses
- *       - DO NOT use hardcoded virtual addresses to allow changing the
- *         IO address space again if needed
- */
-#define davinci_readb(a)        __raw_readb(IO_ADDRESS(a))
-#define davinci_readw(a)        __raw_readw(IO_ADDRESS(a))
-#define davinci_readl(a)        __raw_readl(IO_ADDRESS(a))
+#define __arch_ioremap(p, s, t) davinci_ioremap(p, s, t)
+#define __arch_iounmap(v)       davinci_iounmap(v)
 
-#define davinci_writeb(v, a)    __raw_writeb(v, IO_ADDRESS(a))
-#define davinci_writew(v, a)    __raw_writew(v, IO_ADDRESS(a))
-#define davinci_writel(v, a)    __raw_writel(v, IO_ADDRESS(a))
+void __iomem *davinci_ioremap(unsigned long phys, size_t size,
+                              unsigned int type);
+void davinci_iounmap(volatile void __iomem *addr);
 
 #endif /* __ASSEMBLER__ */
 #endif /* __ASM_ARCH_IO_H */
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index f4c5ca6da9f4..18066074c995 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -96,10 +96,111 @@
 #define IRQ_EMUINT       63
 
 #define DAVINCI_N_AINTC_IRQ     64
-#define DAVINCI_N_GPIO          71
+#define DAVINCI_N_GPIO          104
 
 #define NR_IRQS                 (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO)
 
 #define ARCH_TIMER_IRQ IRQ_TINT1_TINT34
 
+/* DaVinci DM6467-specific Interrupts */
+#define IRQ_DM646X_VP_VERTINT0  0
+#define IRQ_DM646X_VP_VERTINT1  1
+#define IRQ_DM646X_VP_VERTINT2  2
+#define IRQ_DM646X_VP_VERTINT3  3
+#define IRQ_DM646X_VP_ERRINT    4
+#define IRQ_DM646X_RESERVED_1   5
+#define IRQ_DM646X_RESERVED_2   6
+#define IRQ_DM646X_WDINT        7
+#define IRQ_DM646X_CRGENINT0    8
+#define IRQ_DM646X_CRGENINT1    9
+#define IRQ_DM646X_TSIFINT0     10
+#define IRQ_DM646X_TSIFINT1     11
+#define IRQ_DM646X_VDCEINT      12
+#define IRQ_DM646X_USBINT       13
+#define IRQ_DM646X_USBDMAINT    14
+#define IRQ_DM646X_PCIINT       15
+#define IRQ_DM646X_TCERRINT2    20
+#define IRQ_DM646X_TCERRINT3    21
+#define IRQ_DM646X_IDE          22
+#define IRQ_DM646X_HPIINT       23
+#define IRQ_DM646X_EMACRXTHINT  24
+#define IRQ_DM646X_EMACRXINT    25
+#define IRQ_DM646X_EMACTXINT    26
+#define IRQ_DM646X_EMACMISCINT  27
+#define IRQ_DM646X_MCASP0TXINT  28
+#define IRQ_DM646X_MCASP0RXINT  29
+#define IRQ_DM646X_RESERVED_3   31
+#define IRQ_DM646X_MCASP1TXINT  32
+#define IRQ_DM646X_VLQINT       38
+#define IRQ_DM646X_UARTINT2     42
+#define IRQ_DM646X_SPINT0       43
+#define IRQ_DM646X_SPINT1       44
+#define IRQ_DM646X_DSP2ARMINT   45
+#define IRQ_DM646X_RESERVED_4   46
+#define IRQ_DM646X_PSCINT       47
+#define IRQ_DM646X_GPIO0        48
+#define IRQ_DM646X_GPIO1        49
+#define IRQ_DM646X_GPIO2        50
+#define IRQ_DM646X_GPIO3        51
+#define IRQ_DM646X_GPIO4        52
+#define IRQ_DM646X_GPIO5        53
+#define IRQ_DM646X_GPIO6        54
+#define IRQ_DM646X_GPIO7        55
+#define IRQ_DM646X_GPIOBNK0     56
+#define IRQ_DM646X_GPIOBNK1     57
+#define IRQ_DM646X_GPIOBNK2     58
+#define IRQ_DM646X_DDRINT       59
+#define IRQ_DM646X_AEMIFINT     60
+
+/* DaVinci DM355-specific Interrupts */
+#define IRQ_DM355_CCDC_VDINT0   0
+#define IRQ_DM355_CCDC_VDINT1   1
+#define IRQ_DM355_CCDC_VDINT2   2
+#define IRQ_DM355_IPIPE_HST     3
+#define IRQ_DM355_H3AINT        4
+#define IRQ_DM355_IPIPE_SDR     5
+#define IRQ_DM355_IPIPEIFINT    6
+#define IRQ_DM355_OSDINT        7
+#define IRQ_DM355_VENCINT       8
+#define IRQ_DM355_IMCOPINT      11
+#define IRQ_DM355_RTOINT        13
+#define IRQ_DM355_TINT4         13
+#define IRQ_DM355_TINT2_TINT12  13
+#define IRQ_DM355_UARTINT2      14
+#define IRQ_DM355_TINT5         14
+#define IRQ_DM355_TINT2_TINT34  14
+#define IRQ_DM355_TINT6         15
+#define IRQ_DM355_TINT3_TINT12  15
+#define IRQ_DM355_SPINT1_0      17
+#define IRQ_DM355_SPINT1_1      18
+#define IRQ_DM355_SPINT2_0      19
+#define IRQ_DM355_SPINT2_1      21
+#define IRQ_DM355_TINT7         22
+#define IRQ_DM355_TINT3_TINT34  22
+#define IRQ_DM355_SDIOINT0      23
+#define IRQ_DM355_MMCINT0       26
+#define IRQ_DM355_MSINT         26
+#define IRQ_DM355_MMCINT1       27
+#define IRQ_DM355_PWMINT3       28
+#define IRQ_DM355_SDIOINT1      31
+#define IRQ_DM355_SPINT0_0      42
+#define IRQ_DM355_SPINT0_1      43
+#define IRQ_DM355_GPIO0         44
+#define IRQ_DM355_GPIO1         45
+#define IRQ_DM355_GPIO2         46
+#define IRQ_DM355_GPIO3         47
+#define IRQ_DM355_GPIO4         48
+#define IRQ_DM355_GPIO5         49
+#define IRQ_DM355_GPIO6         50
+#define IRQ_DM355_GPIO7         51
+#define IRQ_DM355_GPIO8         52
+#define IRQ_DM355_GPIO9         53
+#define IRQ_DM355_GPIOBNK0      54
+#define IRQ_DM355_GPIOBNK1      55
+#define IRQ_DM355_GPIOBNK2      56
+#define IRQ_DM355_GPIOBNK3      57
+#define IRQ_DM355_GPIOBNK4      58
+#define IRQ_DM355_GPIOBNK5      59
+#define IRQ_DM355_GPIOBNK6      60
+
 #endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index c24b6782804d..bae22cb3e27b 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -1,55 +1,183 @@
 /*
- * DaVinci pin multiplexing defines
+ * Table of the DAVINCI register configurations for the PINMUX combinations
  *
  * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
  *
+ * Based on linux/include/asm-arm/arch-omap/mux.h:
+ * Copyright (C) 2003 - 2005 Nokia Corporation
+ *
+ * Written by Tony Lindgren
+ *
  * 2007 (c) MontaVista Software, Inc. This file is licensed under
  * the terms of the GNU General Public License version 2. This program
  * is licensed "as is" without any warranty of any kind, whether express
  * or implied.
+ *
+ * Copyright (C) 2008 Texas Instruments.
  */
-#ifndef __ASM_ARCH_MUX_H
-#define __ASM_ARCH_MUX_H
-
-#define DAVINCI_MUX_AEAW0       0
-#define DAVINCI_MUX_AEAW1       1
-#define DAVINCI_MUX_AEAW2       2
-#define DAVINCI_MUX_AEAW3       3
-#define DAVINCI_MUX_AEAW4       4
-#define DAVINCI_MUX_AECS4       10
-#define DAVINCI_MUX_AECS5       11
-#define DAVINCI_MUX_VLYNQWD0    12
-#define DAVINCI_MUX_VLYNQWD1    13
-#define DAVINCI_MUX_VLSCREN     14
-#define DAVINCI_MUX_VLYNQEN     15
-#define DAVINCI_MUX_HDIREN      16
-#define DAVINCI_MUX_ATAEN       17
-#define DAVINCI_MUX_RGB666      22
-#define DAVINCI_MUX_RGB888      23
-#define DAVINCI_MUX_LOEEN       24
-#define DAVINCI_MUX_LFLDEN      25
-#define DAVINCI_MUX_CWEN        26
-#define DAVINCI_MUX_CFLDEN      27
-#define DAVINCI_MUX_HPIEN       29
-#define DAVINCI_MUX_1394EN      30
-#define DAVINCI_MUX_EMACEN      31
-
-#define DAVINCI_MUX_LEVEL2      32
-#define DAVINCI_MUX_UART0       (DAVINCI_MUX_LEVEL2 + 0)
-#define DAVINCI_MUX_UART1       (DAVINCI_MUX_LEVEL2 + 1)
-#define DAVINCI_MUX_UART2       (DAVINCI_MUX_LEVEL2 + 2)
-#define DAVINCI_MUX_U2FLO       (DAVINCI_MUX_LEVEL2 + 3)
-#define DAVINCI_MUX_PWM0        (DAVINCI_MUX_LEVEL2 + 4)
-#define DAVINCI_MUX_PWM1        (DAVINCI_MUX_LEVEL2 + 5)
-#define DAVINCI_MUX_PWM2        (DAVINCI_MUX_LEVEL2 + 6)
-#define DAVINCI_MUX_I2C         (DAVINCI_MUX_LEVEL2 + 7)
-#define DAVINCI_MUX_SPI         (DAVINCI_MUX_LEVEL2 + 8)
-#define DAVINCI_MUX_MSTK        (DAVINCI_MUX_LEVEL2 + 9)
-#define DAVINCI_MUX_ASP         (DAVINCI_MUX_LEVEL2 + 10)
-#define DAVINCI_MUX_CLK0        (DAVINCI_MUX_LEVEL2 + 16)
-#define DAVINCI_MUX_CLK1        (DAVINCI_MUX_LEVEL2 + 17)
-#define DAVINCI_MUX_TIMIN       (DAVINCI_MUX_LEVEL2 + 18)
-
-extern void davinci_mux_peripheral(unsigned int mux, unsigned int enable);
-
-#endif /* __ASM_ARCH_MUX_H */
+
+#ifndef __INC_MACH_MUX_H
+#define __INC_MACH_MUX_H
+
+/* System module registers */
+#define PINMUX0                 0x00
+#define PINMUX1                 0x04
+/* dm355 only */
+#define PINMUX2                 0x08
+#define PINMUX3                 0x0c
+#define PINMUX4                 0x10
+#define INTMUX                  0x18
+#define EVTMUX                  0x1c
+
+struct mux_config {
+        const char *name;
+        const char *mux_reg_name;
+        const unsigned char mux_reg;
+        const unsigned char mask_offset;
+        const unsigned char mask;
+        const unsigned char mode;
+        bool debug;
+};
+
+enum davinci_dm644x_index {
+        /* ATA and HDDIR functions */
+        DM644X_HDIREN,
+        DM644X_ATAEN,
+        DM644X_ATAEN_DISABLE,
+
+        /* HPI functions */
+        DM644X_HPIEN_DISABLE,
+
+        /* AEAW functions */
+        DM644X_AEAW,
+
+        /* Memory Stick */
+        DM644X_MSTK,
+
+        /* I2C */
+        DM644X_I2C,
+
+        /* ASP function */
+        DM644X_MCBSP,
+
+        /* UART1 */
+        DM644X_UART1,
+
+        /* UART2 */
+        DM644X_UART2,
+
+        /* PWM0 */
+        DM644X_PWM0,
+
+        /* PWM1 */
+        DM644X_PWM1,
+
+        /* PWM2 */
+        DM644X_PWM2,
+
+        /* VLYNQ function */
+        DM644X_VLYNQEN,
+        DM644X_VLSCREN,
+        DM644X_VLYNQWD,
+
+        /* EMAC and MDIO function */
+        DM644X_EMACEN,
+
+        /* GPIO3V[0:16] pins */
+        DM644X_GPIO3V,
+
+        /* GPIO pins */
+        DM644X_GPIO0,
+        DM644X_GPIO3,
+        DM644X_GPIO43_44,
+        DM644X_GPIO46_47,
+
+        /* VPBE */
+        DM644X_RGB666,
+
+        /* LCD */
+        DM644X_LOEEN,
+        DM644X_LFLDEN,
+};
+
+enum davinci_dm646x_index {
+        /* ATA function */
+        DM646X_ATAEN,
+
+        /* AUDIO Clock */
+        DM646X_AUDCK1,
+        DM646X_AUDCK0,
+
+        /* CRGEN Control */
+        DM646X_CRGMUX,
+
+        /* VPIF Control */
+        DM646X_STSOMUX_DISABLE,
+        DM646X_STSIMUX_DISABLE,
+        DM646X_PTSOMUX_DISABLE,
+        DM646X_PTSIMUX_DISABLE,
+
+        /* TSIF Control */
+        DM646X_STSOMUX,
+        DM646X_STSIMUX,
+        DM646X_PTSOMUX_PARALLEL,
+        DM646X_PTSIMUX_PARALLEL,
+        DM646X_PTSOMUX_SERIAL,
+        DM646X_PTSIMUX_SERIAL,
+};
+
+enum davinci_dm355_index {
+        /* MMC/SD 0 */
+        DM355_MMCSD0,
+
+        /* MMC/SD 1 */
+        DM355_SD1_CLK,
+        DM355_SD1_CMD,
+        DM355_SD1_DATA3,
+        DM355_SD1_DATA2,
+        DM355_SD1_DATA1,
+        DM355_SD1_DATA0,
+
+        /* I2C */
+        DM355_I2C_SDA,
+        DM355_I2C_SCL,
+
+        /* ASP0 function */
+        DM355_MCBSP0_BDX,
+        DM355_MCBSP0_X,
+        DM355_MCBSP0_BFSX,
+        DM355_MCBSP0_BDR,
+        DM355_MCBSP0_R,
+        DM355_MCBSP0_BFSR,
+
+        /* SPI0 */
+        DM355_SPI0_SDI,
+        DM355_SPI0_SDENA0,
+        DM355_SPI0_SDENA1,
+
+        /* IRQ muxing */
+        DM355_INT_EDMA_CC,
+        DM355_INT_EDMA_TC0_ERR,
+        DM355_INT_EDMA_TC1_ERR,
+
+        /* EDMA event muxing */
+        DM355_EVT8_ASP1_TX,
+        DM355_EVT9_ASP1_RX,
+        DM355_EVT26_MMC0_RX,
+};
+
+#ifdef CONFIG_DAVINCI_MUX
+/* setup pin muxing */
+extern void davinci_mux_init(void);
+extern int davinci_mux_register(const struct mux_config *pins,
+                                unsigned long size);
+extern int davinci_cfg_reg(unsigned long reg_cfg);
+#else
+/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
+static inline void davinci_mux_init(void) {}
+static inline int davinci_mux_register(const struct mux_config *pins,
+                                       unsigned long size) { return 0; }
+static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
+#endif
+
+#endif /* __INC_MACH_MUX_H */
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 4977aa071e1e..55a90d419fac 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -38,8 +38,6 @@
 #define DAVINCI_LPSC_TPTC1          4
 #define DAVINCI_LPSC_EMAC           5
 #define DAVINCI_LPSC_EMAC_WRAPPER   6
-#define DAVINCI_LPSC_MDIO           7
-#define DAVINCI_LPSC_IEEE1394       8
 #define DAVINCI_LPSC_USB            9
 #define DAVINCI_LPSC_ATA            10
 #define DAVINCI_LPSC_VLYNQ          11
@@ -47,7 +45,6 @@
 #define DAVINCI_LPSC_DDR_EMIF       13
 #define DAVINCI_LPSC_AEMIF          14
 #define DAVINCI_LPSC_MMC_SD         15
-#define DAVINCI_LPSC_MEMSTICK       16
 #define DAVINCI_LPSC_McBSP          17
 #define DAVINCI_LPSC_I2C            18
 #define DAVINCI_LPSC_UART0          19
@@ -73,4 +70,54 @@
 #define DAVINCI_LPSC_GEM            39
 #define DAVINCI_LPSC_IMCOP          40
 
+#define DM355_LPSC_TIMER3               5
+#define DM355_LPSC_SPI1                 6
+#define DM355_LPSC_MMC_SD1              7
+#define DM355_LPSC_McBSP1               8
+#define DM355_LPSC_PWM3                 10
+#define DM355_LPSC_SPI2                 11
+#define DM355_LPSC_RTO                  12
+#define DM355_LPSC_VPSS_DAC             41
+
+/*
+ * LPSC Assignments
+ */
+#define DM646X_LPSC_ARM            0
+#define DM646X_LPSC_C64X_CPU       1
+#define DM646X_LPSC_HDVICP0        2
+#define DM646X_LPSC_HDVICP1        3
+#define DM646X_LPSC_TPCC           4
+#define DM646X_LPSC_TPTC0          5
+#define DM646X_LPSC_TPTC1          6
+#define DM646X_LPSC_TPTC2          7
+#define DM646X_LPSC_TPTC3          8
+#define DM646X_LPSC_PCI            13
+#define DM646X_LPSC_EMAC           14
+#define DM646X_LPSC_VDCE           15
+#define DM646X_LPSC_VPSSMSTR       16
+#define DM646X_LPSC_VPSSSLV        17
+#define DM646X_LPSC_TSIF0          18
+#define DM646X_LPSC_TSIF1          19
+#define DM646X_LPSC_DDR_EMIF       20
+#define DM646X_LPSC_AEMIF          21
+#define DM646X_LPSC_McASP0         22
+#define DM646X_LPSC_McASP1         23
+#define DM646X_LPSC_CRGEN0         24
+#define DM646X_LPSC_CRGEN1         25
+#define DM646X_LPSC_UART0          26
+#define DM646X_LPSC_UART1          27
+#define DM646X_LPSC_UART2          28
+#define DM646X_LPSC_PWM0           29
+#define DM646X_LPSC_PWM1           30
+#define DM646X_LPSC_I2C            31
+#define DM646X_LPSC_SPI            32
+#define DM646X_LPSC_GPIO           33
+#define DM646X_LPSC_TIMER0         34
+#define DM646X_LPSC_TIMER1         35
+#define DM646X_LPSC_ARM_INTC       45
+
+extern int davinci_psc_is_clk_active(unsigned int id);
+extern void davinci_psc_config(unsigned int domain, unsigned int id,
+                               char enable);
+
 #endif /* __ASM_ARCH_PSC_H */
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index fb8cb229bfd2..632847d74a1c 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -13,8 +13,23 @@
 
 #include <mach/io.h>
 
-#define DAVINCI_UART0_BASE   (IO_PHYS + 0x20000)
-#define DAVINCI_UART1_BASE   (IO_PHYS + 0x20400)
-#define DAVINCI_UART2_BASE   (IO_PHYS + 0x20800)
+#define DAVINCI_MAX_NR_UARTS    3
+#define DAVINCI_UART0_BASE      (IO_PHYS + 0x20000)
+#define DAVINCI_UART1_BASE      (IO_PHYS + 0x20400)
+#define DAVINCI_UART2_BASE      (IO_PHYS + 0x20800)
+
+#define DM355_UART2_BASE        (IO_PHYS + 0x206000)
+
+/* DaVinci UART register offsets */
+#define UART_DAVINCI_PWREMU             0x0c
+#define UART_DM646X_SCR                 0x10
+#define UART_DM646X_SCR_TX_WATERMARK    0x08
+
+struct davinci_uart_config {
+        /* Bit field of UARTs present; bit 0 --> UART1 */
+        unsigned int enabled_uarts;
+};
+
+extern void davinci_serial_init(struct davinci_uart_config *);
 
 #endif /* __ASM_ARCH_SERIAL_H */
diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c
index 299515f70b8b..a548abb513e2 100644
--- a/arch/arm/mach-davinci/io.c
+++ b/arch/arm/mach-davinci/io.c
@@ -51,7 +51,26 @@ void __init davinci_map_common_io(void)
         davinci_check_revision();
 }
 
-void __init davinci_init_common_hw(void)
+#define BETWEEN(p, st, sz)      ((p) >= (st) && (p) < ((st) + (sz)))
+#define XLATE(p, pst, vst)      ((void __iomem *)((p) - (pst) + (vst)))
+
+/*
+ * Intercept ioremap() requests for addresses in our fixed mapping regions.
+ */
+void __iomem *davinci_ioremap(unsigned long p, size_t size, unsigned int type)
+{
+        if (BETWEEN(p, IO_PHYS, IO_SIZE))
+                return XLATE(p, IO_PHYS, IO_VIRT);
+
+        return __arm_ioremap(p, size, type);
+}
+EXPORT_SYMBOL(davinci_ioremap);
+
+void davinci_iounmap(volatile void __iomem *addr)
 {
-        davinci_clk_init();
+        unsigned long virt = (unsigned long)addr;
+
+        if (virt >= VMALLOC_START && virt < VMALLOC_END)
+                __iounmap(addr);
 }
+EXPORT_SYMBOL(davinci_iounmap);
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index 38021af8359a..5a324c90e291 100644
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -25,6 +25,7 @@
 #include <linux/io.h>
 
 #include <mach/hardware.h>
+#include <mach/cputype.h>
 #include <asm/mach/irq.h>
 
 #define IRQ_BIT(irq)            ((irq) & 0x1f)
@@ -40,14 +41,18 @@
 #define IRQ_INTPRI0_REG_OFFSET  0x0030
 #define IRQ_INTPRI7_REG_OFFSET  0x004C
 
+const u8 *davinci_def_priorities;
+
+#define INTC_BASE IO_ADDRESS(DAVINCI_ARM_INTC_BASE)
+
 static inline unsigned int davinci_irq_readl(int offset)
 {
-        return davinci_readl(DAVINCI_ARM_INTC_BASE + offset);
+        return __raw_readl(INTC_BASE + offset);
 }
 
 static inline void davinci_irq_writel(unsigned long value, int offset)
 {
-        davinci_writel(value, DAVINCI_ARM_INTC_BASE + offset);
+        __raw_writel(value, INTC_BASE + offset);
 }
 
 /* Disable interrupt */
@@ -108,9 +113,8 @@ static struct irq_chip davinci_irq_chip_0 = {
         .unmask = davinci_unmask_irq,
 };
 
-
 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
-static const u8 default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = {
+static const u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = {
         [IRQ_VDINT0]            = 2,
         [IRQ_VDINT1]            = 6,
         [IRQ_VDINT2]            = 6,
@@ -177,11 +181,149 @@ static const u8 default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = {
         [IRQ_EMUINT]            = 7,
 };
 
+static const u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
+        [IRQ_DM646X_VP_VERTINT0]        = 7,
+        [IRQ_DM646X_VP_VERTINT1]        = 7,
+        [IRQ_DM646X_VP_VERTINT2]        = 7,
+        [IRQ_DM646X_VP_VERTINT3]        = 7,
+        [IRQ_DM646X_VP_ERRINT]          = 7,
+        [IRQ_DM646X_RESERVED_1]         = 7,
+        [IRQ_DM646X_RESERVED_2]         = 7,
+        [IRQ_DM646X_WDINT]              = 7,
+        [IRQ_DM646X_CRGENINT0]          = 7,
+        [IRQ_DM646X_CRGENINT1]          = 7,
+        [IRQ_DM646X_TSIFINT0]           = 7,
+        [IRQ_DM646X_TSIFINT1]           = 7,
+        [IRQ_DM646X_VDCEINT]            = 7,
+        [IRQ_DM646X_USBINT]             = 7,
+        [IRQ_DM646X_USBDMAINT]          = 7,
+        [IRQ_DM646X_PCIINT]             = 7,
+        [IRQ_CCINT0]                    = 7,    /* dma */
+        [IRQ_CCERRINT]                  = 7,    /* dma */
+        [IRQ_TCERRINT0]                 = 7,    /* dma */
+        [IRQ_TCERRINT]                  = 7,    /* dma */
+        [IRQ_DM646X_TCERRINT2]          = 7,
+        [IRQ_DM646X_TCERRINT3]          = 7,
+        [IRQ_DM646X_IDE]                = 7,
+        [IRQ_DM646X_HPIINT]             = 7,
+        [IRQ_DM646X_EMACRXTHINT]        = 7,
+        [IRQ_DM646X_EMACRXINT]          = 7,
+        [IRQ_DM646X_EMACTXINT]          = 7,
+        [IRQ_DM646X_EMACMISCINT]        = 7,
+        [IRQ_DM646X_MCASP0TXINT]        = 7,
+        [IRQ_DM646X_MCASP0RXINT]        = 7,
+        [IRQ_AEMIFINT]                  = 7,
+        [IRQ_DM646X_RESERVED_3]         = 7,
+        [IRQ_DM646X_MCASP1TXINT]        = 7,    /* clockevent */
+        [IRQ_TINT0_TINT34]              = 7,    /* clocksource */
+        [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
+        [IRQ_TINT1_TINT34]              = 7,    /* system tick */
+        [IRQ_PWMINT0]                   = 7,
+        [IRQ_PWMINT1]                   = 7,
+        [IRQ_DM646X_VLQINT]             = 7,
+        [IRQ_I2C]                       = 7,
+        [IRQ_UARTINT0]                  = 7,
+        [IRQ_UARTINT1]                  = 7,
+        [IRQ_DM646X_UARTINT2]           = 7,
+        [IRQ_DM646X_SPINT0]             = 7,
+        [IRQ_DM646X_SPINT1]             = 7,
+        [IRQ_DM646X_DSP2ARMINT]         = 7,
+        [IRQ_DM646X_RESERVED_4]         = 7,
+        [IRQ_DM646X_PSCINT]             = 7,
+        [IRQ_DM646X_GPIO0]              = 7,
+        [IRQ_DM646X_GPIO1]              = 7,
+        [IRQ_DM646X_GPIO2]              = 7,
+        [IRQ_DM646X_GPIO3]              = 7,
+        [IRQ_DM646X_GPIO4]              = 7,
+        [IRQ_DM646X_GPIO5]              = 7,
+        [IRQ_DM646X_GPIO6]              = 7,
+        [IRQ_DM646X_GPIO7]              = 7,
+        [IRQ_DM646X_GPIOBNK0]           = 7,
+        [IRQ_DM646X_GPIOBNK1]           = 7,
+        [IRQ_DM646X_GPIOBNK2]           = 7,
+        [IRQ_DM646X_DDRINT]             = 7,
+        [IRQ_DM646X_AEMIFINT]           = 7,
+        [IRQ_COMMTX]                    = 7,
+        [IRQ_COMMRX]                    = 7,
+        [IRQ_EMUINT]                    = 7,
+};
+
+static const u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
+        [IRQ_DM355_CCDC_VDINT0]         = 2,
+        [IRQ_DM355_CCDC_VDINT1]         = 6,
+        [IRQ_DM355_CCDC_VDINT2]         = 6,
+        [IRQ_DM355_IPIPE_HST]           = 6,
+        [IRQ_DM355_H3AINT]              = 6,
+        [IRQ_DM355_IPIPE_SDR]           = 6,
+        [IRQ_DM355_IPIPEIFINT]          = 6,
+        [IRQ_DM355_OSDINT]              = 7,
+        [IRQ_DM355_VENCINT]             = 6,
+        [IRQ_ASQINT]                    = 6,
+        [IRQ_IMXINT]                    = 6,
+        [IRQ_USBINT]                    = 4,
+        [IRQ_DM355_RTOINT]              = 4,
+        [IRQ_DM355_UARTINT2]            = 7,
+        [IRQ_DM355_TINT6]               = 7,
+        [IRQ_CCINT0]                    = 5,    /* dma */
+        [IRQ_CCERRINT]                  = 5,    /* dma */
+        [IRQ_TCERRINT0]                 = 5,    /* dma */
+        [IRQ_TCERRINT]                  = 5,    /* dma */
+        [IRQ_DM355_SPINT2_1]            = 7,
+        [IRQ_DM355_TINT7]               = 4,
+        [IRQ_DM355_SDIOINT0]            = 7,
+        [IRQ_MBXINT]                    = 7,
+        [IRQ_MBRINT]                    = 7,
+        [IRQ_MMCINT]                    = 7,
+        [IRQ_DM355_MMCINT1]             = 7,
+        [IRQ_DM355_PWMINT3]             = 7,
+        [IRQ_DDRINT]                    = 7,
+        [IRQ_AEMIFINT]                  = 7,
+        [IRQ_DM355_SDIOINT1]            = 4,
+        [IRQ_TINT0_TINT12]              = 2,    /* clockevent */
+        [IRQ_TINT0_TINT34]              = 2,    /* clocksource */
+        [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
+        [IRQ_TINT1_TINT34]              = 7,    /* system tick */
+        [IRQ_PWMINT0]                   = 7,
+        [IRQ_PWMINT1]                   = 7,
+        [IRQ_PWMINT2]                   = 7,
+        [IRQ_I2C]                       = 3,
+        [IRQ_UARTINT0]                  = 3,
+        [IRQ_UARTINT1]                  = 3,
+        [IRQ_DM355_SPINT0_0]            = 3,
+        [IRQ_DM355_SPINT0_1]            = 3,
+        [IRQ_DM355_GPIO0]               = 3,
+        [IRQ_DM355_GPIO1]               = 7,
+        [IRQ_DM355_GPIO2]               = 4,
+        [IRQ_DM355_GPIO3]               = 4,
+        [IRQ_DM355_GPIO4]               = 7,
+        [IRQ_DM355_GPIO5]               = 7,
+        [IRQ_DM355_GPIO6]               = 7,
+        [IRQ_DM355_GPIO7]               = 7,
+        [IRQ_DM355_GPIO8]               = 7,
+        [IRQ_DM355_GPIO9]               = 7,
+        [IRQ_DM355_GPIOBNK0]            = 7,
+        [IRQ_DM355_GPIOBNK1]            = 7,
+        [IRQ_DM355_GPIOBNK2]            = 7,
+        [IRQ_DM355_GPIOBNK3]            = 7,
+        [IRQ_DM355_GPIOBNK4]            = 7,
+        [IRQ_DM355_GPIOBNK5]            = 7,
+        [IRQ_DM355_GPIOBNK6]            = 7,
+        [IRQ_COMMTX]                    = 7,
+        [IRQ_COMMRX]                    = 7,
+        [IRQ_EMUINT]                    = 7,
+};
+
 /* ARM Interrupt Controller Initialization */
 void __init davinci_irq_init(void)
 {
         unsigned i;
-        const u8 *priority = default_priorities;
+
+        if (cpu_is_davinci_dm644x())
+                davinci_def_priorities = dm644x_default_priorities;
+        else if (cpu_is_davinci_dm646x())
+                davinci_def_priorities = dm646x_default_priorities;
+        else if (cpu_is_davinci_dm355())
+                davinci_def_priorities = dm355_default_priorities;
 
         /* Clear all interrupt requests */
         davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
@@ -209,8 +351,8 @@ void __init davinci_irq_init(void)
                 unsigned        j;
                 u32             pri;
 
-                for (j = 0, pri = 0; j < 32; j += 4, priority++)
-                        pri |= (*priority & 0x07) << j;
+                for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
+                        pri |= (*davinci_def_priorities & 0x07) << j;
                 davinci_irq_writel(pri, i);
         }
 
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index 8ff9d8aca60b..bbba0b247a44 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -1,41 +1,103 @@
 /*
- * DaVinci pin multiplexing configurations
+ * Utility to set the DAVINCI MUX register from a table in mux.h
  *
  * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
  *
+ * Based on linux/arch/arm/plat-omap/mux.c:
+ * Copyright (C) 2003 - 2005 Nokia Corporation
+ *
+ * Written by Tony Lindgren
+ *
  * 2007 (c) MontaVista Software, Inc. This file is licensed under
  * the terms of the GNU General Public License version 2. This program
  * is licensed "as is" without any warranty of any kind, whether express
  * or implied.
+ *
+ * Copyright (C) 2008 Texas Instruments.
  */
 #include <linux/io.h>
+#include <linux/module.h>
 #include <linux/spinlock.h>
 
 #include <mach/hardware.h>
-
 #include <mach/mux.h>
 
-/* System control register offsets */
-#define PINMUX0         0x00
-#define PINMUX1         0x04
+static const struct mux_config *mux_table;
+static unsigned long pin_table_sz;
+
+int __init davinci_mux_register(const struct mux_config *pins,
+                                unsigned long size)
+{
+        mux_table = pins;
+        pin_table_sz = size;
 
-static DEFINE_SPINLOCK(mux_lock);
+        return 0;
+}
 
-void davinci_mux_peripheral(unsigned int mux, unsigned int enable)
+/*
+ * Sets the DAVINCI MUX register based on the table
+ */
+int __init_or_module davinci_cfg_reg(const unsigned long index)
 {
-        u32 pinmux, muxreg = PINMUX0;
+        static DEFINE_SPINLOCK(mux_spin_lock);
+        void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
+        unsigned long flags;
+        const struct mux_config *cfg;
+        unsigned int reg_orig = 0, reg = 0;
+        unsigned int mask, warn = 0;
+
+        if (!mux_table)
+                BUG();
+
+        if (index >= pin_table_sz) {
+                printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
+                       index, pin_table_sz);
+                dump_stack();
+                return -ENODEV;
+        }
+
+        cfg = &mux_table[index];
+
+        if (cfg->name == NULL) {
+                printk(KERN_ERR "No entry for the specified index\n");
+                return -ENODEV;
+        }
+
+        /* Update the mux register in question */
+        if (cfg->mask) {
+                unsigned        tmp1, tmp2;
+
+                spin_lock_irqsave(&mux_spin_lock, flags);
+                reg_orig = __raw_readl(base + cfg->mux_reg);
+
+                mask = (cfg->mask << cfg->mask_offset);
+                tmp1 = reg_orig & mask;
+                reg = reg_orig & ~mask;
+
+                tmp2 = (cfg->mode << cfg->mask_offset);
+                reg |= tmp2;
+
+                if (tmp1 != tmp2)
+                        warn = 1;
+
+                __raw_writel(reg, base + cfg->mux_reg);
+                spin_unlock_irqrestore(&mux_spin_lock, flags);
+        }
+
+        if (warn) {
+#ifdef CONFIG_DAVINCI_MUX_WARNINGS
+                printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
+#endif
+        }
 
-        if (mux >= DAVINCI_MUX_LEVEL2) {
-                muxreg = PINMUX1;
-                mux -= DAVINCI_MUX_LEVEL2;
+#ifdef CONFIG_DAVINCI_MUX_DEBUG
+        if (cfg->debug || warn) {
+                printk(KERN_WARNING "MUX: Setting register %s\n", cfg->name);
+                printk(KERN_WARNING "      %s (0x%08x) = 0x%08x -> 0x%08x\n",
+                       cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
         }
+#endif
 
-        spin_lock(&mux_lock);
-        pinmux = davinci_readl(DAVINCI_SYSTEM_MODULE_BASE + muxreg);
-        if (enable)
-                pinmux |= (1 << mux);
-        else
-                pinmux &= ~(1 << mux);
-        davinci_writel(pinmux, DAVINCI_SYSTEM_MODULE_BASE + muxreg);
-        spin_unlock(&mux_lock);
+        return 0;
 }
+EXPORT_SYMBOL(davinci_cfg_reg);
diff --git a/arch/arm/mach-davinci/mux.h b/arch/arm/mach-davinci/mux.h
new file mode 100644
index 000000000000..adc869413371
--- /dev/null
+++ b/arch/arm/mach-davinci/mux.h
@@ -0,0 +1,51 @@
+/*
+ * Pin-multiplex helper macros for TI DaVinci family devices
+ *
+ * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Copyright (C) 2008 Texas Instruments.
+ */
+#ifndef _MACH_DAVINCI_MUX_H_
+#define _MACH_DAVINCI_MUX_H_
+
+#include <mach/mux.h>
+
+#define MUX_CFG(soc, desc, muxreg, mode_offset, mode_mask, mux_mode, dbg)\
+[soc##_##desc] = {                                                      \
+                        .name =  #desc,                                 \
+                        .debug = dbg,                                   \
+                        .mux_reg_name = "PINMUX"#muxreg,                \
+                        .mux_reg = PINMUX##muxreg,                      \
+                        .mask_offset = mode_offset,                     \
+                        .mask = mode_mask,                              \
+                        .mode = mux_mode,                               \
+                },
+
+#define INT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg)       \
+[soc##_##desc] = {                                                      \
+                        .name =  #desc,                                 \
+                        .debug = dbg,                                   \
+                        .mux_reg_name = "INTMUX",                       \
+                        .mux_reg = INTMUX,                              \
+                        .mask_offset = mode_offset,                     \
+                        .mask = mode_mask,                              \
+                        .mode = mux_mode,                               \
+                },
+
+#define EVT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg)       \
+[soc##_##desc] = {                                                      \
+                        .name =  #desc,                                 \
+                        .debug = dbg,                                   \
+                        .mux_reg_name = "EVTMUX",                       \
+                        .mux_reg = EVTMUX,                              \
+                        .mask_offset = mode_offset,                     \
+                        .mask = mode_mask,                              \
+                        .mode = mux_mode,                               \
+                },
+
+#endif /* _MACH_DAVINCI_MUX_H */
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index 58754f066d5b..84171abf5f7b 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -23,10 +23,13 @@
 #include <linux/init.h>
 #include <linux/io.h>
 
+#include <mach/cputype.h>
 #include <mach/hardware.h>
 #include <mach/psc.h>
 #include <mach/mux.h>
 
+#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000
+
 /* PSC register offsets */
 #define EPCPR           0x070
 #define PTCMD           0x120
@@ -36,102 +39,61 @@
 #define MDSTAT          0x800
 #define MDCTL           0xA00
 
-/* System control register offsets */
-#define VDD3P3V_PWDN    0x48
+#define MDSTAT_STATE_MASK 0x1f
 
-static void davinci_psc_mux(unsigned int id)
+/* Return nonzero iff the domain's clock is active */
+int __init davinci_psc_is_clk_active(unsigned int id)
 {
-        switch (id) {
-        case DAVINCI_LPSC_ATA:
-                davinci_mux_peripheral(DAVINCI_MUX_HDIREN, 1);
-                davinci_mux_peripheral(DAVINCI_MUX_ATAEN, 1);
-                break;
-        case DAVINCI_LPSC_MMC_SD:
-                /* VDD power manupulations are done in U-Boot for CPMAC
-                 * so applies to MMC as well
-                 */
-                /*Set up the pull regiter for MMC */
-                davinci_writel(0, DAVINCI_SYSTEM_MODULE_BASE + VDD3P3V_PWDN);
-                davinci_mux_peripheral(DAVINCI_MUX_MSTK, 0);
-                break;
-        case DAVINCI_LPSC_I2C:
-                davinci_mux_peripheral(DAVINCI_MUX_I2C, 1);
-                break;
-        case DAVINCI_LPSC_McBSP:
-                davinci_mux_peripheral(DAVINCI_MUX_ASP, 1);
-                break;
-        default:
-                break;
-        }
+        void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE);
+        u32 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
+
+        /* if clocked, state can be "Enable" or "SyncReset" */
+        return mdstat & BIT(12);
 }
 
 /* Enable or disable a PSC domain */
 void davinci_psc_config(unsigned int domain, unsigned int id, char enable)
 {
-        u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl, mdstat_mask;
+        u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl;
+        void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE);
+        u32 next_state = enable ? 0x3 : 0x2; /* 0x3 enables, 0x2 disables */
 
-        mdctl = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id);
-        if (enable)
-                mdctl |= 0x00000003;    /* Enable Module */
-        else
-                mdctl &= 0xFFFFFFF2;    /* Disable Module */
-        davinci_writel(mdctl, DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id);
+        mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
+        mdctl &= ~MDSTAT_STATE_MASK;
+        mdctl |= next_state;
+        __raw_writel(mdctl, psc_base + MDCTL + 4 * id);
 
-        pdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDSTAT);
+        pdstat = __raw_readl(psc_base + PDSTAT);
         if ((pdstat & 0x00000001) == 0) {
-                pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
+                pdctl1 = __raw_readl(psc_base + PDCTL1);
                 pdctl1 |= 0x1;
-                davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
+                __raw_writel(pdctl1, psc_base + PDCTL1);
 
                 ptcmd = 1 << domain;
-                davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD);
+                __raw_writel(ptcmd, psc_base + PTCMD);
 
                 do {
-                        epcpr = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
-                                              EPCPR);
+                        epcpr = __raw_readl(psc_base + EPCPR);
                 } while ((((epcpr >> domain) & 1) == 0));
 
-                pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
+                pdctl1 = __raw_readl(psc_base + PDCTL1);
                 pdctl1 |= 0x100;
-                davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
+                __raw_writel(pdctl1, psc_base + PDCTL1);
 
                 do {
-                        ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
+                        ptstat = __raw_readl(psc_base +
                                                PTSTAT);
                 } while (!(((ptstat >> domain) & 1) == 0));
         } else {
                 ptcmd = 1 << domain;
-                davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD);
+                __raw_writel(ptcmd, psc_base + PTCMD);
 
                 do {
-                        ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
-                                               PTSTAT);
+                        ptstat = __raw_readl(psc_base + PTSTAT);
                 } while (!(((ptstat >> domain) & 1) == 0));
         }
 
-        if (enable)
-                mdstat_mask = 0x3;
-        else
-                mdstat_mask = 0x2;
-
         do {
-                mdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
-                                       MDSTAT + 4 * id);
-        } while (!((mdstat & 0x0000001F) == mdstat_mask));
-
-        if (enable)
-                davinci_psc_mux(id);
-}
-
-void __init davinci_psc_init(void)
-{
-        davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_VPSSMSTR, 1);
-        davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_VPSSSLV, 1);
-        davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPCC, 1);
-        davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPTC0, 1);
-        davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TPTC1, 1);
-        davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_GPIO, 1);
-
-        /* Turn on WatchDog timer LPSC.  Needed for RESET to work */
-        davinci_psc_config(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_LPSC_TIMER2, 1);
+                mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
+        } while (!((mdstat & MDSTAT_STATE_MASK) == next_state));
 }
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index 3010f9971255..695075796522 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -32,32 +32,47 @@
 #include <mach/hardware.h>
 #include <mach/serial.h>
 #include <mach/irqs.h>
+#include <mach/cputype.h>
+#include "clock.h"
 
-#define UART_DAVINCI_PWREMU 0x0c
-
-static inline unsigned int davinci_serial_in(struct plat_serial8250_port *up,
-                                          int offset)
+static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
+                                           int offset)
 {
         offset <<= up->regshift;
-        return (unsigned int)__raw_readb(up->membase + offset);
+        return (unsigned int)__raw_readl(IO_ADDRESS(up->mapbase) + offset);
 }
 
-static inline void davinci_serial_outp(struct plat_serial8250_port *p,
-                                       int offset, int value)
+static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
+                                    int value)
 {
         offset <<= p->regshift;
-        __raw_writeb(value, p->membase + offset);
+        __raw_writel(value, IO_ADDRESS(p->mapbase) + offset);
 }
 
 static struct plat_serial8250_port serial_platform_data[] = {
         {
-                .membase        = (char *)IO_ADDRESS(DAVINCI_UART0_BASE),
-                .mapbase        = (unsigned long)DAVINCI_UART0_BASE,
+                .mapbase        = DAVINCI_UART0_BASE,
                 .irq            = IRQ_UARTINT0,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+                                  UPF_IOREMAP,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+        },
+        {
+                .mapbase        = DAVINCI_UART1_BASE,
+                .irq            = IRQ_UARTINT1,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+                                  UPF_IOREMAP,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+        },
+        {
+                .mapbase        = DAVINCI_UART2_BASE,
+                .irq            = IRQ_UARTINT2,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+                                  UPF_IOREMAP,
                 .iotype         = UPIO_MEM,
                 .regshift       = 2,
-                .uartclk        = 27000000,
         },
         {
                 .flags          = 0
@@ -74,22 +89,68 @@ static struct platform_device serial_device = {
 
 static void __init davinci_serial_reset(struct plat_serial8250_port *p)
 {
-        /* reset both transmitter and receiver: bits 14,13 = UTRST, URRST */
         unsigned int pwremu = 0;
 
-        davinci_serial_outp(p, UART_IER, 0);  /* disable all interrupts */
+        serial_write_reg(p, UART_IER, 0);  /* disable all interrupts */
 
-        davinci_serial_outp(p, UART_DAVINCI_PWREMU, pwremu);
+        /* reset both transmitter and receiver: bits 14,13 = UTRST, URRST */
+        serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu);
         mdelay(10);
 
         pwremu |= (0x3 << 13);
         pwremu |= 0x1;
-        davinci_serial_outp(p, UART_DAVINCI_PWREMU, pwremu);
+        serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu);
+
+        if (cpu_is_davinci_dm646x())
+                serial_write_reg(p, UART_DM646X_SCR,
+                                 UART_DM646X_SCR_TX_WATERMARK);
+}
+
+void __init davinci_serial_init(struct davinci_uart_config *info)
+{
+        int i;
+        char name[16];
+        struct clk *uart_clk;
+        struct device *dev = &serial_device.dev;
+
+        /*
+         * Make sure the serial ports are muxed on at this point.
+         * You have to mux them off in device drivers later on
+         * if not needed.
+         */
+        for (i = 0; i < DAVINCI_MAX_NR_UARTS; i++) {
+                struct plat_serial8250_port *p = serial_platform_data + i;
+
+                if (!(info->enabled_uarts & (1 << i))) {
+                        p->flags = 0;
+                        continue;
+                }
+
+                if (cpu_is_davinci_dm646x())
+                        p->iotype = UPIO_MEM32;
+
+                if (cpu_is_davinci_dm355()) {
+                        if (i == 2) {
+                                p->mapbase = (unsigned long)DM355_UART2_BASE;
+                                p->irq = IRQ_DM355_UARTINT2;
+                        }
+                }
+
+                sprintf(name, "uart%d", i);
+                uart_clk = clk_get(dev, name);
+                if (IS_ERR(uart_clk))
+                        printk(KERN_ERR "%s:%d: failed to get UART%d clock\n",
+                                        __func__, __LINE__, i);
+                else {
+                        clk_enable(uart_clk);
+                        p->uartclk = clk_get_rate(uart_clk);
+                        davinci_serial_reset(p);
+                }
+        }
 }
 
 static int __init davinci_init(void)
 {
-        davinci_serial_reset(&serial_platform_data[0]);
         return platform_device_register(&serial_device);
 }
 
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index f8bcd29d17a6..494e01bff5c3 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -16,6 +16,9 @@
 #include <linux/clockchips.h>
 #include <linux/spinlock.h>
 #include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/device.h>
 
 #include <mach/hardware.h>
 #include <asm/system.h>
@@ -24,8 +27,11 @@
 #include <asm/mach/time.h>
 #include <asm/errno.h>
 #include <mach/io.h>
+#include <mach/cputype.h>
+#include "clock.h"
 
 static struct clock_event_device clockevent_davinci;
+static unsigned int davinci_clock_tick_rate;
 
 #define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400)
 #define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800)
@@ -99,9 +105,9 @@ struct timer_s {
         unsigned int id;
         unsigned long period;
         unsigned long opts;
-        unsigned long reg_base;
-        unsigned long tim_reg;
-        unsigned long prd_reg;
+        void __iomem *base;
+        unsigned long tim_off;
+        unsigned long prd_off;
         unsigned long enamode_shift;
         struct irqaction irqaction;
 };
@@ -114,15 +120,15 @@ static struct timer_s timers[];
 
 static int timer32_config(struct timer_s *t)
 {
-        u32 tcr = davinci_readl(t->reg_base + TCR);
+        u32 tcr = __raw_readl(t->base + TCR);
 
         /* disable timer */
         tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift);
-        davinci_writel(tcr, t->reg_base + TCR);
+        __raw_writel(tcr, t->base + TCR);
 
         /* reset counter to zero, set new period */
-        davinci_writel(0, t->tim_reg);
-        davinci_writel(t->period, t->prd_reg);
+        __raw_writel(0, t->base + t->tim_off);
+        __raw_writel(t->period, t->base + t->prd_off);
 
         /* Set enable mode */
         if (t->opts & TIMER_OPTS_ONESHOT) {
@@ -131,13 +137,13 @@ static int timer32_config(struct timer_s *t)
                 tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift;
         }
 
-        davinci_writel(tcr, t->reg_base + TCR);
+        __raw_writel(tcr, t->base + TCR);
         return 0;
 }
 
 static inline u32 timer32_read(struct timer_s *t)
 {
-        return davinci_readl(t->tim_reg);
+        return __raw_readl(t->base + t->tim_off);
 }
 
 static irqreturn_t timer_interrupt(int irq, void *dev_id)
@@ -176,51 +182,54 @@ static struct timer_s timers[] = {
 
 static void __init timer_init(void)
 {
-        u32 bases[] = {DAVINCI_TIMER0_BASE, DAVINCI_TIMER1_BASE};
+        u32 phys_bases[] = {DAVINCI_TIMER0_BASE, DAVINCI_TIMER1_BASE};
         int i;
 
         /* Global init of each 64-bit timer as a whole */
         for(i=0; i<2; i++) {
-                u32 tgcr, base = bases[i];
+                u32 tgcr;
+                void __iomem *base = IO_ADDRESS(phys_bases[i]);
 
                 /* Disabled, Internal clock source */
-                davinci_writel(0, base + TCR);
+                __raw_writel(0, base + TCR);
 
                 /* reset both timers, no pre-scaler for timer34 */
                 tgcr = 0;
-                davinci_writel(tgcr, base + TGCR);
+                __raw_writel(tgcr, base + TGCR);
 
                 /* Set both timers to unchained 32-bit */
                 tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT;
-                davinci_writel(tgcr, base + TGCR);
+                __raw_writel(tgcr, base + TGCR);
 
                 /* Unreset timers */
                 tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
                         (TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
-                davinci_writel(tgcr, base + TGCR);
+                __raw_writel(tgcr, base + TGCR);
 
                 /* Init both counters to zero */
-                davinci_writel(0, base + TIM12);
-                davinci_writel(0, base + TIM34);
+                __raw_writel(0, base + TIM12);
+                __raw_writel(0, base + TIM34);
         }
 
         /* Init of each timer as a 32-bit timer */
         for (i=0; i< ARRAY_SIZE(timers); i++) {
                 struct timer_s *t = &timers[i];
+                u32 phys_base;
 
                 if (t->name) {
                         t->id = i;
-                        t->reg_base = (IS_TIMER1(t->id) ?
+                        phys_base = (IS_TIMER1(t->id) ?
                                DAVINCI_TIMER1_BASE : DAVINCI_TIMER0_BASE);
+                        t->base = IO_ADDRESS(phys_base);
 
                         if (IS_TIMER_BOT(t->id)) {
                                 t->enamode_shift = 6;
-                                t->tim_reg = t->reg_base + TIM12;
-                                t->prd_reg = t->reg_base + PRD12;
+                                t->tim_off = TIM12;
+                                t->prd_off = PRD12;
                         } else {
                                 t->enamode_shift = 22;
-                                t->tim_reg = t->reg_base + TIM34;
-                                t->prd_reg = t->reg_base + PRD34;
+                                t->tim_off = TIM34;
+                                t->prd_off = PRD34;
                         }
 
                         /* Register interrupt */
@@ -238,7 +247,7 @@ static void __init timer_init(void)
 /*
  * clocksource
  */
-static cycle_t read_cycles(void)
+static cycle_t read_cycles(struct clocksource *cs)
 {
         struct timer_s *t = &timers[TID_CLOCKSOURCE];
 
@@ -274,7 +283,7 @@ static void davinci_set_mode(enum clock_event_mode mode,
 
         switch (mode) {
         case CLOCK_EVT_MODE_PERIODIC:
-                t->period = CLOCK_TICK_RATE / (HZ);
+                t->period = davinci_clock_tick_rate / (HZ);
                 t->opts = TIMER_OPTS_PERIODIC;
                 timer32_config(t);
                 break;
@@ -301,21 +310,29 @@ static struct clock_event_device clockevent_davinci = {
 
 static void __init davinci_timer_init(void)
 {
+        struct clk *timer_clk;
+
         static char err[] __initdata = KERN_ERR
                 "%s: can't register clocksource!\n";
 
         /* init timer hw */
         timer_init();
 
+        timer_clk = clk_get(NULL, "timer0");
+        BUG_ON(IS_ERR(timer_clk));
+        clk_enable(timer_clk);
+
+        davinci_clock_tick_rate = clk_get_rate(timer_clk);
+
         /* setup clocksource */
         clocksource_davinci.mult =
-                clocksource_khz2mult(CLOCK_TICK_RATE/1000,
+                clocksource_khz2mult(davinci_clock_tick_rate/1000,
                                      clocksource_davinci.shift);
         if (clocksource_register(&clocksource_davinci))
                 printk(err, clocksource_davinci.name);
 
         /* setup clockevent */
-        clockevent_davinci.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC,
+        clockevent_davinci.mult = div_sc(davinci_clock_tick_rate, NSEC_PER_SEC,
                                          clockevent_davinci.shift);
         clockevent_davinci.max_delta_ns =
                 clockevent_delta2ns(0xfffffffe, &clockevent_davinci);
@@ -333,42 +350,52 @@ struct sys_timer davinci_timer = {
 
 /* reset board using watchdog timer */
 void davinci_watchdog_reset(void) {
-        u32 tgcr, wdtcr, base = DAVINCI_WDOG_BASE;
+        u32 tgcr, wdtcr;
+        void __iomem *base = IO_ADDRESS(DAVINCI_WDOG_BASE);
+        struct device dev;
+        struct clk *wd_clk;
+        char *name = "watchdog";
+
+        dev_set_name(&dev, name);
+        wd_clk = clk_get(&dev, NULL);
+        if (WARN_ON(IS_ERR(wd_clk)))
+                return;
+        clk_enable(wd_clk);
 
         /* disable, internal clock source */
-        davinci_writel(0, base + TCR);
+        __raw_writel(0, base + TCR);
 
         /* reset timer, set mode to 64-bit watchdog, and unreset */
         tgcr = 0;
-        davinci_writel(tgcr, base + TCR);
+        __raw_writel(tgcr, base + TCR);
         tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT;
         tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
                 (TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
-        davinci_writel(tgcr, base + TCR);
+        __raw_writel(tgcr, base + TCR);
 
         /* clear counter and period regs */
-        davinci_writel(0, base + TIM12);
-        davinci_writel(0, base + TIM34);
-        davinci_writel(0, base + PRD12);
-        davinci_writel(0, base + PRD34);
+        __raw_writel(0, base + TIM12);
+        __raw_writel(0, base + TIM34);
+        __raw_writel(0, base + PRD12);
+        __raw_writel(0, base + PRD34);
 
         /* enable */
-        wdtcr = davinci_readl(base + WDTCR);
+        wdtcr = __raw_readl(base + WDTCR);
         wdtcr |= WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT;
-        davinci_writel(wdtcr, base + WDTCR);
+        __raw_writel(wdtcr, base + WDTCR);
 
         /* put watchdog in pre-active state */
         wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) |
                 (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
-        davinci_writel(wdtcr, base + WDTCR);
+        __raw_writel(wdtcr, base + WDTCR);
 
         /* put watchdog in active state */
         wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) |
                 (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
-        davinci_writel(wdtcr, base + WDTCR);
+        __raw_writel(wdtcr, base + WDTCR);
 
         /* write an invalid value to the WDKEY field to trigger
          * a watchdog reset */
         wdtcr = 0x00004000;
-        davinci_writel(wdtcr, base + WDTCR);
+        __raw_writel(wdtcr, base + WDTCR);
 }
diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c
index 2429b79f6da2..abedb6337182 100644
--- a/arch/arm/mach-davinci/usb.c
+++ b/arch/arm/mach-davinci/usb.c
@@ -14,6 +14,8 @@
 #include <mach/hardware.h>
 #include <mach/irqs.h>
 
+#define DAVINCI_USB_OTG_BASE 0x01C64000
+
 #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
 static struct musb_hdrc_eps_bits musb_eps[] = {
         { "ep1_tx", 8, },