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authorMark A. Greer <mgreer@mvista.com>2009-04-15 15:41:40 -0400
committerKevin Hilman <khilman@deeprootsystems.com>2009-05-28 18:17:47 -0400
commit0b0c4c2a6974eae7b96066cb0da35b526fe58468 (patch)
treeb5b037b86d3a08a220b6c31a67fe0005e1fa3a60 /arch/arm/mach-davinci/include/mach
parentb14dc0f9942a9c318c6c49f29511d88b3642e2d0 (diff)
davinci: Integrate cp_intc support into low-level irq code
Integrate the Common Platform Interrupt Controller (cp_intc) support into the low-level irq handling for davinci and similar platforms. Do it such that support for cp_intc and the original aintc can coexist in the same kernel binary. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/include/mach')
-rw-r--r--arch/arm/mach-davinci/include/mach/common.h1
-rw-r--r--arch/arm/mach-davinci/include/mach/entry-macro.S19
2 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index b773d92e7379..22db67744875 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -18,6 +18,7 @@ extern struct sys_timer davinci_timer;
18 18
19extern void davinci_irq_init(void); 19extern void davinci_irq_init(void);
20extern void __iomem *davinci_intc_base; 20extern void __iomem *davinci_intc_base;
21extern int davinci_intc_type;
21 22
22/* parameters describe VBUS sourcing for host mode */ 23/* parameters describe VBUS sourcing for host mode */
23extern void setup_usb(unsigned mA, unsigned potpgt_msec); 24extern void setup_usb(unsigned mA, unsigned potpgt_msec);
diff --git a/arch/arm/mach-davinci/include/mach/entry-macro.S b/arch/arm/mach-davinci/include/mach/entry-macro.S
index ed78851fe4ae..fbdebc7cb409 100644
--- a/arch/arm/mach-davinci/include/mach/entry-macro.S
+++ b/arch/arm/mach-davinci/include/mach/entry-macro.S
@@ -23,9 +23,28 @@
23 .endm 23 .endm
24 24
25 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 25 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
26#if defined(CONFIG_AINTC) && defined(CONFIG_CP_INTC)
27 ldr \tmp, =davinci_intc_type
28 ldr \tmp, [\tmp]
29 cmp \tmp, #DAVINCI_INTC_TYPE_CP_INTC
30 beq 1001f
31#endif
32#if defined(CONFIG_AINTC)
26 ldr \tmp, [\base, #0x14] 33 ldr \tmp, [\base, #0x14]
27 movs \tmp, \tmp, lsr #2 34 movs \tmp, \tmp, lsr #2
28 sub \irqnr, \tmp, #1 35 sub \irqnr, \tmp, #1
36 b 1002f
37#endif
38#if defined(CONFIG_CP_INTC)
391001: ldr \irqnr, [\base, #0x80] /* get irq number */
40 and \irqnr, \irqnr, #0xff /* irq is in bits 0-9 */
41 mov \tmp, \irqnr, lsr #3
42 and \tmp, \tmp, #0xfc
43 add \tmp, \tmp, #0x280 /* get the register offset */
44 ldr \irqstat, [\base, \tmp] /* get the intc status */
45 cmp \irqstat, #0x0
46#endif
471002:
29 .endm 48 .endm
30 49
31 .macro irq_prio_table 50 .macro irq_prio_table