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authorIdo Yariv <ido@wizery.com>2011-07-10 09:14:35 -0400
committerSekhar Nori <nsekhar@ti.com>2011-09-17 06:24:08 -0400
commitf23fe857bbea393b4b94fe2218c98d934bd3d4cf (patch)
tree39661f5a8db2b71a3efcd4dd19c5133462de87f4 /arch/arm/mach-davinci/devices-da8xx.c
parentb6fd41e29dea9c6753b1843a77e50433e6123bcb (diff)
ARM: davinci: Explicitly set channel controllers' default queues
Davinci platforms may define a default queue for each channel controller. If one is not defined, the default queue is set to EVENTQ_1. However, there's no way to distinguish between an unset default queue to one that is set to EVENTQ_0, as EVENTQ_0 = 0. Explicitly specify the default queue for all channel controllers on all Davinci platforms to EVENTQ_1, and don't overwrite it in the EDMA probe function. One exception is the DA850 board, for which EVENTQ_1 is not a valid option for its second channel controller. Use EVENTQ_0 instead for that channel controller. Signed-off-by: Ido Yariv <ido@wizery.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Diffstat (limited to 'arch/arm/mach-davinci/devices-da8xx.c')
-rw-r--r--arch/arm/mach-davinci/devices-da8xx.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 2f7e719636f1..68def7188868 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -136,6 +136,7 @@ static struct edma_soc_info da830_edma_cc0_info = {
136 .n_cc = 1, 136 .n_cc = 1,
137 .queue_tc_mapping = da8xx_queue_tc_mapping, 137 .queue_tc_mapping = da8xx_queue_tc_mapping,
138 .queue_priority_mapping = da8xx_queue_priority_mapping, 138 .queue_priority_mapping = da8xx_queue_priority_mapping,
139 .default_queue = EVENTQ_1,
139}; 140};
140 141
141static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = { 142static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
@@ -151,6 +152,7 @@ static struct edma_soc_info da850_edma_cc_info[] = {
151 .n_cc = 1, 152 .n_cc = 1,
152 .queue_tc_mapping = da8xx_queue_tc_mapping, 153 .queue_tc_mapping = da8xx_queue_tc_mapping,
153 .queue_priority_mapping = da8xx_queue_priority_mapping, 154 .queue_priority_mapping = da8xx_queue_priority_mapping,
155 .default_queue = EVENTQ_1,
154 }, 156 },
155 { 157 {
156 .n_channel = 32, 158 .n_channel = 32,
@@ -160,6 +162,7 @@ static struct edma_soc_info da850_edma_cc_info[] = {
160 .n_cc = 1, 162 .n_cc = 1,
161 .queue_tc_mapping = da850_queue_tc_mapping, 163 .queue_tc_mapping = da850_queue_tc_mapping,
162 .queue_priority_mapping = da850_queue_priority_mapping, 164 .queue_priority_mapping = da850_queue_priority_mapping,
165 .default_queue = EVENTQ_0,
163 }, 166 },
164}; 167};
165 168