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authorSekhar Nori <nsekhar@ti.com>2009-11-16 06:51:33 -0500
committerKevin Hilman <khilman@deeprootsystems.com>2010-02-04 16:29:33 -0500
commit9a219a9ecf49ab156df4c18267ade4d468d9930e (patch)
treec71e664117603bbdf4eef09f1bb15fddccb86de4 /arch/arm/mach-davinci/clock.c
parentd2de05827cce9438dfc61d5a4cf13b6ca82ebdee (diff)
davinci: move PLL wait time values to clock.h
As suspend support is added, the code supporting the suspend operation needs to bypass PLLs and needs to access the same wait time values as the PLL code in clock.c. To facilitate this, move the PLL wait times to clock.h where they can be accessed by suspend code. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/clock.c')
-rw-r--r--arch/arm/mach-davinci/clock.c15
1 files changed, 3 insertions, 12 deletions
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index baece65cb9c0..0fa68c558320 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -376,7 +376,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
376 locktime = ((2000 * prediv) / 100); 376 locktime = ((2000 * prediv) / 100);
377 prediv = (prediv - 1) | PLLDIV_EN; 377 prediv = (prediv - 1) | PLLDIV_EN;
378 } else { 378 } else {
379 locktime = 20; 379 locktime = PLL_LOCK_TIME;
380 } 380 }
381 if (postdiv) 381 if (postdiv)
382 postdiv = (postdiv - 1) | PLLDIV_EN; 382 postdiv = (postdiv - 1) | PLLDIV_EN;
@@ -389,12 +389,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
389 ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN); 389 ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
390 __raw_writel(ctrl, pll->base + PLLCTL); 390 __raw_writel(ctrl, pll->base + PLLCTL);
391 391
392 /* 392 udelay(PLL_BYPASS_TIME);
393 * Wait for 4 OSCIN/CLKIN cycles to ensure that the PLLC has switched
394 * to bypass mode. Delay of 1us ensures we are good for all > 4MHz
395 * OSCIN/CLKIN inputs. Typically the input is ~25MHz.
396 */
397 udelay(1);
398 393
399 /* Reset and enable PLL */ 394 /* Reset and enable PLL */
400 ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS); 395 ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
@@ -408,11 +403,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
408 if (pll->flags & PLL_HAS_POSTDIV) 403 if (pll->flags & PLL_HAS_POSTDIV)
409 __raw_writel(postdiv, pll->base + POSTDIV); 404 __raw_writel(postdiv, pll->base + POSTDIV);
410 405
411 /* 406 udelay(PLL_RESET_TIME);
412 * Wait for PLL to reset properly, OMAP-L138 datasheet says
413 * 'min' time = 125ns
414 */
415 udelay(1);
416 407
417 /* Bring PLL out of reset */ 408 /* Bring PLL out of reset */
418 ctrl |= PLLCTL_PLLRST; 409 ctrl |= PLLCTL_PLLRST;