diff options
author | Alexander Shiyan <shc_work@mail.ru> | 2013-05-13 13:07:33 -0400 |
---|---|---|
committer | Olof Johansson <olof@lixom.net> | 2013-06-11 18:47:38 -0400 |
commit | 7dfbf1b68eb9eea411781ff9e610377febe4d6a2 (patch) | |
tree | ddbdd3b61ce70173f94ac5375c3226c49435f750 /arch/arm/mach-clps711x | |
parent | c99f72addbf5c0ad37d5a9b26f99208464d35f5c (diff) |
ARM: clps711x: Optimize interrupt handling
This patch modify interrupt handler for processing all penging interrupts
at once.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-clps711x')
-rw-r--r-- | arch/arm/mach-clps711x/common.c | 30 |
1 files changed, 18 insertions, 12 deletions
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c index bd658398a819..f6d1746366d4 100644 --- a/arch/arm/mach-clps711x/common.c +++ b/arch/arm/mach-clps711x/common.c | |||
@@ -215,7 +215,7 @@ void __init clps711x_init_irq(void) | |||
215 | } | 215 | } |
216 | } | 216 | } |
217 | 217 | ||
218 | inline u32 fls16(u32 x) | 218 | static inline u32 fls16(u32 x) |
219 | { | 219 | { |
220 | u32 r = 15; | 220 | u32 r = 15; |
221 | 221 | ||
@@ -239,18 +239,24 @@ inline u32 fls16(u32 x) | |||
239 | 239 | ||
240 | asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs) | 240 | asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs) |
241 | { | 241 | { |
242 | u32 irqstat; | 242 | do { |
243 | void __iomem *base = CLPS711X_VIRT_BASE; | 243 | u32 irqstat; |
244 | void __iomem *base = CLPS711X_VIRT_BASE; | ||
245 | |||
246 | irqstat = readw_relaxed(base + INTSR1) & | ||
247 | readw_relaxed(base + INTMR1); | ||
248 | if (irqstat) | ||
249 | handle_IRQ(fls16(irqstat), regs); | ||
250 | |||
251 | irqstat = readw_relaxed(base + INTSR2) & | ||
252 | readw_relaxed(base + INTMR2); | ||
253 | if (irqstat) { | ||
254 | handle_IRQ(fls16(irqstat) + 16, regs); | ||
255 | continue; | ||
256 | } | ||
244 | 257 | ||
245 | irqstat = readl_relaxed(base + INTSR1) & readl_relaxed(base + INTMR1); | 258 | break; |
246 | if (irqstat) { | 259 | } while (1); |
247 | handle_IRQ(fls16(irqstat), regs); | ||
248 | return; | ||
249 | } | ||
250 | |||
251 | irqstat = readl_relaxed(base + INTSR2) & readl_relaxed(base + INTMR2); | ||
252 | if (likely(irqstat)) | ||
253 | handle_IRQ(fls16(irqstat) + 16, regs); | ||
254 | } | 260 | } |
255 | 261 | ||
256 | static u32 notrace clps711x_sched_clock_read(void) | 262 | static u32 notrace clps711x_sched_clock_read(void) |