Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC-specific updates from Arnd Bergmann:
 "This is a larger set of new functionality for the existing SoC
  families, including:

   - vt8500 gains support for new CPU cores, notably the Cortex-A9 based
     wm8850

   - prima2 gains support for the "marco" SoC family, its SMP based
     cousin

   - tegra gains support for the new Tegra4 (Tegra114) family

   - socfpga now supports a newer version of the hardware including SMP

   - i.mx31 and bcm2835 are now using DT probing for their clocks

   - lots of updates for sh-mobile

   - OMAP updates for clocks, power management and USB

   - i.mx6q and tegra now support cpuidle

   - kirkwood now supports PCIe hot plugging

   - tegra clock support is updated

   - tegra USB PHY probing gets implemented diffently"

* tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (148 commits)
  ARM: prima2: remove duplicate v7_invalidate_l1
  ARM: shmobile: r8a7779: Correct TMU clock support again
  ARM: prima2: fix __init section for cpu hotplug
  ARM: OMAP: Consolidate OMAP USB-HS platform data (part 3/3)
  ARM: OMAP: Consolidate OMAP USB-HS platform data (part 1/3)
  arm: socfpga: Add SMP support for actual socfpga harware
  arm: Add v7_invalidate_l1 to cache-v7.S
  arm: socfpga: Add entries to enable make dtbs socfpga
  arm: socfpga: Add new device tree source for actual socfpga HW
  ARM: tegra: sort Kconfig selects for Tegra114
  ARM: tegra: enable ARCH_REQUIRE_GPIOLIB for Tegra114
  ARM: tegra: Fix build error w/ ARCH_TEGRA_114_SOC w/o ARCH_TEGRA_3x_SOC
  ARM: tegra: Fix build error for gic update
  ARM: tegra: remove empty tegra_smp_init_cpus()
  ARM: shmobile: Register ARM architected timer
  ARM: MARCO: fix the build issue due to gic-vic-to-irqchip move
  ARM: shmobile: r8a7779: Correct TMU clock support
  ARM: mxs_defconfig: Select CONFIG_DEVTMPFS_MOUNT
  ARM: mxs: decrease mxs_clockevent_device.min_delta_ns to 2 clock cycles
  ARM: mxs: use apbx bus clock to drive the timers on timrotv2
  ...

1 files changed, 28 insertions, 0 deletions

diff --git a/arch/arm/mach-bcm2835/bcm2835.c b/arch/arm/mach-bcm2835/bcm2835.c
index d615a61e902c..6f5785985dd1 100644
--- a/arch/arm/mach-bcm2835/bcm2835.c
+++ b/arch/arm/mach-bcm2835/bcm2835.c
@@ -26,11 +26,13 @@
 #include <mach/bcm2835_soc.h>
 
 #define PM_RSTC                         0x1c
+#define PM_RSTS                         0x20
 #define PM_WDOG                         0x24
 
 #define PM_PASSWORD                     0x5a000000
 #define PM_RSTC_WRCFG_MASK              0x00000030
 #define PM_RSTC_WRCFG_FULL_RESET        0x00000020
+#define PM_RSTS_HADWRH_SET              0x00000040
 
 static void __iomem *wdt_regs;
 
@@ -67,6 +69,29 @@ static void bcm2835_restart(char mode, const char *cmd)
         mdelay(1);
 }
 
+/*
+ * We can't really power off, but if we do the normal reset scheme, and
+ * indicate to bootcode.bin not to reboot, then most of the chip will be
+ * powered off.
+ */
+static void bcm2835_power_off(void)
+{
+        u32 val;
+
+        /*
+         * We set the watchdog hard reset bit here to distinguish this reset
+         * from the normal (full) reset. bootcode.bin will not reboot after a
+         * hard reset.
+         */
+        val = readl_relaxed(wdt_regs + PM_RSTS);
+        val &= ~PM_RSTC_WRCFG_MASK;
+        val |= PM_PASSWORD | PM_RSTS_HADWRH_SET;
+        writel_relaxed(val, wdt_regs + PM_RSTS);
+
+        /* Continue with normal reset mechanism */
+        bcm2835_restart(0, "");
+}
+
 static struct map_desc io_map __initdata = {
         .virtual = BCM2835_PERIPH_VIRT,
         .pfn = __phys_to_pfn(BCM2835_PERIPH_PHYS),
@@ -84,6 +109,9 @@ static void __init bcm2835_init(void)
         int ret;
 
         bcm2835_setup_restart();
+        if (wdt_regs)
+                pm_power_off = bcm2835_power_off;
+
         bcm2835_init_clocks();
 
         ret = of_platform_populate(NULL, of_default_bus_match_table, NULL,