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authorAlexandre Belloni <alexandre.belloni@free-electrons.com>2015-03-12 08:07:31 -0400
committerNicolas Ferre <nicolas.ferre@atmel.com>2015-03-16 12:03:05 -0400
commitb53cdd03222391f76e82cd0c7d040816c919ab75 (patch)
tree442907fe49dbb8dbdf49e236643825f483336c42 /arch/arm/mach-at91
parentbbfc97e1b1b9fb2177a9134f57506eb371638b85 (diff)
ARM: at91: time: move the system timer driver to drivers/clocksource
Import at91rm9200_time.c from mach-at91 as timer-atmel-st.c. Further cleanup is required to get rid of the mach-at91 headers. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/mach-at91')
-rw-r--r--arch/arm/mach-at91/Kconfig1
-rw-r--r--arch/arm/mach-at91/Makefile2
-rw-r--r--arch/arm/mach-at91/at91rm9200_time.c253
3 files changed, 2 insertions, 254 deletions
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 4da6bae047f3..24b59c75f6af 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -77,6 +77,7 @@ if SOC_SAM_V4_V5
77config SOC_AT91RM9200 77config SOC_AT91RM9200
78 bool "AT91RM9200" 78 bool "AT91RM9200"
79 select ATMEL_AIC_IRQ 79 select ATMEL_AIC_IRQ
80 select ATMEL_ST
80 select COMMON_CLK_AT91 81 select COMMON_CLK_AT91
81 select CPU_ARM920T 82 select CPU_ARM920T
82 select GENERIC_CLOCKEVENTS 83 select GENERIC_CLOCKEVENTS
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index ea54c9824d89..38aaef7b994e 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -7,7 +7,7 @@ obj-y := soc.o
7obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o 7obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o
8 8
9# CPU-specific support 9# CPU-specific support
10obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o at91rm9200_time.o 10obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o
11obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o 11obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o
12obj-$(CONFIG_SOC_SAMA5) += sama5.o 12obj-$(CONFIG_SOC_SAMA5) += sama5.o
13 13
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
deleted file mode 100644
index 7d062ab32674..000000000000
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ /dev/null
@@ -1,253 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/at91rm9200_time.c
3 *
4 * Copyright (C) 2003 SAN People
5 * Copyright (C) 2003 ATMEL
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/kernel.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/clockchips.h>
26#include <linux/export.h>
27#include <linux/of.h>
28#include <linux/of_address.h>
29#include <linux/of_irq.h>
30
31#include <asm/mach/time.h>
32
33#include <mach/at91_st.h>
34#include <mach/hardware.h>
35
36static unsigned long last_crtr;
37static u32 irqmask;
38static struct clock_event_device clkevt;
39
40#define RM9200_TIMER_LATCH ((AT91_SLOW_CLOCK + HZ/2) / HZ)
41
42/*
43 * The ST_CRTR is updated asynchronously to the master clock ... but
44 * the updates as seen by the CPU don't seem to be strictly monotonic.
45 * Waiting until we read the same value twice avoids glitching.
46 */
47static inline unsigned long read_CRTR(void)
48{
49 unsigned long x1, x2;
50
51 x1 = at91_st_read(AT91_ST_CRTR);
52 do {
53 x2 = at91_st_read(AT91_ST_CRTR);
54 if (x1 == x2)
55 break;
56 x1 = x2;
57 } while (1);
58 return x1;
59}
60
61/*
62 * IRQ handler for the timer.
63 */
64static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
65{
66 u32 sr = at91_st_read(AT91_ST_SR) & irqmask;
67
68 /*
69 * irqs should be disabled here, but as the irq is shared they are only
70 * guaranteed to be off if the timer irq is registered first.
71 */
72 WARN_ON_ONCE(!irqs_disabled());
73
74 /* simulate "oneshot" timer with alarm */
75 if (sr & AT91_ST_ALMS) {
76 clkevt.event_handler(&clkevt);
77 return IRQ_HANDLED;
78 }
79
80 /* periodic mode should handle delayed ticks */
81 if (sr & AT91_ST_PITS) {
82 u32 crtr = read_CRTR();
83
84 while (((crtr - last_crtr) & AT91_ST_CRTV) >= RM9200_TIMER_LATCH) {
85 last_crtr += RM9200_TIMER_LATCH;
86 clkevt.event_handler(&clkevt);
87 }
88 return IRQ_HANDLED;
89 }
90
91 /* this irq is shared ... */
92 return IRQ_NONE;
93}
94
95static struct irqaction at91rm9200_timer_irq = {
96 .name = "at91_tick",
97 .flags = IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
98 .handler = at91rm9200_timer_interrupt,
99 .irq = NR_IRQS_LEGACY + AT91_ID_SYS,
100};
101
102static cycle_t read_clk32k(struct clocksource *cs)
103{
104 return read_CRTR();
105}
106
107static struct clocksource clk32k = {
108 .name = "32k_counter",
109 .rating = 150,
110 .read = read_clk32k,
111 .mask = CLOCKSOURCE_MASK(20),
112 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
113};
114
115static void
116clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
117{
118 /* Disable and flush pending timer interrupts */
119 at91_st_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
120 at91_st_read(AT91_ST_SR);
121
122 last_crtr = read_CRTR();
123 switch (mode) {
124 case CLOCK_EVT_MODE_PERIODIC:
125 /* PIT for periodic irqs; fixed rate of 1/HZ */
126 irqmask = AT91_ST_PITS;
127 at91_st_write(AT91_ST_PIMR, RM9200_TIMER_LATCH);
128 break;
129 case CLOCK_EVT_MODE_ONESHOT:
130 /* ALM for oneshot irqs, set by next_event()
131 * before 32 seconds have passed
132 */
133 irqmask = AT91_ST_ALMS;
134 at91_st_write(AT91_ST_RTAR, last_crtr);
135 break;
136 case CLOCK_EVT_MODE_SHUTDOWN:
137 case CLOCK_EVT_MODE_UNUSED:
138 case CLOCK_EVT_MODE_RESUME:
139 irqmask = 0;
140 break;
141 }
142 at91_st_write(AT91_ST_IER, irqmask);
143}
144
145static int
146clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
147{
148 u32 alm;
149 int status = 0;
150
151 BUG_ON(delta < 2);
152
153 /* The alarm IRQ uses absolute time (now+delta), not the relative
154 * time (delta) in our calling convention. Like all clockevents
155 * using such "match" hardware, we have a race to defend against.
156 *
157 * Our defense here is to have set up the clockevent device so the
158 * delta is at least two. That way we never end up writing RTAR
159 * with the value then held in CRTR ... which would mean the match
160 * wouldn't trigger until 32 seconds later, after CRTR wraps.
161 */
162 alm = read_CRTR();
163
164 /* Cancel any pending alarm; flush any pending IRQ */
165 at91_st_write(AT91_ST_RTAR, alm);
166 at91_st_read(AT91_ST_SR);
167
168 /* Schedule alarm by writing RTAR. */
169 alm += delta;
170 at91_st_write(AT91_ST_RTAR, alm);
171
172 return status;
173}
174
175static struct clock_event_device clkevt = {
176 .name = "at91_tick",
177 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
178 .rating = 150,
179 .set_next_event = clkevt32k_next_event,
180 .set_mode = clkevt32k_mode,
181};
182
183void __iomem *at91_st_base;
184EXPORT_SYMBOL_GPL(at91_st_base);
185
186static const struct of_device_id at91rm9200_st_timer_ids[] = {
187 { .compatible = "atmel,at91rm9200-st" },
188 { /* sentinel */ }
189};
190
191static int __init of_at91rm9200_st_init(void)
192{
193 struct device_node *np;
194 int ret;
195
196 np = of_find_matching_node(NULL, at91rm9200_st_timer_ids);
197 if (!np)
198 goto err;
199
200 at91_st_base = of_iomap(np, 0);
201 if (!at91_st_base)
202 goto node_err;
203
204 /* Get the interrupts property */
205 ret = irq_of_parse_and_map(np, 0);
206 if (!ret)
207 goto ioremap_err;
208 at91rm9200_timer_irq.irq = ret;
209
210 of_node_put(np);
211
212 return 0;
213
214ioremap_err:
215 iounmap(at91_st_base);
216node_err:
217 of_node_put(np);
218err:
219 return -EINVAL;
220}
221
222/*
223 * ST (system timer) module supports both clockevents and clocksource.
224 */
225static void __init atmel_st_timer_init(struct device_node *node)
226{
227 /* For device tree enabled device: initialize here */
228 of_at91rm9200_st_init();
229
230 /* Disable all timer interrupts, and clear any pending ones */
231 at91_st_write(AT91_ST_IDR,
232 AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
233 at91_st_read(AT91_ST_SR);
234
235 /* Make IRQs happen for the system timer */
236 setup_irq(at91rm9200_timer_irq.irq, &at91rm9200_timer_irq);
237
238 /* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
239 * directly for the clocksource and all clockevents, after adjusting
240 * its prescaler from the 1 Hz default.
241 */
242 at91_st_write(AT91_ST_RTMR, 1);
243
244 /* Setup timer clockevent, with minimum of two ticks (important!!) */
245 clkevt.cpumask = cpumask_of(0);
246 clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK,
247 2, AT91_ST_ALMV);
248
249 /* register clocksource */
250 clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
251}
252CLOCKSOURCE_OF_DECLARE(atmel_st_timer, "atmel,at91rm9200-st",
253 atmel_st_timer_init);