Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull support for new arm SoCs from Olof Johansson:
 "Three new system-on-chip models are supported: the st-ericsson u9540
  in ux500, the sam9n12 in at91 and the emma ev2 in shmobile.

  Emma is a little bit special because it is completely unrelated to the
  classic shmobile models, but the new Renesas rmobile SoCs are a
  combination of things from both Emma and shmobile, so it was decided
  to have them all live in one directory.

  This also contains updates to existing shmobile soc code as well as
  some related board changes due to dependencies."

* tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (23 commits)
  mach-shmobile: Use DT_MACHINE for KZM9D V3
  mach-shmobile: Emma Mobile EV2 DT support V3
  mach-shmobile: KZM9D board Ethernet support V3
  mach-shmobile: Emma Mobile EV2 GPIO support V3
  mach-shmobile: Emma Mobile EV2 SMP support V3
  mach-shmobile: KZM9D board support V3
  mach-shmobile: Emma Mobile EV2 SoC base support V3
  gpio: Emma Mobile GPIO driver V2
  ARM: mach-shmobile: sh73a0: fixup PINT/IRQ16-IRQ31 irq number conflict
  ARM: mach-shmobile: clock-r8a7740: use followparent_recalc on usb24s
  ARM: mach-shmobile: clock-r8a7740: add MMCIF clock
  ARM: mach-shmobile: clock-r8a7740: add SDHI clock
  ARM: mach-shmobile: clock-r8a7740: add USB clock
  ARM: mach-shmobile: clock-r8a7740: add FSI clock
  ARM: mach-shmobile: r8a7740: cleanup I2C workaround method
  ARM: mach-shmobile: r8a7740: add gpio_irq support
  ARM: mach-shmobile: sh7372: Add FSI DMAEngine support
  ARM / mach-shmobile: Use preset_lpj with calibrate_delay()
  ARM: ux500: ioremap differences for DB9540
  ARM: ux500: core U9540 support
  ...

11 files changed, 389 insertions, 5 deletions

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 98a42f3472d5..19505c0a3f01 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -91,6 +91,14 @@ config SOC_AT91SAM9X5
           This support covers AT91SAM9G15, AT91SAM9G25, AT91SAM9X25, AT91SAM9G35
           and AT91SAM9X35.
 
+config SOC_AT91SAM9N12
+        bool "AT91SAM9N12 family"
+        select SOC_AT91SAM9
+        select HAVE_AT91_DBGU0
+        select HAVE_FB_ATMEL
+        help
+          Select this if you are using Atmel's AT91SAM9N12 SoC.
+
 choice
         prompt "Atmel AT91 Processor Devices for non DT boards"
 
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 79d0f60af0b2..3bb7a51efc9d 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_SOC_AT91SAM9260)	+= at91sam9260.o
 obj-$(CONFIG_SOC_AT91SAM9261)   += at91sam9261.o
 obj-$(CONFIG_SOC_AT91SAM9263)   += at91sam9263.o
 obj-$(CONFIG_SOC_AT91SAM9G45)   += at91sam9g45.o
+obj-$(CONFIG_SOC_AT91SAM9N12)   += at91sam9n12.o
 obj-$(CONFIG_SOC_AT91SAM9X5)    += at91sam9x5.o
 obj-$(CONFIG_SOC_AT91SAM9RL)    += at91sam9rl.o
 
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index c03417ddbf0c..9e84fe4f2aaa 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -30,5 +30,7 @@ dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9g20.dtb
 dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9g20.dtb
 # sam9g45
 dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb
+# sam9n12
+dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9n12ek.dtb
 # sam9x5
 dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g25ek.dtb
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
new file mode 100644
index 000000000000..08494664ab78
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -0,0 +1,233 @@
+/*
+ * SoC specific setup code for the AT91SAM9N12
+ *
+ * Copyright (C) 2012 Atmel Corporation.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/at91sam9n12.h>
+#include <mach/at91_pmc.h>
+#include <mach/cpu.h>
+#include <mach/board.h>
+
+#include "soc.h"
+#include "generic.h"
+#include "clock.h"
+#include "sam9_smc.h"
+
+/* --------------------------------------------------------------------
+ *  Clocks
+ * -------------------------------------------------------------------- */
+
+/*
+ * The peripheral clocks.
+ */
+static struct clk pioAB_clk = {
+        .name           = "pioAB_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_PIOAB,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioCD_clk = {
+        .name           = "pioCD_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_PIOCD,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart0_clk = {
+        .name           = "usart0_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_USART0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart1_clk = {
+        .name           = "usart1_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_USART1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart2_clk = {
+        .name           = "usart2_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_USART2,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart3_clk = {
+        .name           = "usart3_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_USART3,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi0_clk = {
+        .name           = "twi0_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_TWI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi1_clk = {
+        .name           = "twi1_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_TWI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mmc_clk = {
+        .name           = "mci_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_MCI,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi0_clk = {
+        .name           = "spi0_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_SPI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi1_clk = {
+        .name           = "spi1_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_SPI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk uart0_clk = {
+        .name           = "uart0_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_UART0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk uart1_clk = {
+        .name           = "uart1_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_UART1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tcb_clk = {
+        .name           = "tcb_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_TCB,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pwm_clk = {
+        .name           = "pwm_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_PWM,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk adc_clk = {
+        .name           = "adc_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_ADC,
+        .type   = CLK_TYPE_PERIPHERAL,
+};
+static struct clk dma_clk = {
+        .name           = "dma_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_DMA,
+        .type   = CLK_TYPE_PERIPHERAL,
+};
+static struct clk uhp_clk = {
+        .name           = "uhp",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_UHP,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk udp_clk = {
+        .name           = "udp_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_UDP,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk lcdc_clk = {
+        .name           = "lcdc_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_LCDC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc_clk = {
+        .name           = "ssc_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_SSC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+
+static struct clk *periph_clocks[] __initdata = {
+        &pioAB_clk,
+        &pioCD_clk,
+        &usart0_clk,
+        &usart1_clk,
+        &usart2_clk,
+        &usart3_clk,
+        &twi0_clk,
+        &twi1_clk,
+        &mmc_clk,
+        &spi0_clk,
+        &spi1_clk,
+        &lcdc_clk,
+        &uart0_clk,
+        &uart1_clk,
+        &tcb_clk,
+        &pwm_clk,
+        &adc_clk,
+        &dma_clk,
+        &uhp_clk,
+        &udp_clk,
+        &ssc_clk,
+};
+
+static struct clk_lookup periph_clocks_lookups[] = {
+        /* lookup table for DT entries */
+        CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
+        CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
+        CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
+        CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
+        CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk),
+        CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
+        CLKDEV_CON_ID("pioA", &pioAB_clk),
+        CLKDEV_CON_ID("pioB", &pioAB_clk),
+        CLKDEV_CON_ID("pioC", &pioCD_clk),
+        CLKDEV_CON_ID("pioD", &pioCD_clk),
+        /* additional fake clock for macb_hclk */
+        CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk),
+        CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk),
+};
+
+/*
+ * The two programmable clocks.
+ * You must configure pin multiplexing to bring these signals out.
+ */
+static struct clk pck0 = {
+        .name           = "pck0",
+        .pmc_mask       = AT91_PMC_PCK0,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 0,
+};
+static struct clk pck1 = {
+        .name           = "pck1",
+        .pmc_mask       = AT91_PMC_PCK1,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 1,
+};
+
+static void __init at91sam9n12_register_clocks(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
+                clk_register(periph_clocks[i]);
+        clk_register(&pck0);
+        clk_register(&pck1);
+
+        clkdev_add_table(periph_clocks_lookups,
+                         ARRAY_SIZE(periph_clocks_lookups));
+
+}
+
+/* --------------------------------------------------------------------
+ *  AT91SAM9N12 processor initialization
+ * -------------------------------------------------------------------- */
+
+static void __init at91sam9n12_map_io(void)
+{
+        at91_init_sram(0, AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE);
+}
+
+void __init at91sam9n12_initialize(void)
+{
+        at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0);
+
+        /* Register GPIO subsystem (using DT) */
+        at91_gpio_init(NULL, 0);
+}
+
+struct at91_init_soc __initdata at91sam9n12_soc = {
+        .map_io = at91sam9n12_map_io,
+        .register_clocks = at91sam9n12_register_clocks,
+        .init = at91sam9n12_initialize,
+};
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 6b692824c988..de2ec6b8fea7 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -58,13 +58,15 @@ EXPORT_SYMBOL_GPL(at91_pmc_base);
 
 #define cpu_has_800M_plla()     (  cpu_is_at91sam9g20() \
                                 || cpu_is_at91sam9g45() \
-                                || cpu_is_at91sam9x5())
+                                || cpu_is_at91sam9x5() \
+                                || cpu_is_at91sam9n12())
 
 #define cpu_has_300M_plla()     (cpu_is_at91sam9g10())
 
 #define cpu_has_pllb()          (!(cpu_is_at91sam9rl() \
                                 || cpu_is_at91sam9g45() \
-                                || cpu_is_at91sam9x5()))
+                                || cpu_is_at91sam9x5() \
+                                || cpu_is_at91sam9n12()))
 
 #define cpu_has_upll()          (cpu_is_at91sam9g45() \
                                 || cpu_is_at91sam9x5())
@@ -78,12 +80,15 @@ EXPORT_SYMBOL_GPL(at91_pmc_base);
                                 || cpu_is_at91sam9x5()))
 
 #define cpu_has_plladiv2()      (cpu_is_at91sam9g45() \
-                                || cpu_is_at91sam9x5())
+                                || cpu_is_at91sam9x5() \
+                                || cpu_is_at91sam9n12())
 
 #define cpu_has_mdiv3()         (cpu_is_at91sam9g45() \
-                                || cpu_is_at91sam9x5())
+                                || cpu_is_at91sam9x5() \
+                                || cpu_is_at91sam9n12())
 
-#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5())
+#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \
+                                || cpu_is_at91sam9n12())
 
 static LIST_HEAD(clocks);
 static DEFINE_SPINLOCK(clk_lock);
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h
new file mode 100644
index 000000000000..d374b87c0459
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9n12.h
@@ -0,0 +1,60 @@
+/*
+ * SoC specific header file for the AT91SAM9N12
+ *
+ * Copyright (C) 2012 Atmel Corporation
+ *
+ * Common definitions, based on AT91SAM9N12 SoC datasheet
+ *
+ * Licensed under GPLv2 or later
+ */
+
+#ifndef _AT91SAM9N12_H_
+#define _AT91SAM9N12_H_
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91SAM9N12_ID_PIOAB    2       /* Parallel I/O Controller A and B */
+#define AT91SAM9N12_ID_PIOCD    3       /* Parallel I/O Controller C and D */
+#define AT91SAM9N12_ID_FUSE     4       /* FUSE Controller */
+#define AT91SAM9N12_ID_USART0   5       /* USART 0 */
+#define AT91SAM9N12_ID_USART1   6       /* USART 1 */
+#define AT91SAM9N12_ID_USART2   7       /* USART 2 */
+#define AT91SAM9N12_ID_USART3   8       /* USART 3 */
+#define AT91SAM9N12_ID_TWI0     9       /* Two-Wire Interface 0 */
+#define AT91SAM9N12_ID_TWI1     10      /* Two-Wire Interface 1 */
+#define AT91SAM9N12_ID_MCI      12      /* High Speed Multimedia Card Interface */
+#define AT91SAM9N12_ID_SPI0     13      /* Serial Peripheral Interface 0 */
+#define AT91SAM9N12_ID_SPI1     14      /* Serial Peripheral Interface 1 */
+#define AT91SAM9N12_ID_UART0    15      /* UART 0 */
+#define AT91SAM9N12_ID_UART1    16      /* UART 1 */
+#define AT91SAM9N12_ID_TCB      17      /* Timer Counter 0, 1, 2, 3, 4 and 5 */
+#define AT91SAM9N12_ID_PWM      18      /* Pulse Width Modulation Controller */
+#define AT91SAM9N12_ID_ADC      19      /* ADC Controller */
+#define AT91SAM9N12_ID_DMA      20      /* DMA Controller */
+#define AT91SAM9N12_ID_UHP      22      /* USB Host High Speed */
+#define AT91SAM9N12_ID_UDP      23      /* USB Device High Speed */
+#define AT91SAM9N12_ID_LCDC     25      /* LCD Controller */
+#define AT91SAM9N12_ID_ISI      25      /* Image Sensor Interface */
+#define AT91SAM9N12_ID_SSC      28      /* Synchronous Serial Controller */
+#define AT91SAM9N12_ID_TRNG     30      /* TRNG */
+#define AT91SAM9N12_ID_IRQ0     31      /* Advanced Interrupt Controller */
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT91SAM9N12_BASE_USART0 0xf801c000
+#define AT91SAM9N12_BASE_USART1 0xf8020000
+#define AT91SAM9N12_BASE_USART2 0xf8024000
+#define AT91SAM9N12_BASE_USART3 0xf8028000
+
+/*
+ * Internal Memory.
+ */
+#define AT91SAM9N12_SRAM_BASE   0x00300000      /* Internal SRAM base address */
+#define AT91SAM9N12_SRAM_SIZE   SZ_32K          /* Internal SRAM size (32Kb) */
+
+#define AT91SAM9N12_ROM_BASE    0x00100000      /* Internal ROM base address */
+#define AT91SAM9N12_ROM_SIZE    SZ_128K         /* Internal ROM size (128Kb) */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h
new file mode 100644
index 000000000000..40060cd62fa9
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h
@@ -0,0 +1,53 @@
+/*
+ * Matrix-centric header file for the AT91SAM9N12
+ *
+ * Copyright (C) 2012 Atmel Corporation.
+ *
+ * Only EBI related registers.
+ * Write Protect register definitions may be useful.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef _AT91SAM9N12_MATRIX_H_
+#define _AT91SAM9N12_MATRIX_H_
+
+#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x118)   /* EBI Chip Select Assignment Register */
+#define         AT91_MATRIX_EBI_CS1A            (1 << 1)        /* Chip Select 1 Assignment */
+#define                 AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
+#define                 AT91_MATRIX_EBI_CS1A_SDRAMC             (1 << 1)
+#define         AT91_MATRIX_EBI_CS3A            (1 << 3)        /* Chip Select 3 Assignment */
+#define                 AT91_MATRIX_EBI_CS3A_SMC                (0 << 3)
+#define                 AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH      (1 << 3)
+#define         AT91_MATRIX_EBI_DBPUC           (1 << 8)        /* Data Bus Pull-up Configuration */
+#define                 AT91_MATRIX_EBI_DBPU_ON                 (0 << 8)
+#define                 AT91_MATRIX_EBI_DBPU_OFF                (1 << 8)
+#define         AT91_MATRIX_EBI_VDDIOMSEL       (1 << 16)       /* Memory voltage selection */
+#define                 AT91_MATRIX_EBI_VDDIOMSEL_1_8V          (0 << 16)
+#define                 AT91_MATRIX_EBI_VDDIOMSEL_3_3V          (1 << 16)
+#define         AT91_MATRIX_EBI_EBI_IOSR        (1 << 17)       /* EBI I/O slew rate selection */
+#define                 AT91_MATRIX_EBI_EBI_IOSR_REDUCED        (0 << 17)
+#define                 AT91_MATRIX_EBI_EBI_IOSR_NORMAL         (1 << 17)
+#define         AT91_MATRIX_EBI_DDR_IOSR        (1 << 18)       /* DDR2 dedicated port I/O slew rate selection */
+#define                 AT91_MATRIX_EBI_DDR_IOSR_REDUCED        (0 << 18)
+#define                 AT91_MATRIX_EBI_DDR_IOSR_NORMAL         (1 << 18)
+#define         AT91_MATRIX_NFD0_SELECT         (1 << 24)       /* NAND Flash Data Bus Selection */
+#define                 AT91_MATRIX_NFD0_ON_D0                  (0 << 24)
+#define                 AT91_MATRIX_NFD0_ON_D16                 (1 << 24)
+#define         AT91_MATRIX_DDR_MP_EN           (1 << 25)       /* DDR Multi-port Enable */
+#define                 AT91_MATRIX_MP_OFF                      (0 << 25)
+#define                 AT91_MATRIX_MP_ON                       (1 << 25)
+
+#define AT91_MATRIX_WPMR        (AT91_MATRIX + 0x1E4)   /* Write Protect Mode Register */
+#define         AT91_MATRIX_WPMR_WPEN           (1 << 0)        /* Write Protect ENable */
+#define                 AT91_MATRIX_WPMR_WP_WPDIS               (0 << 0)
+#define                 AT91_MATRIX_WPMR_WP_WPEN                (1 << 0)
+#define         AT91_MATRIX_WPMR_WPKEY          (0xFFFFFF << 8) /* Write Protect KEY */
+
+#define AT91_MATRIX_WPSR        (AT91_MATRIX + 0x1E8)   /* Write Protect Status Register */
+#define         AT91_MATRIX_WPSR_WPVS           (1 << 0)        /* Write Protect Violation Status */
+#define                 AT91_MATRIX_WPSR_NO_WPV         (0 << 0)
+#define                 AT91_MATRIX_WPSR_WPV            (1 << 0)
+#define         AT91_MATRIX_WPSR_WPVSRC         (0xFFFF << 8)   /* Write Protect Violation Source */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index 73d2fd209ce4..b6504c19d55c 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -25,6 +25,7 @@
 #define ARCH_ID_AT91SAM9G45MRL  0x819b05a2      /* aka 9G45-ES2 & non ES lots */
 #define ARCH_ID_AT91SAM9G45ES   0x819b05a1      /* 9G45-ES (Engineering Sample) */
 #define ARCH_ID_AT91SAM9X5      0x819a05a0
+#define ARCH_ID_AT91SAM9N12     0x819a07a0
 
 #define ARCH_ID_AT91SAM9XE128   0x329973a0
 #define ARCH_ID_AT91SAM9XE256   0x329a93a0
@@ -71,6 +72,9 @@ enum at91_soc_type {
         /* SAM9X5 */
         AT91_SOC_SAM9X5,
 
+        /* SAM9N12 */
+        AT91_SOC_SAM9N12,
+
         /* Unknown type */
         AT91_SOC_NONE
 };
@@ -177,6 +181,12 @@ static inline int at91_soc_is_detected(void)
 #define cpu_is_at91sam9x25()    (0)
 #endif
 
+#ifdef CONFIG_SOC_AT91SAM9N12
+#define cpu_is_at91sam9n12()    (at91_soc_initdata.type == AT91_SOC_SAM9N12)
+#else
+#define cpu_is_at91sam9n12()    (0)
+#endif
+
 /*
  * Since this is ARM, we will never run on any AVR32 CPU. But these
  * definitions may reduce clutter in common drivers.
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index ef5786299c60..09242b67d277 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -32,6 +32,7 @@
 #include <mach/at91sam9rl.h>
 #include <mach/at91sam9g45.h>
 #include <mach/at91sam9x5.h>
+#include <mach/at91sam9n12.h>
 
 /*
  * On all at91 except rm9200 and x40 have the System Controller starts
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index f44a2e7272e3..944bffb08991 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -143,6 +143,11 @@ static void __init soc_detect(u32 dbgu_base)
                 at91_soc_initdata.type = AT91_SOC_SAM9X5;
                 at91_boot_soc = at91sam9x5_soc;
                 break;
+
+        case ARCH_ID_AT91SAM9N12:
+                at91_soc_initdata.type = AT91_SOC_SAM9N12;
+                at91_boot_soc = at91sam9n12_soc;
+                break;
         }
 
         /* at91sam9g10 */
@@ -210,6 +215,7 @@ static const char *soc_name[] = {
         [AT91_SOC_SAM9G45]      = "at91sam9g45",
         [AT91_SOC_SAM9RL]       = "at91sam9rl",
         [AT91_SOC_SAM9X5]       = "at91sam9x5",
+        [AT91_SOC_SAM9N12]      = "at91sam9n12",
         [AT91_SOC_NONE]         = "Unknown"
 };
 
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
index 683dddfd8b13..a9cfeb153719 100644
--- a/arch/arm/mach-at91/soc.h
+++ b/arch/arm/mach-at91/soc.h
@@ -20,6 +20,7 @@ extern struct at91_init_soc at91sam9263_soc;
 extern struct at91_init_soc at91sam9g45_soc;
 extern struct at91_init_soc at91sam9rl_soc;
 extern struct at91_init_soc at91sam9x5_soc;
+extern struct at91_init_soc at91sam9n12_soc;
 
 static inline int at91_soc_is_enabled(void)
 {
@@ -53,3 +54,7 @@ static inline int at91_soc_is_enabled(void)
 #if !defined(CONFIG_SOC_AT91SAM9X5)
 #define at91sam9x5_soc  at91_boot_soc
 #endif
+
+#if !defined(CONFIG_SOC_AT91SAM9N12)
+#define at91sam9n12_soc at91_boot_soc
+#endif