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authorAndrew Victor <linux@maxim.org.za>2009-12-15 15:57:27 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-01-20 07:34:06 -0500
commit5e38efae9635436efa1e4952cf953085839a7121 (patch)
tree2e9d8a7b0476c72f8e876929416f940e78efece4 /arch/arm/mach-at91
parent74d2e4f8d79ae0c4b6ec027958d5b18058662eea (diff)
ARM: 5850/1: [AT91] AT572D940HF processor support
Add support for the Atmel AT572D940HF processor (DIOPSIS range). This processor integrates an ARM926 core, a DSP and the SoC peripherals usually found on an AT91 processor (USART, SSC, SPI, TWI, CAN, etc) Signed-off-by: Antonio R. Costa <costa.antonior@gmail.com> Signed-off-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-at91')
-rw-r--r--arch/arm/mach-at91/Kconfig6
-rw-r--r--arch/arm/mach-at91/Makefile1
-rw-r--r--arch/arm/mach-at91/at572d940hf.c377
-rw-r--r--arch/arm/mach-at91/at572d940hf_devices.c970
-rw-r--r--arch/arm/mach-at91/clock.c8
-rw-r--r--arch/arm/mach-at91/clock.h2
-rw-r--r--arch/arm/mach-at91/generic.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at572d940hf.h123
-rw-r--r--arch/arm/mach-at91/include/mach/at572d940hf_matrix.h123
-rw-r--r--arch/arm/mach-at91/include/mach/at91_pmc.h1
-rw-r--r--arch/arm/mach-at91/include/mach/board.h5
-rw-r--r--arch/arm/mach-at91/include/mach/cpu.h8
-rw-r--r--arch/arm/mach-at91/include/mach/hardware.h2
-rw-r--r--arch/arm/mach-at91/include/mach/timex.h5
14 files changed, 1628 insertions, 5 deletions
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 0b2ee953f164..c67fa3b7eeb1 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -89,6 +89,12 @@ config ARCH_AT91CAP9
89 select GENERIC_CLOCKEVENTS 89 select GENERIC_CLOCKEVENTS
90 select HAVE_FB_ATMEL 90 select HAVE_FB_ATMEL
91 91
92config ARCH_AT572D940HF
93 bool "AT572D940HF"
94 select CPU_ARM926T
95 select GENERIC_TIME
96 select GENERIC_CLOCKEVENTS
97
92config ARCH_AT91X40 98config ARCH_AT91X40
93 bool "AT91x40" 99 bool "AT91x40"
94 100
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 709fbad4a3ee..8ddce96b6aa5 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devi
19obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o 19obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
20 obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o 20 obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
21obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o 21obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
22obj-$(CONFIG_ARCH_AT572D940HF) += at572d940hf.o at91sam926x_time.o at572d940hf_devices.o sam9_smc.o
22obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o 23obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
23 24
24# AT91RM9200 board-specific support 25# AT91RM9200 board-specific support
diff --git a/arch/arm/mach-at91/at572d940hf.c b/arch/arm/mach-at91/at572d940hf.c
new file mode 100644
index 000000000000..a6b9c68c003a
--- /dev/null
+++ b/arch/arm/mach-at91/at572d940hf.c
@@ -0,0 +1,377 @@
1/*
2 * arch/arm/mach-at91/at572d940hf.c
3 *
4 * Antonio R. Costa <costa.antonior@gmail.com>
5 * Copyright (C) 2008 Atmel
6 *
7 * Copyright (C) 2005 SAN People
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#include <linux/module.h>
26
27#include <asm/mach/irq.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30#include <mach/at572d940hf.h>
31#include <mach/at91_pmc.h>
32#include <mach/at91_rstc.h>
33
34#include "generic.h"
35#include "clock.h"
36
37static struct map_desc at572d940hf_io_desc[] __initdata = {
38 {
39 .virtual = AT91_VA_BASE_SYS,
40 .pfn = __phys_to_pfn(AT91_BASE_SYS),
41 .length = SZ_16K,
42 .type = MT_DEVICE,
43 }, {
44 .virtual = AT91_IO_VIRT_BASE - AT572D940HF_SRAM_SIZE,
45 .pfn = __phys_to_pfn(AT572D940HF_SRAM_BASE),
46 .length = AT572D940HF_SRAM_SIZE,
47 .type = MT_DEVICE,
48 },
49};
50
51/* --------------------------------------------------------------------
52 * Clocks
53 * -------------------------------------------------------------------- */
54
55/*
56 * The peripheral clocks.
57 */
58static struct clk pioA_clk = {
59 .name = "pioA_clk",
60 .pmc_mask = 1 << AT572D940HF_ID_PIOA,
61 .type = CLK_TYPE_PERIPHERAL,
62};
63static struct clk pioB_clk = {
64 .name = "pioB_clk",
65 .pmc_mask = 1 << AT572D940HF_ID_PIOB,
66 .type = CLK_TYPE_PERIPHERAL,
67};
68static struct clk pioC_clk = {
69 .name = "pioC_clk",
70 .pmc_mask = 1 << AT572D940HF_ID_PIOC,
71 .type = CLK_TYPE_PERIPHERAL,
72};
73static struct clk macb_clk = {
74 .name = "macb_clk",
75 .pmc_mask = 1 << AT572D940HF_ID_EMAC,
76 .type = CLK_TYPE_PERIPHERAL,
77};
78static struct clk usart0_clk = {
79 .name = "usart0_clk",
80 .pmc_mask = 1 << AT572D940HF_ID_US0,
81 .type = CLK_TYPE_PERIPHERAL,
82};
83static struct clk usart1_clk = {
84 .name = "usart1_clk",
85 .pmc_mask = 1 << AT572D940HF_ID_US1,
86 .type = CLK_TYPE_PERIPHERAL,
87};
88static struct clk usart2_clk = {
89 .name = "usart2_clk",
90 .pmc_mask = 1 << AT572D940HF_ID_US2,
91 .type = CLK_TYPE_PERIPHERAL,
92};
93static struct clk mmc_clk = {
94 .name = "mci_clk",
95 .pmc_mask = 1 << AT572D940HF_ID_MCI,
96 .type = CLK_TYPE_PERIPHERAL,
97};
98static struct clk udc_clk = {
99 .name = "udc_clk",
100 .pmc_mask = 1 << AT572D940HF_ID_UDP,
101 .type = CLK_TYPE_PERIPHERAL,
102};
103static struct clk twi0_clk = {
104 .name = "twi0_clk",
105 .pmc_mask = 1 << AT572D940HF_ID_TWI0,
106 .type = CLK_TYPE_PERIPHERAL,
107};
108static struct clk spi0_clk = {
109 .name = "spi0_clk",
110 .pmc_mask = 1 << AT572D940HF_ID_SPI0,
111 .type = CLK_TYPE_PERIPHERAL,
112};
113static struct clk spi1_clk = {
114 .name = "spi1_clk",
115 .pmc_mask = 1 << AT572D940HF_ID_SPI1,
116 .type = CLK_TYPE_PERIPHERAL,
117};
118static struct clk ssc0_clk = {
119 .name = "ssc0_clk",
120 .pmc_mask = 1 << AT572D940HF_ID_SSC0,
121 .type = CLK_TYPE_PERIPHERAL,
122};
123static struct clk ssc1_clk = {
124 .name = "ssc1_clk",
125 .pmc_mask = 1 << AT572D940HF_ID_SSC1,
126 .type = CLK_TYPE_PERIPHERAL,
127};
128static struct clk ssc2_clk = {
129 .name = "ssc2_clk",
130 .pmc_mask = 1 << AT572D940HF_ID_SSC2,
131 .type = CLK_TYPE_PERIPHERAL,
132};
133static struct clk tc0_clk = {
134 .name = "tc0_clk",
135 .pmc_mask = 1 << AT572D940HF_ID_TC0,
136 .type = CLK_TYPE_PERIPHERAL,
137};
138static struct clk tc1_clk = {
139 .name = "tc1_clk",
140 .pmc_mask = 1 << AT572D940HF_ID_TC1,
141 .type = CLK_TYPE_PERIPHERAL,
142};
143static struct clk tc2_clk = {
144 .name = "tc2_clk",
145 .pmc_mask = 1 << AT572D940HF_ID_TC2,
146 .type = CLK_TYPE_PERIPHERAL,
147};
148static struct clk ohci_clk = {
149 .name = "ohci_clk",
150 .pmc_mask = 1 << AT572D940HF_ID_UHP,
151 .type = CLK_TYPE_PERIPHERAL,
152};
153static struct clk ssc3_clk = {
154 .name = "ssc3_clk",
155 .pmc_mask = 1 << AT572D940HF_ID_SSC3,
156 .type = CLK_TYPE_PERIPHERAL,
157};
158static struct clk twi1_clk = {
159 .name = "twi1_clk",
160 .pmc_mask = 1 << AT572D940HF_ID_TWI1,
161 .type = CLK_TYPE_PERIPHERAL,
162};
163static struct clk can0_clk = {
164 .name = "can0_clk",
165 .pmc_mask = 1 << AT572D940HF_ID_CAN0,
166 .type = CLK_TYPE_PERIPHERAL,
167};
168static struct clk can1_clk = {
169 .name = "can1_clk",
170 .pmc_mask = 1 << AT572D940HF_ID_CAN1,
171 .type = CLK_TYPE_PERIPHERAL,
172};
173static struct clk mAgicV_clk = {
174 .name = "mAgicV_clk",
175 .pmc_mask = 1 << AT572D940HF_ID_MSIRQ0,
176 .type = CLK_TYPE_PERIPHERAL,
177};
178
179
180static struct clk *periph_clocks[] __initdata = {
181 &pioA_clk,
182 &pioB_clk,
183 &pioC_clk,
184 &macb_clk,
185 &usart0_clk,
186 &usart1_clk,
187 &usart2_clk,
188 &mmc_clk,
189 &udc_clk,
190 &twi0_clk,
191 &spi0_clk,
192 &spi1_clk,
193 &ssc0_clk,
194 &ssc1_clk,
195 &ssc2_clk,
196 &tc0_clk,
197 &tc1_clk,
198 &tc2_clk,
199 &ohci_clk,
200 &ssc3_clk,
201 &twi1_clk,
202 &can0_clk,
203 &can1_clk,
204 &mAgicV_clk,
205 /* irq0 .. irq2 */
206};
207
208/*
209 * The five programmable clocks.
210 * You must configure pin multiplexing to bring these signals out.
211 */
212static struct clk pck0 = {
213 .name = "pck0",
214 .pmc_mask = AT91_PMC_PCK0,
215 .type = CLK_TYPE_PROGRAMMABLE,
216 .id = 0,
217};
218static struct clk pck1 = {
219 .name = "pck1",
220 .pmc_mask = AT91_PMC_PCK1,
221 .type = CLK_TYPE_PROGRAMMABLE,
222 .id = 1,
223};
224static struct clk pck2 = {
225 .name = "pck2",
226 .pmc_mask = AT91_PMC_PCK2,
227 .type = CLK_TYPE_PROGRAMMABLE,
228 .id = 2,
229};
230static struct clk pck3 = {
231 .name = "pck3",
232 .pmc_mask = AT91_PMC_PCK3,
233 .type = CLK_TYPE_PROGRAMMABLE,
234 .id = 3,
235};
236
237static struct clk mAgicV_mem_clk = {
238 .name = "mAgicV_mem_clk",
239 .pmc_mask = AT91_PMC_PCK4,
240 .type = CLK_TYPE_PROGRAMMABLE,
241 .id = 4,
242};
243
244/* HClocks */
245static struct clk hck0 = {
246 .name = "hck0",
247 .pmc_mask = AT91_PMC_HCK0,
248 .type = CLK_TYPE_SYSTEM,
249 .id = 0,
250};
251static struct clk hck1 = {
252 .name = "hck1",
253 .pmc_mask = AT91_PMC_HCK1,
254 .type = CLK_TYPE_SYSTEM,
255 .id = 1,
256};
257
258static void __init at572d940hf_register_clocks(void)
259{
260 int i;
261
262 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
263 clk_register(periph_clocks[i]);
264
265 clk_register(&pck0);
266 clk_register(&pck1);
267 clk_register(&pck2);
268 clk_register(&pck3);
269 clk_register(&mAgicV_mem_clk);
270
271 clk_register(&hck0);
272 clk_register(&hck1);
273}
274
275/* --------------------------------------------------------------------
276 * GPIO
277 * -------------------------------------------------------------------- */
278
279static struct at91_gpio_bank at572d940hf_gpio[] = {
280 {
281 .id = AT572D940HF_ID_PIOA,
282 .offset = AT91_PIOA,
283 .clock = &pioA_clk,
284 }, {
285 .id = AT572D940HF_ID_PIOB,
286 .offset = AT91_PIOB,
287 .clock = &pioB_clk,
288 }, {
289 .id = AT572D940HF_ID_PIOC,
290 .offset = AT91_PIOC,
291 .clock = &pioC_clk,
292 }
293};
294
295static void at572d940hf_reset(void)
296{
297 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
298}
299
300
301/* --------------------------------------------------------------------
302 * AT572D940HF processor initialization
303 * -------------------------------------------------------------------- */
304
305void __init at572d940hf_initialize(unsigned long main_clock)
306{
307 /* Map peripherals */
308 iotable_init(at572d940hf_io_desc, ARRAY_SIZE(at572d940hf_io_desc));
309
310 at91_arch_reset = at572d940hf_reset;
311 at91_extern_irq = (1 << AT572D940HF_ID_IRQ0) | (1 << AT572D940HF_ID_IRQ1)
312 | (1 << AT572D940HF_ID_IRQ2);
313
314 /* Init clock subsystem */
315 at91_clock_init(main_clock);
316
317 /* Register the processor-specific clocks */
318 at572d940hf_register_clocks();
319
320 /* Register GPIO subsystem */
321 at91_gpio_init(at572d940hf_gpio, 3);
322}
323
324/* --------------------------------------------------------------------
325 * Interrupt initialization
326 * -------------------------------------------------------------------- */
327
328/*
329 * The default interrupt priority levels (0 = lowest, 7 = highest).
330 */
331static unsigned int at572d940hf_default_irq_priority[NR_AIC_IRQS] __initdata = {
332 7, /* Advanced Interrupt Controller */
333 7, /* System Peripherals */
334 0, /* Parallel IO Controller A */
335 0, /* Parallel IO Controller B */
336 0, /* Parallel IO Controller C */
337 3, /* Ethernet */
338 6, /* USART 0 */
339 6, /* USART 1 */
340 6, /* USART 2 */
341 0, /* Multimedia Card Interface */
342 4, /* USB Device Port */
343 0, /* Two-Wire Interface 0 */
344 6, /* Serial Peripheral Interface 0 */
345 6, /* Serial Peripheral Interface 1 */
346 5, /* Serial Synchronous Controller 0 */
347 5, /* Serial Synchronous Controller 1 */
348 5, /* Serial Synchronous Controller 2 */
349 0, /* Timer Counter 0 */
350 0, /* Timer Counter 1 */
351 0, /* Timer Counter 2 */
352 3, /* USB Host port */
353 3, /* Serial Synchronous Controller 3 */
354 0, /* Two-Wire Interface 1 */
355 0, /* CAN Controller 0 */
356 0, /* CAN Controller 1 */
357 0, /* mAgicV HALT line */
358 0, /* mAgicV SIRQ0 line */
359 0, /* mAgicV exception line */
360 0, /* mAgicV end of DMA line */
361 0, /* Advanced Interrupt Controller */
362 0, /* Advanced Interrupt Controller */
363 0, /* Advanced Interrupt Controller */
364};
365
366void __init at572d940hf_init_interrupts(unsigned int priority[NR_AIC_IRQS])
367{
368 if (!priority)
369 priority = at572d940hf_default_irq_priority;
370
371 /* Initialize the AIC interrupt controller */
372 at91_aic_init(priority);
373
374 /* Enable GPIO interrupts */
375 at91_gpio_irq_setup();
376}
377
diff --git a/arch/arm/mach-at91/at572d940hf_devices.c b/arch/arm/mach-at91/at572d940hf_devices.c
new file mode 100644
index 000000000000..0fc20a240782
--- /dev/null
+++ b/arch/arm/mach-at91/at572d940hf_devices.c
@@ -0,0 +1,970 @@
1/*
2 * arch/arm/mach-at91/at572d940hf_devices.c
3 *
4 * Copyright (C) 2008 Atmel Antonio R. Costa <costa.antonior@gmail.com>
5 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
6 * Copyright (C) 2005 David Brownell
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26
27#include <linux/dma-mapping.h>
28#include <linux/platform_device.h>
29
30#include <mach/board.h>
31#include <mach/gpio.h>
32#include <mach/at572d940hf.h>
33#include <mach/at572d940hf_matrix.h>
34#include <mach/at91sam9_smc.h>
35
36#include "generic.h"
37#include "sam9_smc.h"
38
39
40/* --------------------------------------------------------------------
41 * USB Host
42 * -------------------------------------------------------------------- */
43
44#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
45static u64 ohci_dmamask = DMA_BIT_MASK(32);
46static struct at91_usbh_data usbh_data;
47
48static struct resource usbh_resources[] = {
49 [0] = {
50 .start = AT572D940HF_UHP_BASE,
51 .end = AT572D940HF_UHP_BASE + SZ_1M - 1,
52 .flags = IORESOURCE_MEM,
53 },
54 [1] = {
55 .start = AT572D940HF_ID_UHP,
56 .end = AT572D940HF_ID_UHP,
57 .flags = IORESOURCE_IRQ,
58 },
59};
60
61static struct platform_device at572d940hf_usbh_device = {
62 .name = "at91_ohci",
63 .id = -1,
64 .dev = {
65 .dma_mask = &ohci_dmamask,
66 .coherent_dma_mask = DMA_BIT_MASK(32),
67 .platform_data = &usbh_data,
68 },
69 .resource = usbh_resources,
70 .num_resources = ARRAY_SIZE(usbh_resources),
71};
72
73void __init at91_add_device_usbh(struct at91_usbh_data *data)
74{
75 if (!data)
76 return;
77
78 usbh_data = *data;
79 platform_device_register(&at572d940hf_usbh_device);
80
81}
82#else
83void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
84#endif
85
86
87/* --------------------------------------------------------------------
88 * USB Device (Gadget)
89 * -------------------------------------------------------------------- */
90
91#ifdef CONFIG_USB_GADGET_AT91
92static struct at91_udc_data udc_data;
93
94static struct resource udc_resources[] = {
95 [0] = {
96 .start = AT572D940HF_BASE_UDP,
97 .end = AT572D940HF_BASE_UDP + SZ_16K - 1,
98 .flags = IORESOURCE_MEM,
99 },
100 [1] = {
101 .start = AT572D940HF_ID_UDP,
102 .end = AT572D940HF_ID_UDP,
103 .flags = IORESOURCE_IRQ,
104 },
105};
106
107static struct platform_device at572d940hf_udc_device = {
108 .name = "at91_udc",
109 .id = -1,
110 .dev = {
111 .platform_data = &udc_data,
112 },
113 .resource = udc_resources,
114 .num_resources = ARRAY_SIZE(udc_resources),
115};
116
117void __init at91_add_device_udc(struct at91_udc_data *data)
118{
119 if (!data)
120 return;
121
122 if (data->vbus_pin) {
123 at91_set_gpio_input(data->vbus_pin, 0);
124 at91_set_deglitch(data->vbus_pin, 1);
125 }
126
127 /* Pullup pin is handled internally */
128
129 udc_data = *data;
130 platform_device_register(&at572d940hf_udc_device);
131}
132#else
133void __init at91_add_device_udc(struct at91_udc_data *data) {}
134#endif
135
136
137/* --------------------------------------------------------------------
138 * Ethernet
139 * -------------------------------------------------------------------- */
140
141#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
142static u64 eth_dmamask = DMA_BIT_MASK(32);
143static struct at91_eth_data eth_data;
144
145static struct resource eth_resources[] = {
146 [0] = {
147 .start = AT572D940HF_BASE_EMAC,
148 .end = AT572D940HF_BASE_EMAC + SZ_16K - 1,
149 .flags = IORESOURCE_MEM,
150 },
151 [1] = {
152 .start = AT572D940HF_ID_EMAC,
153 .end = AT572D940HF_ID_EMAC,
154 .flags = IORESOURCE_IRQ,
155 },
156};
157
158static struct platform_device at572d940hf_eth_device = {
159 .name = "macb",
160 .id = -1,
161 .dev = {
162 .dma_mask = &eth_dmamask,
163 .coherent_dma_mask = DMA_BIT_MASK(32),
164 .platform_data = &eth_data,
165 },
166 .resource = eth_resources,
167 .num_resources = ARRAY_SIZE(eth_resources),
168};
169
170void __init at91_add_device_eth(struct at91_eth_data *data)
171{
172 if (!data)
173 return;
174
175 if (data->phy_irq_pin) {
176 at91_set_gpio_input(data->phy_irq_pin, 0);
177 at91_set_deglitch(data->phy_irq_pin, 1);
178 }
179
180 /* Only RMII is supported */
181 data->is_rmii = 1;
182
183 /* Pins used for RMII */
184 at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXCK_EREFCK */
185 at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
186 at91_set_A_periph(AT91_PIN_PA18, 0); /* ERX0 */
187 at91_set_A_periph(AT91_PIN_PA19, 0); /* ERX1 */
188 at91_set_A_periph(AT91_PIN_PA20, 0); /* ERXER */
189 at91_set_A_periph(AT91_PIN_PA23, 0); /* ETXEN */
190 at91_set_A_periph(AT91_PIN_PA21, 0); /* ETX0 */
191 at91_set_A_periph(AT91_PIN_PA22, 0); /* ETX1 */
192 at91_set_A_periph(AT91_PIN_PA13, 0); /* EMDIO */
193 at91_set_A_periph(AT91_PIN_PA14, 0); /* EMDC */
194
195 eth_data = *data;
196 platform_device_register(&at572d940hf_eth_device);
197}
198#else
199void __init at91_add_device_eth(struct at91_eth_data *data) {}
200#endif
201
202
203/* --------------------------------------------------------------------
204 * MMC / SD
205 * -------------------------------------------------------------------- */
206
207#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
208static u64 mmc_dmamask = DMA_BIT_MASK(32);
209static struct at91_mmc_data mmc_data;
210
211static struct resource mmc_resources[] = {
212 [0] = {
213 .start = AT572D940HF_BASE_MCI,
214 .end = AT572D940HF_BASE_MCI + SZ_16K - 1,
215 .flags = IORESOURCE_MEM,
216 },
217 [1] = {
218 .start = AT572D940HF_ID_MCI,
219 .end = AT572D940HF_ID_MCI,
220 .flags = IORESOURCE_IRQ,
221 },
222};
223
224static struct platform_device at572d940hf_mmc_device = {
225 .name = "at91_mci",
226 .id = -1,
227 .dev = {
228 .dma_mask = &mmc_dmamask,
229 .coherent_dma_mask = DMA_BIT_MASK(32),
230 .platform_data = &mmc_data,
231 },
232 .resource = mmc_resources,
233 .num_resources = ARRAY_SIZE(mmc_resources),
234};
235
236void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
237{
238 if (!data)
239 return;
240
241 /* input/irq */
242 if (data->det_pin) {
243 at91_set_gpio_input(data->det_pin, 1);
244 at91_set_deglitch(data->det_pin, 1);
245 }
246 if (data->wp_pin)
247 at91_set_gpio_input(data->wp_pin, 1);
248 if (data->vcc_pin)
249 at91_set_gpio_output(data->vcc_pin, 0);
250
251 /* CLK */
252 at91_set_A_periph(AT91_PIN_PC22, 0);
253
254 /* CMD */
255 at91_set_A_periph(AT91_PIN_PC23, 1);
256
257 /* DAT0, maybe DAT1..DAT3 */
258 at91_set_A_periph(AT91_PIN_PC24, 1);
259 if (data->wire4) {
260 at91_set_A_periph(AT91_PIN_PC25, 1);
261 at91_set_A_periph(AT91_PIN_PC26, 1);
262 at91_set_A_periph(AT91_PIN_PC27, 1);
263 }
264
265 mmc_data = *data;
266 platform_device_register(&at572d940hf_mmc_device);
267}
268#else
269void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
270#endif
271
272
273/* --------------------------------------------------------------------
274 * NAND / SmartMedia
275 * -------------------------------------------------------------------- */
276
277#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
278static struct atmel_nand_data nand_data;
279
280#define NAND_BASE AT91_CHIPSELECT_3
281
282static struct resource nand_resources[] = {
283 {
284 .start = NAND_BASE,
285 .end = NAND_BASE + SZ_256M - 1,
286 .flags = IORESOURCE_MEM,
287 }
288};
289
290static struct platform_device at572d940hf_nand_device = {
291 .name = "atmel_nand",
292 .id = -1,
293 .dev = {
294 .platform_data = &nand_data,
295 },
296 .resource = nand_resources,
297 .num_resources = ARRAY_SIZE(nand_resources),
298};
299
300void __init at91_add_device_nand(struct atmel_nand_data *data)
301{
302 unsigned long csa;
303
304 if (!data)
305 return;
306
307 csa = at91_sys_read(AT91_MATRIX_EBICSA);
308 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
309
310 /* enable pin */
311 if (data->enable_pin)
312 at91_set_gpio_output(data->enable_pin, 1);
313
314 /* ready/busy pin */
315 if (data->rdy_pin)
316 at91_set_gpio_input(data->rdy_pin, 1);
317
318 /* card detect pin */
319 if (data->det_pin)
320 at91_set_gpio_input(data->det_pin, 1);
321
322 at91_set_A_periph(AT91_PIN_PB28, 0); /* A[22] */
323 at91_set_B_periph(AT91_PIN_PA28, 0); /* NANDOE */
324 at91_set_B_periph(AT91_PIN_PA29, 0); /* NANDWE */
325
326 nand_data = *data;
327 platform_device_register(&at572d940hf_nand_device);
328}
329
330#else
331void __init at91_add_device_nand(struct atmel_nand_data *data) {}
332#endif
333
334
335/* --------------------------------------------------------------------
336 * TWI (i2c)
337 * -------------------------------------------------------------------- */
338
339/*
340 * Prefer the GPIO code since the TWI controller isn't robust
341 * (gets overruns and underruns under load) and can only issue
342 * repeated STARTs in one scenario (the driver doesn't yet handle them).
343 */
344
345#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
346
347static struct i2c_gpio_platform_data pdata = {
348 .sda_pin = AT91_PIN_PC7,
349 .sda_is_open_drain = 1,
350 .scl_pin = AT91_PIN_PC8,
351 .scl_is_open_drain = 1,
352 .udelay = 2, /* ~100 kHz */
353};
354
355static struct platform_device at572d940hf_twi_device {
356 .name = "i2c-gpio",
357 .id = -1,
358 .dev.platform_data = &pdata,
359};
360
361void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
362{
363 at91_set_GPIO_periph(AT91_PIN_PC7, 1); /* TWD (SDA) */
364 at91_set_multi_drive(AT91_PIN_PC7, 1);
365
366 at91_set_GPIO_periph(AT91_PIN_PA8, 1); /* TWCK (SCL) */
367 at91_set_multi_drive(AT91_PIN_PC8, 1);
368
369 i2c_register_board_info(0, devices, nr_devices);
370 platform_device_register(&at572d940hf_twi_device);
371}
372
373#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
374
375static struct resource twi0_resources[] = {
376 [0] = {
377 .start = AT572D940HF_BASE_TWI0,
378 .end = AT572D940HF_BASE_TWI0 + SZ_16K - 1,
379 .flags = IORESOURCE_MEM,
380 },
381 [1] = {
382 .start = AT572D940HF_ID_TWI0,
383 .end = AT572D940HF_ID_TWI0,
384 .flags = IORESOURCE_IRQ,
385 },
386};
387
388static struct platform_device at572d940hf_twi0_device = {
389 .name = "at91_i2c",
390 .id = 0,
391 .resource = twi0_resources,
392 .num_resources = ARRAY_SIZE(twi0_resources),
393};
394
395static struct resource twi1_resources[] = {
396 [0] = {
397 .start = AT572D940HF_BASE_TWI1,
398 .end = AT572D940HF_BASE_TWI1 + SZ_16K - 1,
399 .flags = IORESOURCE_MEM,
400 },
401 [1] = {
402 .start = AT572D940HF_ID_TWI1,
403 .end = AT572D940HF_ID_TWI1,
404 .flags = IORESOURCE_IRQ,
405 },
406};
407
408static struct platform_device at572d940hf_twi1_device = {
409 .name = "at91_i2c",
410 .id = 1,
411 .resource = twi1_resources,
412 .num_resources = ARRAY_SIZE(twi1_resources),
413};
414
415void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
416{
417 /* pins used for TWI0 interface */
418 at91_set_A_periph(AT91_PIN_PC7, 0); /* TWD */
419 at91_set_multi_drive(AT91_PIN_PC7, 1);
420
421 at91_set_A_periph(AT91_PIN_PC8, 0); /* TWCK */
422 at91_set_multi_drive(AT91_PIN_PC8, 1);
423
424 /* pins used for TWI1 interface */
425 at91_set_A_periph(AT91_PIN_PC20, 0); /* TWD */
426 at91_set_multi_drive(AT91_PIN_PC20, 1);
427
428 at91_set_A_periph(AT91_PIN_PC21, 0); /* TWCK */
429 at91_set_multi_drive(AT91_PIN_PC21, 1);
430
431 i2c_register_board_info(0, devices, nr_devices);
432 platform_device_register(&at572d940hf_twi0_device);
433 platform_device_register(&at572d940hf_twi1_device);
434}
435#else
436void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
437#endif
438
439
440/* --------------------------------------------------------------------
441 * SPI
442 * -------------------------------------------------------------------- */
443
444#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
445static u64 spi_dmamask = DMA_BIT_MASK(32);
446
447static struct resource spi0_resources[] = {
448 [0] = {
449 .start = AT572D940HF_BASE_SPI0,
450 .end = AT572D940HF_BASE_SPI0 + SZ_16K - 1,
451 .flags = IORESOURCE_MEM,
452 },
453 [1] = {
454 .start = AT572D940HF_ID_SPI0,
455 .end = AT572D940HF_ID_SPI0,
456 .flags = IORESOURCE_IRQ,
457 },
458};
459
460static struct platform_device at572d940hf_spi0_device = {
461 .name = "atmel_spi",
462 .id = 0,
463 .dev = {
464 .dma_mask = &spi_dmamask,
465 .coherent_dma_mask = DMA_BIT_MASK(32),
466 },
467 .resource = spi0_resources,
468 .num_resources = ARRAY_SIZE(spi0_resources),
469};
470
471static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
472
473static struct resource spi1_resources[] = {
474 [0] = {
475 .start = AT572D940HF_BASE_SPI1,
476 .end = AT572D940HF_BASE_SPI1 + SZ_16K - 1,
477 .flags = IORESOURCE_MEM,
478 },
479 [1] = {
480 .start = AT572D940HF_ID_SPI1,
481 .end = AT572D940HF_ID_SPI1,
482 .flags = IORESOURCE_IRQ,
483 },
484};
485
486static struct platform_device at572d940hf_spi1_device = {
487 .name = "atmel_spi",
488 .id = 1,
489 .dev = {
490 .dma_mask = &spi_dmamask,
491 .coherent_dma_mask = DMA_BIT_MASK(32),
492 },
493 .resource = spi1_resources,
494 .num_resources = ARRAY_SIZE(spi1_resources),
495};
496
497static const unsigned spi1_standard_cs[4] = { AT91_PIN_PC3, AT91_PIN_PC4, AT91_PIN_PC5, AT91_PIN_PC6 };
498
499void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
500{
501 int i;
502 unsigned long cs_pin;
503 short enable_spi0 = 0;
504 short enable_spi1 = 0;
505
506 /* Choose SPI chip-selects */
507 for (i = 0; i < nr_devices; i++) {
508 if (devices[i].controller_data)
509 cs_pin = (unsigned long) devices[i].controller_data;
510 else if (devices[i].bus_num == 0)
511 cs_pin = spi0_standard_cs[devices[i].chip_select];
512 else
513 cs_pin = spi1_standard_cs[devices[i].chip_select];
514
515 if (devices[i].bus_num == 0)
516 enable_spi0 = 1;
517 else
518 enable_spi1 = 1;
519
520 /* enable chip-select pin */
521 at91_set_gpio_output(cs_pin, 1);
522
523 /* pass chip-select pin to driver */
524 devices[i].controller_data = (void *) cs_pin;
525 }
526
527 spi_register_board_info(devices, nr_devices);
528
529 /* Configure SPI bus(es) */
530 if (enable_spi0) {
531 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
532 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
533 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
534
535 at91_clock_associate("spi0_clk", &at572d940hf_spi0_device.dev, "spi_clk");
536 platform_device_register(&at572d940hf_spi0_device);
537 }
538 if (enable_spi1) {
539 at91_set_A_periph(AT91_PIN_PC0, 0); /* SPI1_MISO */
540 at91_set_A_periph(AT91_PIN_PC1, 0); /* SPI1_MOSI */
541 at91_set_A_periph(AT91_PIN_PC2, 0); /* SPI1_SPCK */
542
543 at91_clock_associate("spi1_clk", &at572d940hf_spi1_device.dev, "spi_clk");
544 platform_device_register(&at572d940hf_spi1_device);
545 }
546}
547#else
548void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
549#endif
550
551
552/* --------------------------------------------------------------------
553 * Timer/Counter blocks
554 * -------------------------------------------------------------------- */
555
556#ifdef CONFIG_ATMEL_TCLIB
557
558static struct resource tcb_resources[] = {
559 [0] = {
560 .start = AT572D940HF_BASE_TCB,
561 .end = AT572D940HF_BASE_TCB + SZ_16K - 1,
562 .flags = IORESOURCE_MEM,
563 },
564 [1] = {
565 .start = AT572D940HF_ID_TC0,
566 .end = AT572D940HF_ID_TC0,
567 .flags = IORESOURCE_IRQ,
568 },
569 [2] = {
570 .start = AT572D940HF_ID_TC1,
571 .end = AT572D940HF_ID_TC1,
572 .flags = IORESOURCE_IRQ,
573 },
574 [3] = {
575 .start = AT572D940HF_ID_TC2,
576 .end = AT572D940HF_ID_TC2,
577 .flags = IORESOURCE_IRQ,
578 },
579};
580
581static struct platform_device at572d940hf_tcb_device = {
582 .name = "atmel_tcb",
583 .id = 0,
584 .resource = tcb_resources,
585 .num_resources = ARRAY_SIZE(tcb_resources),
586};
587
588static void __init at91_add_device_tc(void)
589{
590 /* this chip has a separate clock and irq for each TC channel */
591 at91_clock_associate("tc0_clk", &at572d940hf_tcb_device.dev, "t0_clk");
592 at91_clock_associate("tc1_clk", &at572d940hf_tcb_device.dev, "t1_clk");
593 at91_clock_associate("tc2_clk", &at572d940hf_tcb_device.dev, "t2_clk");
594 platform_device_register(&at572d940hf_tcb_device);
595}
596#else
597static void __init at91_add_device_tc(void) { }
598#endif
599
600
601/* --------------------------------------------------------------------
602 * RTT
603 * -------------------------------------------------------------------- */
604
605static struct resource rtt_resources[] = {
606 {
607 .start = AT91_BASE_SYS + AT91_RTT,
608 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
609 .flags = IORESOURCE_MEM,
610 }
611};
612
613static struct platform_device at572d940hf_rtt_device = {
614 .name = "at91_rtt",
615 .id = 0,
616 .resource = rtt_resources,
617 .num_resources = ARRAY_SIZE(rtt_resources),
618};
619
620static void __init at91_add_device_rtt(void)
621{
622 platform_device_register(&at572d940hf_rtt_device);
623}
624
625
626/* --------------------------------------------------------------------
627 * Watchdog
628 * -------------------------------------------------------------------- */
629
630#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
631static struct platform_device at572d940hf_wdt_device = {
632 .name = "at91_wdt",
633 .id = -1,
634 .num_resources = 0,
635};
636
637static void __init at91_add_device_watchdog(void)
638{
639 platform_device_register(&at572d940hf_wdt_device);
640}
641#else
642static void __init at91_add_device_watchdog(void) {}
643#endif
644
645
646/* --------------------------------------------------------------------
647 * UART
648 * -------------------------------------------------------------------- */
649
650#if defined(CONFIG_SERIAL_ATMEL)
651static struct resource dbgu_resources[] = {
652 [0] = {
653 .start = AT91_VA_BASE_SYS + AT91_DBGU,
654 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
655 .flags = IORESOURCE_MEM,
656 },
657 [1] = {
658 .start = AT91_ID_SYS,
659 .end = AT91_ID_SYS,
660 .flags = IORESOURCE_IRQ,
661 },
662};
663
664static struct atmel_uart_data dbgu_data = {
665 .use_dma_tx = 0,
666 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
667 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
668};
669
670static u64 dbgu_dmamask = DMA_BIT_MASK(32);
671
672static struct platform_device at572d940hf_dbgu_device = {
673 .name = "atmel_usart",
674 .id = 0,
675 .dev = {
676 .dma_mask = &dbgu_dmamask,
677 .coherent_dma_mask = DMA_BIT_MASK(32),
678 .platform_data = &dbgu_data,
679 },
680 .resource = dbgu_resources,
681 .num_resources = ARRAY_SIZE(dbgu_resources),
682};
683
684static inline void configure_dbgu_pins(void)
685{
686 at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
687 at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
688}
689
690static struct resource uart0_resources[] = {
691 [0] = {
692 .start = AT572D940HF_BASE_US0,
693 .end = AT572D940HF_BASE_US0 + SZ_16K - 1,
694 .flags = IORESOURCE_MEM,
695 },
696 [1] = {
697 .start = AT572D940HF_ID_US0,
698 .end = AT572D940HF_ID_US0,
699 .flags = IORESOURCE_IRQ,
700 },
701};
702
703static struct atmel_uart_data uart0_data = {
704 .use_dma_tx = 1,
705 .use_dma_rx = 1,
706};
707
708static u64 uart0_dmamask = DMA_BIT_MASK(32);
709
710static struct platform_device at572d940hf_uart0_device = {
711 .name = "atmel_usart",
712 .id = 1,
713 .dev = {
714 .dma_mask = &uart0_dmamask,
715 .coherent_dma_mask = DMA_BIT_MASK(32),
716 .platform_data = &uart0_data,
717 },
718 .resource = uart0_resources,
719 .num_resources = ARRAY_SIZE(uart0_resources),
720};
721
722static inline void configure_usart0_pins(unsigned pins)
723{
724 at91_set_A_periph(AT91_PIN_PA8, 1); /* TXD0 */
725 at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
726
727 if (pins & ATMEL_UART_RTS)
728 at91_set_A_periph(AT91_PIN_PA10, 0); /* RTS0 */
729 if (pins & ATMEL_UART_CTS)
730 at91_set_A_periph(AT91_PIN_PA9, 0); /* CTS0 */
731}
732
733static struct resource uart1_resources[] = {
734 [0] = {
735 .start = AT572D940HF_BASE_US1,
736 .end = AT572D940HF_BASE_US1 + SZ_16K - 1,
737 .flags = IORESOURCE_MEM,
738 },
739 [1] = {
740 .start = AT572D940HF_ID_US1,
741 .end = AT572D940HF_ID_US1,
742 .flags = IORESOURCE_IRQ,
743 },
744};
745
746static struct atmel_uart_data uart1_data = {
747 .use_dma_tx = 1,
748 .use_dma_rx = 1,
749};
750
751static u64 uart1_dmamask = DMA_BIT_MASK(32);
752
753static struct platform_device at572d940hf_uart1_device = {
754 .name = "atmel_usart",
755 .id = 2,
756 .dev = {
757 .dma_mask = &uart1_dmamask,
758 .coherent_dma_mask = DMA_BIT_MASK(32),
759 .platform_data = &uart1_data,
760 },
761 .resource = uart1_resources,
762 .num_resources = ARRAY_SIZE(uart1_resources),
763};
764
765static inline void configure_usart1_pins(unsigned pins)
766{
767 at91_set_A_periph(AT91_PIN_PC10, 1); /* TXD1 */
768 at91_set_A_periph(AT91_PIN_PC9 , 0); /* RXD1 */
769
770 if (pins & ATMEL_UART_RTS)
771 at91_set_A_periph(AT91_PIN_PC12, 0); /* RTS1 */
772 if (pins & ATMEL_UART_CTS)
773 at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS1 */
774}
775
776static struct resource uart2_resources[] = {
777 [0] = {
778 .start = AT572D940HF_BASE_US2,
779 .end = AT572D940HF_BASE_US2 + SZ_16K - 1,
780 .flags = IORESOURCE_MEM,
781 },
782 [1] = {
783 .start = AT572D940HF_ID_US2,
784 .end = AT572D940HF_ID_US2,
785 .flags = IORESOURCE_IRQ,
786 },
787};
788
789static struct atmel_uart_data uart2_data = {
790 .use_dma_tx = 1,
791 .use_dma_rx = 1,
792};
793
794static u64 uart2_dmamask = DMA_BIT_MASK(32);
795
796static struct platform_device at572d940hf_uart2_device = {
797 .name = "atmel_usart",
798 .id = 3,
799 .dev = {
800 .dma_mask = &uart2_dmamask,
801 .coherent_dma_mask = DMA_BIT_MASK(32),
802 .platform_data = &uart2_data,
803 },
804 .resource = uart2_resources,
805 .num_resources = ARRAY_SIZE(uart2_resources),
806};
807
808static inline void configure_usart2_pins(unsigned pins)
809{
810 at91_set_A_periph(AT91_PIN_PC15, 1); /* TXD2 */
811 at91_set_A_periph(AT91_PIN_PC14, 0); /* RXD2 */
812
813 if (pins & ATMEL_UART_RTS)
814 at91_set_A_periph(AT91_PIN_PC17, 0); /* RTS2 */
815 if (pins & ATMEL_UART_CTS)
816 at91_set_A_periph(AT91_PIN_PC16, 0); /* CTS2 */
817}
818
819static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
820struct platform_device *atmel_default_console_device; /* the serial console device */
821
822void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
823{
824 struct platform_device *pdev;
825
826 switch (id) {
827 case 0: /* DBGU */
828 pdev = &at572d940hf_dbgu_device;
829 configure_dbgu_pins();
830 at91_clock_associate("mck", &pdev->dev, "usart");
831 break;
832 case AT572D940HF_ID_US0:
833 pdev = &at572d940hf_uart0_device;
834 configure_usart0_pins(pins);
835 at91_clock_associate("usart0_clk", &pdev->dev, "usart");
836 break;
837 case AT572D940HF_ID_US1:
838 pdev = &at572d940hf_uart1_device;
839 configure_usart1_pins(pins);
840 at91_clock_associate("usart1_clk", &pdev->dev, "usart");
841 break;
842 case AT572D940HF_ID_US2:
843 pdev = &at572d940hf_uart2_device;
844 configure_usart2_pins(pins);
845 at91_clock_associate("usart2_clk", &pdev->dev, "usart");
846 break;
847 default:
848 return;
849 }
850 pdev->id = portnr; /* update to mapped ID */
851
852 if (portnr < ATMEL_MAX_UART)
853 at91_uarts[portnr] = pdev;
854}
855
856void __init at91_set_serial_console(unsigned portnr)
857{
858 if (portnr < ATMEL_MAX_UART)
859 atmel_default_console_device = at91_uarts[portnr];
860}
861
862void __init at91_add_device_serial(void)
863{
864 int i;
865
866 for (i = 0; i < ATMEL_MAX_UART; i++) {
867 if (at91_uarts[i])
868 platform_device_register(at91_uarts[i]);
869 }
870
871 if (!atmel_default_console_device)
872 printk(KERN_INFO "AT91: No default serial console defined.\n");
873}
874
875#else
876void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
877void __init at91_set_serial_console(unsigned portnr) {}
878void __init at91_add_device_serial(void) {}
879#endif
880
881
882/* --------------------------------------------------------------------
883 * mAgic
884 * -------------------------------------------------------------------- */
885
886#ifdef CONFIG_MAGICV
887static struct resource mAgic_resources[] = {
888 {
889 .start = AT91_MAGIC_PM_BASE,
890 .end = AT91_MAGIC_PM_BASE + AT91_MAGIC_PM_SIZE - 1,
891 .flags = IORESOURCE_MEM,
892 },
893 {
894 .start = AT91_MAGIC_DM_I_BASE,
895 .end = AT91_MAGIC_DM_I_BASE + AT91_MAGIC_DM_I_SIZE - 1,
896 .flags = IORESOURCE_MEM,
897 },
898 {
899 .start = AT91_MAGIC_DM_F_BASE,
900 .end = AT91_MAGIC_DM_F_BASE + AT91_MAGIC_DM_F_SIZE - 1,
901 .flags = IORESOURCE_MEM,
902 },
903 {
904 .start = AT91_MAGIC_DM_DB_BASE,
905 .end = AT91_MAGIC_DM_DB_BASE + AT91_MAGIC_DM_DB_SIZE - 1,
906 .flags = IORESOURCE_MEM,
907 },
908 {
909 .start = AT91_MAGIC_REGS_BASE,
910 .end = AT91_MAGIC_REGS_BASE + AT91_MAGIC_REGS_SIZE - 1,
911 .flags = IORESOURCE_MEM,
912 },
913 {
914 .start = AT91_MAGIC_EXTPAGE_BASE,
915 .end = AT91_MAGIC_EXTPAGE_BASE + AT91_MAGIC_EXTPAGE_SIZE - 1,
916 .flags = IORESOURCE_MEM,
917 },
918 {
919 .start = AT572D940HF_ID_MSIRQ0,
920 .end = AT572D940HF_ID_MSIRQ0,
921 .flags = IORESOURCE_IRQ,
922 },
923 {
924 .start = AT572D940HF_ID_MHALT,
925 .end = AT572D940HF_ID_MHALT,
926 .flags = IORESOURCE_IRQ,
927 },
928 {
929 .start = AT572D940HF_ID_MEXC,
930 .end = AT572D940HF_ID_MEXC,
931 .flags = IORESOURCE_IRQ,
932 },
933 {
934 .start = AT572D940HF_ID_MEDMA,
935 .end = AT572D940HF_ID_MEDMA,
936 .flags = IORESOURCE_IRQ,
937 },
938};
939
940static struct platform_device mAgic_device = {
941 .name = "mAgic",
942 .id = -1,
943 .num_resources = ARRAY_SIZE(mAgic_resources),
944 .resource = mAgic_resources,
945};
946
947void __init at91_add_device_mAgic(void)
948{
949 platform_device_register(&mAgic_device);
950}
951#else
952void __init at91_add_device_mAgic(void) {}
953#endif
954
955
956/* -------------------------------------------------------------------- */
957
958/*
959 * These devices are always present and don't need any board-specific
960 * setup.
961 */
962static int __init at91_add_standard_devices(void)
963{
964 at91_add_device_rtt();
965 at91_add_device_watchdog();
966 at91_add_device_tc();
967 return 0;
968}
969
970arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index c042dcf4725f..7f7da439341f 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -29,6 +29,7 @@
29#include <mach/cpu.h> 29#include <mach/cpu.h>
30 30
31#include "clock.h" 31#include "clock.h"
32#include "generic.h"
32 33
33 34
34/* 35/*
@@ -628,7 +629,7 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
628 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); 629 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
629 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || 630 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
630 cpu_is_at91sam9263() || cpu_is_at91sam9g20() || 631 cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
631 cpu_is_at91sam9g10()) { 632 cpu_is_at91sam9g10() || cpu_is_at572d940hf()) {
632 uhpck.pmc_mask = AT91SAM926x_PMC_UHP; 633 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
633 udpck.pmc_mask = AT91SAM926x_PMC_UDP; 634 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
634 } else if (cpu_is_at91cap9()) { 635 } else if (cpu_is_at91cap9()) {
@@ -711,12 +712,13 @@ int __init at91_clock_init(unsigned long main_clock)
711 /* 712 /*
712 * USB HS clock init 713 * USB HS clock init
713 */ 714 */
714 if (cpu_has_utmi()) 715 if (cpu_has_utmi()) {
715 /* 716 /*
716 * multiplier is hard-wired to 40 717 * multiplier is hard-wired to 40
717 * (obtain the USB High Speed 480 MHz when input is 12 MHz) 718 * (obtain the USB High Speed 480 MHz when input is 12 MHz)
718 */ 719 */
719 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz; 720 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
721 }
720 722
721 /* 723 /*
722 * USB FS clock init 724 * USB FS clock init
@@ -746,7 +748,7 @@ int __init at91_clock_init(unsigned long main_clock)
746 mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ? 748 mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
747 freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ 749 freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
748 } else { 750 } else {
749 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ 751 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
750 } 752 }
751 753
752 /* Register the PMC's standard clocks */ 754 /* Register the PMC's standard clocks */
diff --git a/arch/arm/mach-at91/clock.h b/arch/arm/mach-at91/clock.h
index 1ba3b95ff359..6cf4b78e175d 100644
--- a/arch/arm/mach-at91/clock.h
+++ b/arch/arm/mach-at91/clock.h
@@ -22,7 +22,7 @@ struct clk {
22 struct clk *parent; 22 struct clk *parent;
23 u32 pmc_mask; 23 u32 pmc_mask;
24 void (*mode)(struct clk *, int); 24 void (*mode)(struct clk *, int);
25 unsigned id:2; /* PCK0..3, or 32k/main/a/b */ 25 unsigned id:3; /* PCK0..4, or 32k/main/a/b */
26 unsigned type; /* clock type */ 26 unsigned type; /* clock type */
27 u16 users; 27 u16 users;
28}; 28};
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 88e413b38480..65c3dc5ba0d0 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -17,6 +17,7 @@ extern void __init at91sam9rl_initialize(unsigned long main_clock);
17extern void __init at91sam9g45_initialize(unsigned long main_clock); 17extern void __init at91sam9g45_initialize(unsigned long main_clock);
18extern void __init at91x40_initialize(unsigned long main_clock); 18extern void __init at91x40_initialize(unsigned long main_clock);
19extern void __init at91cap9_initialize(unsigned long main_clock); 19extern void __init at91cap9_initialize(unsigned long main_clock);
20extern void __init at572d940hf_initialize(unsigned long main_clock);
20 21
21 /* Interrupts */ 22 /* Interrupts */
22extern void __init at91rm9200_init_interrupts(unsigned int priority[]); 23extern void __init at91rm9200_init_interrupts(unsigned int priority[]);
@@ -27,6 +28,7 @@ extern void __init at91sam9rl_init_interrupts(unsigned int priority[]);
27extern void __init at91sam9g45_init_interrupts(unsigned int priority[]); 28extern void __init at91sam9g45_init_interrupts(unsigned int priority[]);
28extern void __init at91x40_init_interrupts(unsigned int priority[]); 29extern void __init at91x40_init_interrupts(unsigned int priority[]);
29extern void __init at91cap9_init_interrupts(unsigned int priority[]); 30extern void __init at91cap9_init_interrupts(unsigned int priority[]);
31extern void __init at572d940hf_init_interrupts(unsigned int priority[]);
30extern void __init at91_aic_init(unsigned int priority[]); 32extern void __init at91_aic_init(unsigned int priority[]);
31 33
32 /* Timer */ 34 /* Timer */
diff --git a/arch/arm/mach-at91/include/mach/at572d940hf.h b/arch/arm/mach-at91/include/mach/at572d940hf.h
new file mode 100644
index 000000000000..2d9b0af9c4d5
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at572d940hf.h
@@ -0,0 +1,123 @@
1/*
2 * include/mach/at572d940hf.h
3 *
4 * Antonio R. Costa <costa.antonior@gmail.com>
5 * Copyright (C) 2008 Atmel
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22
23#ifndef AT572D940HF_H
24#define AT572D940HF_H
25
26/*
27 * Peripheral identifiers/interrupts.
28 */
29#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
30#define AT91_ID_SYS 1 /* System Peripherals */
31#define AT572D940HF_ID_PIOA 2 /* Parallel IO Controller A */
32#define AT572D940HF_ID_PIOB 3 /* Parallel IO Controller B */
33#define AT572D940HF_ID_PIOC 4 /* Parallel IO Controller C */
34#define AT572D940HF_ID_EMAC 5 /* MACB ethernet controller */
35#define AT572D940HF_ID_US0 6 /* USART 0 */
36#define AT572D940HF_ID_US1 7 /* USART 1 */
37#define AT572D940HF_ID_US2 8 /* USART 2 */
38#define AT572D940HF_ID_MCI 9 /* Multimedia Card Interface */
39#define AT572D940HF_ID_UDP 10 /* USB Device Port */
40#define AT572D940HF_ID_TWI0 11 /* Two-Wire Interface 0 */
41#define AT572D940HF_ID_SPI0 12 /* Serial Peripheral Interface 0 */
42#define AT572D940HF_ID_SPI1 13 /* Serial Peripheral Interface 1 */
43#define AT572D940HF_ID_SSC0 14 /* Serial Synchronous Controller 0 */
44#define AT572D940HF_ID_SSC1 15 /* Serial Synchronous Controller 1 */
45#define AT572D940HF_ID_SSC2 16 /* Serial Synchronous Controller 2 */
46#define AT572D940HF_ID_TC0 17 /* Timer Counter 0 */
47#define AT572D940HF_ID_TC1 18 /* Timer Counter 1 */
48#define AT572D940HF_ID_TC2 19 /* Timer Counter 2 */
49#define AT572D940HF_ID_UHP 20 /* USB Host port */
50#define AT572D940HF_ID_SSC3 21 /* Serial Synchronous Controller 3 */
51#define AT572D940HF_ID_TWI1 22 /* Two-Wire Interface 1 */
52#define AT572D940HF_ID_CAN0 23 /* CAN Controller 0 */
53#define AT572D940HF_ID_CAN1 24 /* CAN Controller 1 */
54#define AT572D940HF_ID_MHALT 25 /* mAgicV HALT line */
55#define AT572D940HF_ID_MSIRQ0 26 /* mAgicV SIRQ0 line */
56#define AT572D940HF_ID_MEXC 27 /* mAgicV exception line */
57#define AT572D940HF_ID_MEDMA 28 /* mAgicV end of DMA line */
58#define AT572D940HF_ID_IRQ0 29 /* External Interrupt Source (IRQ0) */
59#define AT572D940HF_ID_IRQ1 30 /* External Interrupt Source (IRQ1) */
60#define AT572D940HF_ID_IRQ2 31 /* External Interrupt Source (IRQ2) */
61
62
63/*
64 * User Peripheral physical base addresses.
65 */
66#define AT572D940HF_BASE_TCB 0xfffa0000
67#define AT572D940HF_BASE_TC0 0xfffa0000
68#define AT572D940HF_BASE_TC1 0xfffa0040
69#define AT572D940HF_BASE_TC2 0xfffa0080
70#define AT572D940HF_BASE_UDP 0xfffa4000
71#define AT572D940HF_BASE_MCI 0xfffa8000
72#define AT572D940HF_BASE_TWI0 0xfffac000
73#define AT572D940HF_BASE_US0 0xfffb0000
74#define AT572D940HF_BASE_US1 0xfffb4000
75#define AT572D940HF_BASE_US2 0xfffb8000
76#define AT572D940HF_BASE_SSC0 0xfffbc000
77#define AT572D940HF_BASE_SSC1 0xfffc0000
78#define AT572D940HF_BASE_SSC2 0xfffc4000
79#define AT572D940HF_BASE_SPI0 0xfffc8000
80#define AT572D940HF_BASE_SPI1 0xfffcc000
81#define AT572D940HF_BASE_SSC3 0xfffd0000
82#define AT572D940HF_BASE_TWI1 0xfffd4000
83#define AT572D940HF_BASE_EMAC 0xfffd8000
84#define AT572D940HF_BASE_CAN0 0xfffdc000
85#define AT572D940HF_BASE_CAN1 0xfffe0000
86#define AT91_BASE_SYS 0xffffea00
87
88
89/*
90 * System Peripherals (offset from AT91_BASE_SYS)
91 */
92#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
93#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
94#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
95#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
96#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
97#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
98#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
99#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
100#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
101#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
102#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
103#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
104#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
105
106#define AT91_USART0 AT572D940HF_ID_US0
107#define AT91_USART1 AT572D940HF_ID_US1
108#define AT91_USART2 AT572D940HF_ID_US2
109
110
111/*
112 * Internal Memory.
113 */
114#define AT572D940HF_SRAM_BASE 0x00300000 /* Internal SRAM base address */
115#define AT572D940HF_SRAM_SIZE (48 * SZ_1K) /* Internal SRAM size (48Kb) */
116
117#define AT572D940HF_ROM_BASE 0x00400000 /* Internal ROM base address */
118#define AT572D940HF_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
119
120#define AT572D940HF_UHP_BASE 0x00500000 /* USB Host controller */
121
122
123#endif
diff --git a/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h b/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h
new file mode 100644
index 000000000000..b6751df09488
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h
@@ -0,0 +1,123 @@
1/*
2 * include/mach//at572d940hf_matrix.h
3 *
4 * Antonio R. Costa <costa.antonior@gmail.com>
5 * Copyright (C) 2008 Atmel
6 *
7 * Copyright (C) 2005 SAN People
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#ifndef AT572D940HF_MATRIX_H
25#define AT572D940HF_MATRIX_H
26
27#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
28#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
29#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
30#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
31#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
32#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
33
34#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
35#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
36#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
37#define AT91_MATRIX_ULBT_FOUR (2 << 0)
38#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
39#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
40
41#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
42#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
43#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
44#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
45#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
46#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
47#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
48#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
49#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
50#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
51#define AT91_MATRIX_FIXED_DEFMSTR (0x7 << 18) /* Fixed Index of Default Master */
52#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
53#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
54#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
55
56#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
57#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
58#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
59#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
60#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
61
62#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
63#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
64#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
65#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
66#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
67#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
68#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
69
70#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
71#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
72#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
73
74#define AT91_MATRIX_SFR0 (AT91_MATRIX + 0x110) /* Special Function Register 0 */
75#define AT91_MATRIX_SFR1 (AT91_MATRIX + 0x114) /* Special Function Register 1 */
76#define AT91_MATRIX_SFR2 (AT91_MATRIX + 0x118) /* Special Function Register 2 */
77#define AT91_MATRIX_SFR3 (AT91_MATRIX + 0x11C) /* Special Function Register 3 */
78#define AT91_MATRIX_SFR4 (AT91_MATRIX + 0x120) /* Special Function Register 4 */
79#define AT91_MATRIX_SFR5 (AT91_MATRIX + 0x124) /* Special Function Register 5 */
80#define AT91_MATRIX_SFR6 (AT91_MATRIX + 0x128) /* Special Function Register 6 */
81#define AT91_MATRIX_SFR7 (AT91_MATRIX + 0x12C) /* Special Function Register 7 */
82#define AT91_MATRIX_SFR8 (AT91_MATRIX + 0x130) /* Special Function Register 8 */
83#define AT91_MATRIX_SFR9 (AT91_MATRIX + 0x134) /* Special Function Register 9 */
84#define AT91_MATRIX_SFR10 (AT91_MATRIX + 0x138) /* Special Function Register 10 */
85#define AT91_MATRIX_SFR11 (AT91_MATRIX + 0x13C) /* Special Function Register 11 */
86#define AT91_MATRIX_SFR12 (AT91_MATRIX + 0x140) /* Special Function Register 12 */
87#define AT91_MATRIX_SFR13 (AT91_MATRIX + 0x144) /* Special Function Register 13 */
88#define AT91_MATRIX_SFR14 (AT91_MATRIX + 0x148) /* Special Function Register 14 */
89#define AT91_MATRIX_SFR15 (AT91_MATRIX + 0x14C) /* Special Function Register 15 */
90
91
92/*
93 * The following registers / bits are not defined in the Datasheet (Revision A)
94 */
95
96#define AT91_MATRIX_TCR (AT91_MATRIX + 0x100) /* TCM Configuration Register */
97#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
98#define AT91_MATRIX_ITCM_0 (0 << 0)
99#define AT91_MATRIX_ITCM_16 (5 << 0)
100#define AT91_MATRIX_ITCM_32 (6 << 0)
101#define AT91_MATRIX_ITCM_64 (7 << 0)
102#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
103#define AT91_MATRIX_DTCM_0 (0 << 4)
104#define AT91_MATRIX_DTCM_16 (5 << 4)
105#define AT91_MATRIX_DTCM_32 (6 << 4)
106#define AT91_MATRIX_DTCM_64 (7 << 4)
107
108#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */
109#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
110#define AT91_MATRIX_CS1A_SMC (0 << 1)
111#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
112#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
113#define AT91_MATRIX_CS3A_SMC (0 << 3)
114#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
115#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
116#define AT91_MATRIX_CS4A_SMC (0 << 4)
117#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
118#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
119#define AT91_MATRIX_CS5A_SMC (0 << 5)
120#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
121#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
122
123#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 64589eaaaee8..e46f93e34aab 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -32,6 +32,7 @@
32#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ 32#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
33#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ 33#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
34#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ 34#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
35#define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */
35#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ 36#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
36#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ 37#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
37 38
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index bb6f6a7ba5e0..ceaec6c16eb2 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -87,7 +87,7 @@ struct at91_eth_data {
87extern void __init at91_add_device_eth(struct at91_eth_data *data); 87extern void __init at91_add_device_eth(struct at91_eth_data *data);
88 88
89#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) \ 89#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) \
90 || defined(CONFIG_ARCH_AT91SAM9G45) 90 || defined(CONFIG_ARCH_AT91SAM9G45) || defined(CONFIG_ARCH_AT572D940HF)
91#define eth_platform_data at91_eth_data 91#define eth_platform_data at91_eth_data
92#endif 92#endif
93 93
@@ -205,6 +205,9 @@ extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
205extern void __init at91_gpio_leds(struct gpio_led *leds, int nr); 205extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
206extern void __init at91_pwm_leds(struct gpio_led *leds, int nr); 206extern void __init at91_pwm_leds(struct gpio_led *leds, int nr);
207 207
208 /* AT572D940HF DSP */
209extern void __init at91_add_device_mAgic(void);
210
208/* FIXME: this needs a better location, but gets stuff building again */ 211/* FIXME: this needs a better location, but gets stuff building again */
209extern int at91_suspend_entering_slow_clock(void); 212extern int at91_suspend_entering_slow_clock(void);
210 213
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index c22df30ed5e5..5a0650101d45 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -33,6 +33,8 @@
33#define ARCH_ID_AT91SAM9XE256 0x329a93a0 33#define ARCH_ID_AT91SAM9XE256 0x329a93a0
34#define ARCH_ID_AT91SAM9XE512 0x329aa3a0 34#define ARCH_ID_AT91SAM9XE512 0x329aa3a0
35 35
36#define ARCH_ID_AT572D940HF 0x0e0303e0
37
36#define ARCH_ID_AT91M40800 0x14080044 38#define ARCH_ID_AT91M40800 0x14080044
37#define ARCH_ID_AT91R40807 0x44080746 39#define ARCH_ID_AT91R40807 0x44080746
38#define ARCH_ID_AT91M40807 0x14080745 40#define ARCH_ID_AT91M40807 0x14080745
@@ -141,6 +143,12 @@ static inline unsigned long at91cap9_rev_identify(void)
141#define cpu_is_at91cap9_revC() (0) 143#define cpu_is_at91cap9_revC() (0)
142#endif 144#endif
143 145
146#ifdef CONFIG_ARCH_AT572D940HF
147#define cpu_is_at572d940hf() (at91_cpu_identify() == ARCH_ID_AT572D940HF)
148#else
149#define cpu_is_at572d940hf() (0)
150#endif
151
144/* 152/*
145 * Since this is ARM, we will never run on any AVR32 CPU. But these 153 * Since this is ARM, we will never run on any AVR32 CPU. But these
146 * definitions may reduce clutter in common drivers. 154 * definitions may reduce clutter in common drivers.
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index a0df8b022df2..3d64a75e3ed5 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -32,6 +32,8 @@
32#include <mach/at91cap9.h> 32#include <mach/at91cap9.h>
33#elif defined(CONFIG_ARCH_AT91X40) 33#elif defined(CONFIG_ARCH_AT91X40)
34#include <mach/at91x40.h> 34#include <mach/at91x40.h>
35#elif defined(CONFIG_ARCH_AT572D940HF)
36#include <mach/at572d940hf.h>
35#else 37#else
36#error "Unsupported AT91 processor" 38#error "Unsupported AT91 processor"
37#endif 39#endif
diff --git a/arch/arm/mach-at91/include/mach/timex.h b/arch/arm/mach-at91/include/mach/timex.h
index 31ac2d97f14c..05a6e8af80c4 100644
--- a/arch/arm/mach-at91/include/mach/timex.h
+++ b/arch/arm/mach-at91/include/mach/timex.h
@@ -82,6 +82,11 @@
82#define AT91X40_MASTER_CLOCK 40000000 82#define AT91X40_MASTER_CLOCK 40000000
83#define CLOCK_TICK_RATE (AT91X40_MASTER_CLOCK) 83#define CLOCK_TICK_RATE (AT91X40_MASTER_CLOCK)
84 84
85#elif defined(CONFIG_ARCH_AT572D940HF)
86
87#define AT572D940HF_MASTER_CLOCK 80000000
88#define CLOCK_TICK_RATE (AT572D940HF_MASTER_CLOCK/16)
89
85#endif 90#endif
86 91
87#endif 92#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 11:38:13 -0500