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authorLudovic Desroches <ludovic.desroches@atmel.com>2012-06-22 05:41:34 -0400
committerNicolas Ferre <nicolas.ferre@atmel.com>2012-07-02 08:26:58 -0400
commit3a6b37134c71be1b085be7fe5234f364dc68e2de (patch)
tree4ced8b4a0c27ce5824e7393e9d0c264554834f6b /arch/arm/mach-at91
parentf8a073ee378b9893aee0749c3868a6ecfb0c1636 (diff)
ARM: at91: remove static irq priorities for sam9x5
Since irq priorites are managed in DT, static ones are no more required for sam9x5 which only has DT support. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/mach-at91')
-rw-r--r--arch/arm/mach-at91/at91sam9x5.c38
1 files changed, 0 insertions, 38 deletions
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 537710b68982..477cf9d06672 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -319,47 +319,9 @@ void __init at91sam9x5_initialize(void)
319/* -------------------------------------------------------------------- 319/* --------------------------------------------------------------------
320 * Interrupt initialization 320 * Interrupt initialization
321 * -------------------------------------------------------------------- */ 321 * -------------------------------------------------------------------- */
322/*
323 * The default interrupt priority levels (0 = lowest, 7 = highest).
324 */
325static unsigned int at91sam9x5_default_irq_priority[NR_AIC_IRQS] __initdata = {
326 7, /* Advanced Interrupt Controller (FIQ) */
327 7, /* System Peripherals */
328 1, /* Parallel IO Controller A and B */
329 1, /* Parallel IO Controller C and D */
330 4, /* Soft Modem */
331 5, /* USART 0 */
332 5, /* USART 1 */
333 5, /* USART 2 */
334 5, /* USART 3 */
335 6, /* Two-Wire Interface 0 */
336 6, /* Two-Wire Interface 1 */
337 6, /* Two-Wire Interface 2 */
338 0, /* Multimedia Card Interface 0 */
339 5, /* Serial Peripheral Interface 0 */
340 5, /* Serial Peripheral Interface 1 */
341 5, /* UART 0 */
342 5, /* UART 1 */
343 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
344 0, /* Pulse Width Modulation Controller */
345 0, /* ADC Controller */
346 0, /* DMA Controller 0 */
347 0, /* DMA Controller 1 */
348 2, /* USB Host High Speed port */
349 2, /* USB Device High speed port */
350 3, /* Ethernet MAC 0 */
351 3, /* LDC Controller or Image Sensor Interface */
352 0, /* Multimedia Card Interface 1 */
353 3, /* Ethernet MAC 1 */
354 4, /* Synchronous Serial Interface */
355 4, /* CAN Controller 0 */
356 4, /* CAN Controller 1 */
357 0, /* Advanced Interrupt Controller (IRQ0) */
358};
359 322
360struct at91_init_soc __initdata at91sam9x5_soc = { 323struct at91_init_soc __initdata at91sam9x5_soc = {
361 .map_io = at91sam9x5_map_io, 324 .map_io = at91sam9x5_map_io,
362 .default_irq_priority = at91sam9x5_default_irq_priority,
363 .register_clocks = at91sam9x5_register_clocks, 325 .register_clocks = at91sam9x5_register_clocks,
364 .init = at91sam9x5_initialize, 326 .init = at91sam9x5_initialize,
365}; 327};