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authorNicolas Ferre <nicolas.ferre@atmel.com>2009-06-26 10:36:56 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-06-27 06:05:21 -0400
commitfddcc0ae58edefeb7ac1e460411d7dfbe8ebdacc (patch)
tree337b517d1caaae1f3239998c431efdb23ee1b1eb /arch/arm/mach-at91/include
parent2ef9df7ada6b6dd53446a994ef6e3a6ad5a300ef (diff)
[ARM] 5571/1: at91: Basic support for at91sam9g45 series: header files.
AT91sam9g45 series is an ARM 926ej-s SOC family clocked at 400/133MHz. It embedds USB high speed host and device, LCD, DDR2 RAM, and a full set of peripherals. Here is the basic header file support for this product series. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-at91/include')
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9g45.h138
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h153
-rw-r--r--arch/arm/mach-at91/include/mach/cpu.h16
-rw-r--r--arch/arm/mach-at91/include/mach/hardware.h2
-rw-r--r--arch/arm/mach-at91/include/mach/timex.h5
5 files changed, 314 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
new file mode 100644
index 000000000000..2c42cf5f0c54
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -0,0 +1,138 @@
1/*
2 * Chip-specific header file for the AT91SAM9G45 family
3 *
4 * Copyright (C) 2008-2009 Atmel Corporation.
5 *
6 * Common definitions.
7 * Based on AT91SAM9G45 preliminary datasheet.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91SAM9G45_H
16#define AT91SAM9G45_H
17
18/*
19 * Peripheral identifiers/interrupts.
20 */
21#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
22#define AT91_ID_SYS 1 /* System Controller Interrupt */
23#define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */
24#define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */
25#define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */
26#define AT91SAM9G45_ID_PIODE 5 /* Parallel I/O Controller D and E */
27#define AT91SAM9G45_ID_TRNG 6 /* True Random Number Generator */
28#define AT91SAM9G45_ID_US0 7 /* USART 0 */
29#define AT91SAM9G45_ID_US1 8 /* USART 1 */
30#define AT91SAM9G45_ID_US2 9 /* USART 2 */
31#define AT91SAM9G45_ID_US3 10 /* USART 3 */
32#define AT91SAM9G45_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */
33#define AT91SAM9G45_ID_TWI0 12 /* Two-Wire Interface 0 */
34#define AT91SAM9G45_ID_TWI1 13 /* Two-Wire Interface 1 */
35#define AT91SAM9G45_ID_SPI0 14 /* Serial Peripheral Interface 0 */
36#define AT91SAM9G45_ID_SPI1 15 /* Serial Peripheral Interface 1 */
37#define AT91SAM9G45_ID_SSC0 16 /* Synchronous Serial Controller 0 */
38#define AT91SAM9G45_ID_SSC1 17 /* Synchronous Serial Controller 1 */
39#define AT91SAM9G45_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
40#define AT91SAM9G45_ID_PWMC 19 /* Pulse Width Modulation Controller */
41#define AT91SAM9G45_ID_TSC 20 /* Touch Screen ADC Controller */
42#define AT91SAM9G45_ID_DMA 21 /* DMA Controller */
43#define AT91SAM9G45_ID_UHPHS 22 /* USB Host High Speed */
44#define AT91SAM9G45_ID_LCDC 23 /* LCD Controller */
45#define AT91SAM9G45_ID_AC97C 24 /* AC97 Controller */
46#define AT91SAM9G45_ID_EMAC 25 /* Ethernet MAC */
47#define AT91SAM9G45_ID_ISI 26 /* Image Sensor Interface */
48#define AT91SAM9G45_ID_UDPHS 27 /* USB Device High Speed */
49#define AT91SAM9G45_ID_AESTDESSHA 28 /* AES + T-DES + SHA */
50#define AT91SAM9G45_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */
51#define AT91SAM9G45_ID_VDEC 30 /* Video Decoder */
52#define AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */
53
54/*
55 * User Peripheral physical base addresses.
56 */
57#define AT91SAM9G45_BASE_UDPHS 0xfff78000
58#define AT91SAM9G45_BASE_TCB0 0xfff7c000
59#define AT91SAM9G45_BASE_TC0 0xfff7c000
60#define AT91SAM9G45_BASE_TC1 0xfff7c040
61#define AT91SAM9G45_BASE_TC2 0xfff7c080
62#define AT91SAM9G45_BASE_MCI0 0xfff80000
63#define AT91SAM9G45_BASE_TWI0 0xfff84000
64#define AT91SAM9G45_BASE_TWI1 0xfff88000
65#define AT91SAM9G45_BASE_US0 0xfff8c000
66#define AT91SAM9G45_BASE_US1 0xfff90000
67#define AT91SAM9G45_BASE_US2 0xfff94000
68#define AT91SAM9G45_BASE_US3 0xfff98000
69#define AT91SAM9G45_BASE_SSC0 0xfff9c000
70#define AT91SAM9G45_BASE_SSC1 0xfffa0000
71#define AT91SAM9G45_BASE_SPI0 0xfffa4000
72#define AT91SAM9G45_BASE_SPI1 0xfffa8000
73#define AT91SAM9G45_BASE_AC97C 0xfffac000
74#define AT91SAM9G45_BASE_TSC 0xfffb0000
75#define AT91SAM9G45_BASE_ISI 0xfffb4000
76#define AT91SAM9G45_BASE_PWMC 0xfffb8000
77#define AT91SAM9G45_BASE_EMAC 0xfffbc000
78#define AT91SAM9G45_BASE_AES 0xfffc0000
79#define AT91SAM9G45_BASE_TDES 0xfffc4000
80#define AT91SAM9G45_BASE_SHA 0xfffc8000
81#define AT91SAM9G45_BASE_TRNG 0xfffcc000
82#define AT91SAM9G45_BASE_MCI1 0xfffd0000
83#define AT91SAM9G45_BASE_TCB1 0xfffd4000
84#define AT91SAM9G45_BASE_TC3 0xfffd4000
85#define AT91SAM9G45_BASE_TC4 0xfffd4040
86#define AT91SAM9G45_BASE_TC5 0xfffd4080
87#define AT91_BASE_SYS 0xffffe200
88
89/*
90 * System Peripherals (offset from AT91_BASE_SYS)
91 */
92#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
93#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS)
94#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
95#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
96#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
97#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
98#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
99#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
100#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
101#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
102#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
103#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
104#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS)
105#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
106#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
107#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
108#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
109#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
110#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
111#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
112#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS)
113
114#define AT91_USART0 AT91SAM9G45_BASE_US0
115#define AT91_USART1 AT91SAM9G45_BASE_US1
116#define AT91_USART2 AT91SAM9G45_BASE_US2
117#define AT91_USART3 AT91SAM9G45_BASE_US3
118
119/*
120 * Internal Memory.
121 */
122#define AT91SAM9G45_SRAM_BASE 0x00300000 /* Internal SRAM base address */
123#define AT91SAM9G45_SRAM_SIZE SZ_64K /* Internal SRAM size (64Kb) */
124
125#define AT91SAM9G45_ROM_BASE 0x00400000 /* Internal ROM base address */
126#define AT91SAM9G45_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */
127
128#define AT91SAM9G45_LCDC_BASE 0x00500000 /* LCD Controller */
129#define AT91SAM9G45_UDPHS_FIFO 0x00600000 /* USB Device HS controller */
130#define AT91SAM9G45_OHCI_BASE 0x00700000 /* USB Host controller (OHCI) */
131#define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */
132#define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */
133
134#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6
135
136#define CONSISTENT_DMA_SIZE SZ_4M
137
138#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
new file mode 100644
index 000000000000..c972d60e0aeb
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
@@ -0,0 +1,153 @@
1/*
2 * Matrix-centric header file for the AT91SAM9G45 family
3 *
4 * Copyright (C) 2008-2009 Atmel Corporation.
5 *
6 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
7 * Based on AT91SAM9G45 preliminary datasheet.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91SAM9G45_MATRIX_H
16#define AT91SAM9G45_MATRIX_H
17
18#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
19#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
20#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
21#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
22#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
23#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
24#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
25#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
26#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
27#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */
28#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */
29#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */
30#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
31#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
32#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
33#define AT91_MATRIX_ULBT_FOUR (2 << 0)
34#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
35#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
36#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
37#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
38#define AT91_MATRIX_ULBT_128 (7 << 0)
39
40#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
41#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
42#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
43#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
44#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
45#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
46#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
47#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
48#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
49#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
50#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
51#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
52#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
53#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
54
55#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
56#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
57#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
58#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
59#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
60#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
61#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
62#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
63#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
64#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
65#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
66#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
67#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
68#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
69#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
70#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
71#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
72#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
73#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
74#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
75#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
76#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
77#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
78#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
79#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
80#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
81#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
82#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
83
84#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
85#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
86#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
87#define AT91_MATRIX_RCB2 (1 << 2)
88#define AT91_MATRIX_RCB3 (1 << 3)
89#define AT91_MATRIX_RCB4 (1 << 4)
90#define AT91_MATRIX_RCB5 (1 << 5)
91#define AT91_MATRIX_RCB6 (1 << 6)
92#define AT91_MATRIX_RCB7 (1 << 7)
93#define AT91_MATRIX_RCB8 (1 << 8)
94#define AT91_MATRIX_RCB9 (1 << 9)
95#define AT91_MATRIX_RCB10 (1 << 10)
96#define AT91_MATRIX_RCB11 (1 << 11)
97
98#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x110) /* TCM Configuration Register */
99#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
100#define AT91_MATRIX_ITCM_0 (0 << 0)
101#define AT91_MATRIX_ITCM_32 (6 << 0)
102#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
103#define AT91_MATRIX_DTCM_0 (0 << 4)
104#define AT91_MATRIX_DTCM_32 (6 << 4)
105#define AT91_MATRIX_DTCM_64 (7 << 4)
106#define AT91_MATRIX_TCM_NWS (0x1 << 11) /* Wait state TCM register */
107#define AT91_MATRIX_TCM_NO_WS (0x0 << 11)
108#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11)
109
110#define AT91_MATRIX_VIDEO (AT91_MATRIX + 0x118) /* Video Mode Configuration Register */
111#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */
112#define AT91C_VDEC_SEL_OFF (0 << 0)
113#define AT91C_VDEC_SEL_ON (1 << 0)
114
115#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x128) /* EBI Chip Select Assignment Register */
116#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
117#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
118#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
119#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
120#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
121#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
122#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
123#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
124#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4)
125#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
126#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
127#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5)
128#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
129#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
130#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
131#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
132#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
133#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
134#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
135#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
136#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
137#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
138#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
139#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
140
141#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
142#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
143#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
144#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
145#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
146
147#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
148#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
149#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
150#define AT91_MATRIX_WPSR_WPV (1 << 0)
151#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
152
153#endif
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index c554c3e4d553..b73e7bf097da 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -23,6 +23,7 @@
23#define ARCH_ID_AT91SAM9263 0x019607a0 23#define ARCH_ID_AT91SAM9263 0x019607a0
24#define ARCH_ID_AT91SAM9G20 0x019905a0 24#define ARCH_ID_AT91SAM9G20 0x019905a0
25#define ARCH_ID_AT91SAM9RL64 0x019b03a0 25#define ARCH_ID_AT91SAM9RL64 0x019b03a0
26#define ARCH_ID_AT91SAM9G45 0x819b05a0
26#define ARCH_ID_AT91CAP9 0x039A03A0 27#define ARCH_ID_AT91CAP9 0x039A03A0
27 28
28#define ARCH_ID_AT91SAM9XE128 0x329973a0 29#define ARCH_ID_AT91SAM9XE128 0x329973a0
@@ -39,6 +40,15 @@ static inline unsigned long at91_cpu_identify(void)
39 return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); 40 return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION);
40} 41}
41 42
43#define ARCH_EXID_AT91SAM9M11 0x00000001
44#define ARCH_EXID_AT91SAM9M10 0x00000002
45#define ARCH_EXID_AT91SAM9G45 0x00000004
46
47static inline unsigned long at91_exid_identify(void)
48{
49 return at91_sys_read(AT91_DBGU_EXID);
50}
51
42 52
43#define ARCH_FAMILY_AT91X92 0x09200000 53#define ARCH_FAMILY_AT91X92 0x09200000
44#define ARCH_FAMILY_AT91SAM9 0x01900000 54#define ARCH_FAMILY_AT91SAM9 0x01900000
@@ -99,6 +109,12 @@ static inline unsigned long at91cap9_rev_identify(void)
99#define cpu_is_at91sam9rl() (0) 109#define cpu_is_at91sam9rl() (0)
100#endif 110#endif
101 111
112#ifdef CONFIG_ARCH_AT91SAM9G45
113#define cpu_is_at91sam9g45() (at91_cpu_identify() == ARCH_ID_AT91SAM9G45)
114#else
115#define cpu_is_at91sam9g45() (0)
116#endif
117
102#ifdef CONFIG_ARCH_AT91CAP9 118#ifdef CONFIG_ARCH_AT91CAP9
103#define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9) 119#define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9)
104#define cpu_is_at91cap9_revB() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_B) 120#define cpu_is_at91cap9_revB() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_B)
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index da0b681c652c..f0869170fa00 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -26,6 +26,8 @@
26#include <mach/at91sam9263.h> 26#include <mach/at91sam9263.h>
27#elif defined(CONFIG_ARCH_AT91SAM9RL) 27#elif defined(CONFIG_ARCH_AT91SAM9RL)
28#include <mach/at91sam9rl.h> 28#include <mach/at91sam9rl.h>
29#elif defined(CONFIG_ARCH_AT91SAM9G45)
30#include <mach/at91sam9g45.h>
29#elif defined(CONFIG_ARCH_AT91CAP9) 31#elif defined(CONFIG_ARCH_AT91CAP9)
30#include <mach/at91cap9.h> 32#include <mach/at91cap9.h>
31#elif defined(CONFIG_ARCH_AT91X40) 33#elif defined(CONFIG_ARCH_AT91X40)
diff --git a/arch/arm/mach-at91/include/mach/timex.h b/arch/arm/mach-at91/include/mach/timex.h
index d84c9948becf..38f6c4250c76 100644
--- a/arch/arm/mach-at91/include/mach/timex.h
+++ b/arch/arm/mach-at91/include/mach/timex.h
@@ -62,6 +62,11 @@
62#define AT91SAM9_MASTER_CLOCK 132096000 62#define AT91SAM9_MASTER_CLOCK 132096000
63#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) 63#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
64 64
65#elif defined(CONFIG_ARCH_AT91SAM9G45)
66
67#define AT91SAM9_MASTER_CLOCK 133333333
68#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
69
65#elif defined(CONFIG_ARCH_AT91CAP9) 70#elif defined(CONFIG_ARCH_AT91CAP9)
66 71
67#define AT91CAP9_MASTER_CLOCK 100000000 72#define AT91CAP9_MASTER_CLOCK 100000000
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 13:30:37 -0400