diff options
author | Josh Wu <josh.wu@atmel.com> | 2013-08-27 07:28:00 -0400 |
---|---|---|
committer | Jonathan Cameron <jic23@kernel.org> | 2013-08-29 16:45:04 -0400 |
commit | e1811f97ba985fef3f703f55aeb5d23660c919ef (patch) | |
tree | 4cf474f2e516d1d60bf9fb1de89f4b60735d3364 /arch/arm/mach-at91/include | |
parent | 2d2da9fc7113ee5df06519e435f2f9430acf40c5 (diff) |
iio: at91: introduce the multiple compatible string for different IPs.
As use the multiple compatible string, we can remove hardware register in dt.
CC: devicetree@vger.kernel.org
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Diffstat (limited to 'arch/arm/mach-at91/include')
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91_adc.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91_adc.h b/arch/arm/mach-at91/include/mach/at91_adc.h index 8e7ed5c90817..bea1a2021d1e 100644 --- a/arch/arm/mach-at91/include/mach/at91_adc.h +++ b/arch/arm/mach-at91/include/mach/at91_adc.h | |||
@@ -48,6 +48,9 @@ | |||
48 | #define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */ | 48 | #define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */ |
49 | #define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */ | 49 | #define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */ |
50 | 50 | ||
51 | #define AT91_ADC_SR_9X5 0x30 /* Status Register for 9x5 */ | ||
52 | #define AT91_ADC_SR_DRDY_9X5 (1 << 24) /* Data Ready */ | ||
53 | |||
51 | #define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */ | 54 | #define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */ |
52 | #define AT91_ADC_LDATA (0x3ff) | 55 | #define AT91_ADC_LDATA (0x3ff) |
53 | 56 | ||
@@ -58,4 +61,10 @@ | |||
58 | #define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */ | 61 | #define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */ |
59 | #define AT91_ADC_DATA (0x3ff) | 62 | #define AT91_ADC_DATA (0x3ff) |
60 | 63 | ||
64 | #define AT91_ADC_CDR0_9X5 (0x50) /* Channel Data Register 0 for 9X5 */ | ||
65 | |||
66 | #define AT91_ADC_TRGR_9260 AT91_ADC_MR | ||
67 | #define AT91_ADC_TRGR_9G45 0x08 | ||
68 | #define AT91_ADC_TRGR_9X5 0xC0 | ||
69 | |||
61 | #endif | 70 | #endif |