diff options
author | Nicolas Ferre <nicolas.ferre@atmel.com> | 2014-10-21 08:16:54 -0400 |
---|---|---|
committer | Nicolas Ferre <nicolas.ferre@atmel.com> | 2014-11-03 12:48:00 -0500 |
commit | 7538ec7d1e5990f719538aeec9c021ba694040d9 (patch) | |
tree | 08113291c67ffa840181229877ef43a88305bb70 /arch/arm/mach-at91/include | |
parent | cac7f2429872d3733dc3f9915857b1691da2eb2f (diff) |
ARM: at91: remove no-MMU at91x40 support
As there is currently no-one to take care of this old !MMU target and as its
support in recent kernels is a bit rotten, remove this at91x40 support and the
board file associated with it (at91eb01).
There are modern ARM !MMU in Mainline now so this target is not interesting for
building tests anymore. It would be better to start from these modern ARM !MMU
platforms to reintroduce at91x40 support if needed.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Greg Ungerer <gerg@uclinux.org>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-at91/include')
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91_dbgu.h | 3 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91x40.h | 60 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/cpu.h | 1 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/hardware.h | 5 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/uncompress.h | 7 |
5 files changed, 0 insertions, 76 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h index 3b5948566e52..42925e8f78e4 100644 --- a/arch/arm/mach-at91/include/mach/at91_dbgu.h +++ b/arch/arm/mach-at91/include/mach/at91_dbgu.h | |||
@@ -16,7 +16,6 @@ | |||
16 | #ifndef AT91_DBGU_H | 16 | #ifndef AT91_DBGU_H |
17 | #define AT91_DBGU_H | 17 | #define AT91_DBGU_H |
18 | 18 | ||
19 | #if !defined(CONFIG_ARCH_AT91X40) | ||
20 | #define AT91_DBGU_CR (0x00) /* Control Register */ | 19 | #define AT91_DBGU_CR (0x00) /* Control Register */ |
21 | #define AT91_DBGU_MR (0x04) /* Mode Register */ | 20 | #define AT91_DBGU_MR (0x04) /* Mode Register */ |
22 | #define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */ | 21 | #define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */ |
@@ -34,8 +33,6 @@ | |||
34 | #define AT91_DBGU_FNR (0x48) /* Force NTRST Register [SAM9 only] */ | 33 | #define AT91_DBGU_FNR (0x48) /* Force NTRST Register [SAM9 only] */ |
35 | #define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ | 34 | #define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ |
36 | 35 | ||
37 | #endif /* AT91_DBGU */ | ||
38 | |||
39 | /* | 36 | /* |
40 | * Some AT91 parts that don't have full DEBUG units still support the ID | 37 | * Some AT91 parts that don't have full DEBUG units still support the ID |
41 | * and extensions register. | 38 | * and extensions register. |
diff --git a/arch/arm/mach-at91/include/mach/at91x40.h b/arch/arm/mach-at91/include/mach/at91x40.h deleted file mode 100644 index 38dca2bb027f..000000000000 --- a/arch/arm/mach-at91/include/mach/at91x40.h +++ /dev/null | |||
@@ -1,60 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-at91/include/mach/at91x40.h | ||
3 | * | ||
4 | * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | */ | ||
11 | |||
12 | #ifndef AT91X40_H | ||
13 | #define AT91X40_H | ||
14 | |||
15 | /* | ||
16 | * IRQ list. | ||
17 | */ | ||
18 | #define AT91X40_ID_USART0 2 /* USART port 0 */ | ||
19 | #define AT91X40_ID_USART1 3 /* USART port 1 */ | ||
20 | #define AT91X40_ID_TC0 4 /* Timer/Counter 0 */ | ||
21 | #define AT91X40_ID_TC1 5 /* Timer/Counter 1*/ | ||
22 | #define AT91X40_ID_TC2 6 /* Timer/Counter 2*/ | ||
23 | #define AT91X40_ID_WD 7 /* Watchdog? */ | ||
24 | #define AT91X40_ID_PIOA 8 /* Parallel IO Controller A */ | ||
25 | |||
26 | #define AT91X40_ID_IRQ0 16 /* External IRQ 0 */ | ||
27 | #define AT91X40_ID_IRQ1 17 /* External IRQ 1 */ | ||
28 | #define AT91X40_ID_IRQ2 18 /* External IRQ 2 */ | ||
29 | |||
30 | /* | ||
31 | * System Peripherals | ||
32 | */ | ||
33 | #define AT91_BASE_SYS 0xffc00000 | ||
34 | |||
35 | #define AT91_EBI 0xffe00000 /* External Bus Interface */ | ||
36 | #define AT91_SF 0xfff00000 /* Special Function */ | ||
37 | #define AT91_USART1 0xfffcc000 /* USART 1 */ | ||
38 | #define AT91_USART0 0xfffd0000 /* USART 0 */ | ||
39 | #define AT91_TC 0xfffe0000 /* Timer Counter */ | ||
40 | #define AT91_PIOA 0xffff0000 /* PIO Controller A */ | ||
41 | #define AT91_PS 0xffff4000 /* Power Save */ | ||
42 | #define AT91_WD 0xffff8000 /* Watchdog Timer */ | ||
43 | |||
44 | /* | ||
45 | * The AT91x40 series doesn't have a debug unit like the other AT91 parts. | ||
46 | * But it does have a chip identify register and extension ID, so define at | ||
47 | * least these here. | ||
48 | */ | ||
49 | #define AT91_DBGU_CIDR (AT91_SF + 0) /* CIDR in PS segment */ | ||
50 | #define AT91_DBGU_EXID (AT91_SF + 4) /* EXID in PS segment */ | ||
51 | |||
52 | /* | ||
53 | * Support defines for the simple Power Controller module. | ||
54 | */ | ||
55 | #define AT91_PS_CR (AT91_PS + 0) /* PS Control register */ | ||
56 | #define AT91_PS_CR_CPU (1 << 0) /* CPU clock disable bit */ | ||
57 | |||
58 | #define AT91X40_MASTER_CLOCK 40000000 | ||
59 | |||
60 | #endif /* AT91X40_H */ | ||
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h index b27e9ca65653..61914fb35f5d 100644 --- a/arch/arm/mach-at91/include/mach/cpu.h +++ b/arch/arm/mach-at91/include/mach/cpu.h | |||
@@ -62,7 +62,6 @@ | |||
62 | #define ARCH_EXID_SAMA5D43 0x00000003 | 62 | #define ARCH_EXID_SAMA5D43 0x00000003 |
63 | #define ARCH_EXID_SAMA5D44 0x00000004 | 63 | #define ARCH_EXID_SAMA5D44 0x00000004 |
64 | 64 | ||
65 | #define ARCH_FAMILY_AT91X92 0x09200000 | ||
66 | #define ARCH_FAMILY_AT91SAM9 0x01900000 | 65 | #define ARCH_FAMILY_AT91SAM9 0x01900000 |
67 | #define ARCH_FAMILY_AT91SAM9XE 0x02900000 | 66 | #define ARCH_FAMILY_AT91SAM9XE 0x02900000 |
68 | 67 | ||
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index c13797352688..a57c1c52a574 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h | |||
@@ -24,9 +24,6 @@ | |||
24 | /* sama5d4 */ | 24 | /* sama5d4 */ |
25 | #define AT91_BASE_DBGU2 0xfc069000 | 25 | #define AT91_BASE_DBGU2 0xfc069000 |
26 | 26 | ||
27 | #if defined(CONFIG_ARCH_AT91X40) | ||
28 | #include <mach/at91x40.h> | ||
29 | #else | ||
30 | #include <mach/at91rm9200.h> | 27 | #include <mach/at91rm9200.h> |
31 | #include <mach/at91sam9260.h> | 28 | #include <mach/at91sam9260.h> |
32 | #include <mach/at91sam9261.h> | 29 | #include <mach/at91sam9261.h> |
@@ -51,8 +48,6 @@ | |||
51 | */ | 48 | */ |
52 | #define AT91_BASE_SYS 0xffffc000 | 49 | #define AT91_BASE_SYS 0xffffc000 |
53 | 50 | ||
54 | #endif | ||
55 | |||
56 | /* | 51 | /* |
57 | * On sama5d4 there is no system controller, we map some needed peripherals | 52 | * On sama5d4 there is no system controller, we map some needed peripherals |
58 | */ | 53 | */ |
diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h index acb2d890ad7e..4ebb609369e3 100644 --- a/arch/arm/mach-at91/include/mach/uncompress.h +++ b/arch/arm/mach-at91/include/mach/uncompress.h | |||
@@ -31,7 +31,6 @@ | |||
31 | 31 | ||
32 | void __iomem *at91_uart; | 32 | void __iomem *at91_uart; |
33 | 33 | ||
34 | #if !defined(CONFIG_ARCH_AT91X40) | ||
35 | static const u32 uarts_rm9200[] = { | 34 | static const u32 uarts_rm9200[] = { |
36 | AT91_BASE_DBGU0, | 35 | AT91_BASE_DBGU0, |
37 | AT91RM9200_BASE_US0, | 36 | AT91RM9200_BASE_US0, |
@@ -188,12 +187,6 @@ static inline void arch_decomp_setup(void) | |||
188 | 187 | ||
189 | at91_uart = NULL; | 188 | at91_uart = NULL; |
190 | } | 189 | } |
191 | #else | ||
192 | static inline void arch_decomp_setup(void) | ||
193 | { | ||
194 | at91_uart = NULL; | ||
195 | } | ||
196 | #endif | ||
197 | 190 | ||
198 | /* | 191 | /* |
199 | * The following code assumes the serial port has already been | 192 | * The following code assumes the serial port has already been |