ARM: KVM: introduce per-vcpu HYP Configuration Register

So far, KVM/ARM used a fixed HCR configuration per guest, except for
the VI/VF/VA bits to control the interrupt in absence of VGIC.

With the upcoming need to dynamically reconfigure trapping, it becomes
necessary to allow the HCR to be changed on a per-vcpu basis.

The fix here is to mimic what KVM/arm64 already does: a per vcpu HCR
field, initialized at setup time.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>

1 files changed, 3 insertions, 6 deletions

diff --git a/arch/arm/kvm/interrupts_head.S b/arch/arm/kvm/interrupts_head.S
index 6f18695a09cb..a37270d7d4d6 100644
--- a/arch/arm/kvm/interrupts_head.S
+++ b/arch/arm/kvm/interrupts_head.S
@@ -597,17 +597,14 @@ vcpu	.req	r0		@ vcpu pointer always in r0
 
 /* Enable/Disable: stage-2 trans., trap interrupts, trap wfi, trap smc */
 .macro configure_hyp_role operation
-        mrc     p15, 4, r2, c1, c1, 0   @ HCR
-        bic     r2, r2, #HCR_VIRT_EXCP_MASK
-        ldr     r3, =HCR_GUEST_MASK
         .if \operation == vmentry
-        orr     r2, r2, r3
+        ldr     r2, [vcpu, #VCPU_HCR]
         ldr     r3, [vcpu, #VCPU_IRQ_LINES]
         orr     r2, r2, r3
         .else
-        bic     r2, r2, r3
+        mov     r2, #0
         .endif
-        mcr     p15, 4, r2, c1, c1, 0
+        mcr     p15, 4, r2, c1, c1, 0   @ HCR
 .endm
 
 .macro load_vcpu