ARM: LPAE: MMU setup for the 3-level page table format

This patch adds the MMU initialisation for the LPAE page table format.
The swapper_pg_dir size with LPAE is 5 rather than 4 pages. A new
proc-v7-3level.S file contains the TTB initialisation, context switch
and PTE setting code with the LPAE. The TTBRx split is based on the
PAGE_OFFSET with TTBR1 used for the kernel mappings. The 36-bit mappings
(supersections) and a few other memory types in mmu.c are conditionally
compiled.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

1 files changed, 43 insertions, 2 deletions

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 54eb94aff6cd..c8e797baaf55 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -39,8 +39,14 @@
 #error KERNEL_RAM_VADDR must start at 0xXXXX8000
 #endif
 
+#ifdef CONFIG_ARM_LPAE
+        /* LPAE requires an additional page for the PGD */
+#define PG_DIR_SIZE     0x5000
+#define PMD_ORDER       3
+#else
 #define PG_DIR_SIZE     0x4000
 #define PMD_ORDER       2
+#endif
 
         .globl  swapper_pg_dir
         .equ    swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
@@ -164,6 +170,25 @@ __create_page_tables:
         teq     r0, r6
         bne     1b
 
+#ifdef CONFIG_ARM_LPAE
+        /*
+         * Build the PGD table (first level) to point to the PMD table. A PGD
+         * entry is 64-bit wide.
+         */
+        mov     r0, r4
+        add     r3, r4, #0x1000                 @ first PMD table address
+        orr     r3, r3, #3                      @ PGD block type
+        mov     r6, #4                          @ PTRS_PER_PGD
+        mov     r7, #1 << (55 - 32)             @ L_PGD_SWAPPER
+1:      str     r3, [r0], #4                    @ set bottom PGD entry bits
+        str     r7, [r0], #4                    @ set top PGD entry bits
+        add     r3, r3, #0x1000                 @ next PMD table
+        subs    r6, r6, #1
+        bne     1b
+
+        add     r4, r4, #0x1000                 @ point to the PMD tables
+#endif
+
         ldr     r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
 
         /*
@@ -219,8 +244,8 @@ __create_page_tables:
 #endif
 
         /*
-         * Then map boot params address in r2 or
-         * the first 1MB of ram if boot params address is not specified.
+         * Then map boot params address in r2 or the first 1MB (2MB with LPAE)
+         * of ram if boot params address is not specified.
          */
         mov     r0, r2, lsr #SECTION_SHIFT
         movs    r0, r0, lsl #SECTION_SHIFT
@@ -251,7 +276,15 @@ __create_page_tables:
         mov     r3, r7, lsr #SECTION_SHIFT
         ldr     r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
         orr     r3, r7, r3, lsl #SECTION_SHIFT
+#ifdef CONFIG_ARM_LPAE
+        mov     r7, #1 << (54 - 32)             @ XN
+#else
+        orr     r3, r3, #PMD_SECT_XN
+#endif
 1:      str     r3, [r0], #4
+#ifdef CONFIG_ARM_LPAE
+        str     r7, [r0], #4
+#endif
         add     r3, r3, #1 << SECTION_SHIFT
         cmp     r0, r6
         blo     1b
@@ -283,6 +316,9 @@ __create_page_tables:
         str     r3, [r0]
 #endif
 #endif
+#ifdef CONFIG_ARM_LPAE
+        sub     r4, r4, #0x1000         @ point to the PGD table
+#endif
         mov     pc, lr
 ENDPROC(__create_page_tables)
         .ltorg
@@ -374,12 +410,17 @@ __enable_mmu:
 #ifdef CONFIG_CPU_ICACHE_DISABLE
         bic     r0, r0, #CR_I
 #endif
+#ifdef CONFIG_ARM_LPAE
+        mov     r5, #0
+        mcrr    p15, 0, r4, r5, c2              @ load TTBR0
+#else
         mov     r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
                       domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
                       domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
                       domain_val(DOMAIN_IO, DOMAIN_CLIENT))
         mcr     p15, 0, r5, c3, c0, 0           @ load domain access register
         mcr     p15, 0, r4, c2, c0, 0           @ load page table pointer
+#endif
         b       __turn_mmu_on
 ENDPROC(__enable_mmu)