diff options
author | Russell King <rmk+kernel@arm.linux.org.uk> | 2014-07-12 08:59:24 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2014-07-12 08:59:24 -0400 |
commit | cda390bb8f0fc751194ef5f4c691ca8d3ff91009 (patch) | |
tree | 9739758690c5107b73a09f632ae2f8fc2507db09 /arch/arm/kernel/probes-arm.c | |
parent | 9a2c33a422d60e8e55c5aff6752522dc39993b16 (diff) | |
parent | 449fd15fbcde239875031d70fd06abb4a0e1ed09 (diff) |
Merge branch 'kprobes-test-fixes' of git://git.linaro.org/people/tixy/kernel into fixes
Diffstat (limited to 'arch/arm/kernel/probes-arm.c')
-rw-r--r-- | arch/arm/kernel/probes-arm.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/kernel/probes-arm.c b/arch/arm/kernel/probes-arm.c index 51a13a027989..8eaef81d8344 100644 --- a/arch/arm/kernel/probes-arm.c +++ b/arch/arm/kernel/probes-arm.c | |||
@@ -341,12 +341,12 @@ static const union decode_item arm_cccc_000x_table[] = { | |||
341 | /* CMP (reg-shift reg) cccc 0001 0101 xxxx xxxx xxxx 0xx1 xxxx */ | 341 | /* CMP (reg-shift reg) cccc 0001 0101 xxxx xxxx xxxx 0xx1 xxxx */ |
342 | /* CMN (reg-shift reg) cccc 0001 0111 xxxx xxxx xxxx 0xx1 xxxx */ | 342 | /* CMN (reg-shift reg) cccc 0001 0111 xxxx xxxx xxxx 0xx1 xxxx */ |
343 | DECODE_EMULATEX (0x0f900090, 0x01100010, PROBES_DATA_PROCESSING_REG, | 343 | DECODE_EMULATEX (0x0f900090, 0x01100010, PROBES_DATA_PROCESSING_REG, |
344 | REGS(ANY, 0, NOPC, 0, ANY)), | 344 | REGS(NOPC, 0, NOPC, 0, NOPC)), |
345 | 345 | ||
346 | /* MOV (reg-shift reg) cccc 0001 101x xxxx xxxx xxxx 0xx1 xxxx */ | 346 | /* MOV (reg-shift reg) cccc 0001 101x xxxx xxxx xxxx 0xx1 xxxx */ |
347 | /* MVN (reg-shift reg) cccc 0001 111x xxxx xxxx xxxx 0xx1 xxxx */ | 347 | /* MVN (reg-shift reg) cccc 0001 111x xxxx xxxx xxxx 0xx1 xxxx */ |
348 | DECODE_EMULATEX (0x0fa00090, 0x01a00010, PROBES_DATA_PROCESSING_REG, | 348 | DECODE_EMULATEX (0x0fa00090, 0x01a00010, PROBES_DATA_PROCESSING_REG, |
349 | REGS(0, ANY, NOPC, 0, ANY)), | 349 | REGS(0, NOPC, NOPC, 0, NOPC)), |
350 | 350 | ||
351 | /* AND (reg-shift reg) cccc 0000 000x xxxx xxxx xxxx 0xx1 xxxx */ | 351 | /* AND (reg-shift reg) cccc 0000 000x xxxx xxxx xxxx 0xx1 xxxx */ |
352 | /* EOR (reg-shift reg) cccc 0000 001x xxxx xxxx xxxx 0xx1 xxxx */ | 352 | /* EOR (reg-shift reg) cccc 0000 001x xxxx xxxx xxxx 0xx1 xxxx */ |
@@ -359,7 +359,7 @@ static const union decode_item arm_cccc_000x_table[] = { | |||
359 | /* ORR (reg-shift reg) cccc 0001 100x xxxx xxxx xxxx 0xx1 xxxx */ | 359 | /* ORR (reg-shift reg) cccc 0001 100x xxxx xxxx xxxx 0xx1 xxxx */ |
360 | /* BIC (reg-shift reg) cccc 0001 110x xxxx xxxx xxxx 0xx1 xxxx */ | 360 | /* BIC (reg-shift reg) cccc 0001 110x xxxx xxxx xxxx 0xx1 xxxx */ |
361 | DECODE_EMULATEX (0x0e000090, 0x00000010, PROBES_DATA_PROCESSING_REG, | 361 | DECODE_EMULATEX (0x0e000090, 0x00000010, PROBES_DATA_PROCESSING_REG, |
362 | REGS(ANY, ANY, NOPC, 0, ANY)), | 362 | REGS(NOPC, NOPC, NOPC, 0, NOPC)), |
363 | 363 | ||
364 | DECODE_END | 364 | DECODE_END |
365 | }; | 365 | }; |