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authorSudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com>2012-07-31 05:11:23 -0400
committerWill Deacon <will.deacon@arm.com>2012-11-09 06:37:25 -0500
commit513c99ce4e64245be1f83f56039ec4891b451955 (patch)
tree5f322c568433b855fede78276e9dd7ce06188025 /arch/arm/kernel/perf_event_v7.c
parente50c54189f7c6211a99539156e3978474f0b1a0b (diff)
ARM: perf: allocate CPU PMU dynamically at probe time
Supporting multiple, heterogeneous CPU PMUs requires us to allocate the arm_pmu structures dynamically as the devices are probed. This patch removes the static structure definitions for each CPU PMU type and instead passes pointers to the PMU-specific init functions. Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm/kernel/perf_event_v7.c')
-rw-r--r--arch/arm/kernel/perf_event_v7.c106
1 files changed, 55 insertions, 51 deletions
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index bd4b090ebcfd..b189403f30e4 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -18,8 +18,6 @@
18 18
19#ifdef CONFIG_CPU_V7 19#ifdef CONFIG_CPU_V7
20 20
21static struct arm_pmu armv7pmu;
22
23/* 21/*
24 * Common ARMv7 event types 22 * Common ARMv7 event types
25 * 23 *
@@ -1014,7 +1012,7 @@ static void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
1014 * We only need to set the event for the cycle counter if we 1012 * We only need to set the event for the cycle counter if we
1015 * have the ability to perform event filtering. 1013 * have the ability to perform event filtering.
1016 */ 1014 */
1017 if (armv7pmu.set_event_filter || idx != ARMV7_IDX_CYCLE_COUNTER) 1015 if (cpu_pmu->set_event_filter || idx != ARMV7_IDX_CYCLE_COUNTER)
1018 armv7_pmnc_write_evtsel(idx, hwc->config_base); 1016 armv7_pmnc_write_evtsel(idx, hwc->config_base);
1019 1017
1020 /* 1018 /*
@@ -1232,17 +1230,18 @@ static int armv7_a7_map_event(struct perf_event *event)
1232 &armv7_a7_perf_cache_map, 0xFF); 1230 &armv7_a7_perf_cache_map, 0xFF);
1233} 1231}
1234 1232
1235static struct arm_pmu armv7pmu = { 1233static void armv7pmu_init(struct arm_pmu *cpu_pmu)
1236 .handle_irq = armv7pmu_handle_irq, 1234{
1237 .enable = armv7pmu_enable_event, 1235 cpu_pmu->handle_irq = armv7pmu_handle_irq;
1238 .disable = armv7pmu_disable_event, 1236 cpu_pmu->enable = armv7pmu_enable_event;
1239 .read_counter = armv7pmu_read_counter, 1237 cpu_pmu->disable = armv7pmu_disable_event;
1240 .write_counter = armv7pmu_write_counter, 1238 cpu_pmu->read_counter = armv7pmu_read_counter;
1241 .get_event_idx = armv7pmu_get_event_idx, 1239 cpu_pmu->write_counter = armv7pmu_write_counter;
1242 .start = armv7pmu_start, 1240 cpu_pmu->get_event_idx = armv7pmu_get_event_idx;
1243 .stop = armv7pmu_stop, 1241 cpu_pmu->start = armv7pmu_start;
1244 .reset = armv7pmu_reset, 1242 cpu_pmu->stop = armv7pmu_stop;
1245 .max_period = (1LLU << 32) - 1, 1243 cpu_pmu->reset = armv7pmu_reset;
1244 cpu_pmu->max_period = (1LLU << 32) - 1;
1246}; 1245};
1247 1246
1248static u32 __devinit armv7_read_num_pmnc_events(void) 1247static u32 __devinit armv7_read_num_pmnc_events(void)
@@ -1256,70 +1255,75 @@ static u32 __devinit armv7_read_num_pmnc_events(void)
1256 return nb_cnt + 1; 1255 return nb_cnt + 1;
1257} 1256}
1258 1257
1259static struct arm_pmu *__devinit armv7_a8_pmu_init(void) 1258static int __devinit armv7_a8_pmu_init(struct arm_pmu *cpu_pmu)
1260{ 1259{
1261 armv7pmu.name = "ARMv7 Cortex-A8"; 1260 armv7pmu_init(cpu_pmu);
1262 armv7pmu.map_event = armv7_a8_map_event; 1261 cpu_pmu->name = "ARMv7 Cortex-A8";
1263 armv7pmu.num_events = armv7_read_num_pmnc_events(); 1262 cpu_pmu->map_event = armv7_a8_map_event;
1264 return &armv7pmu; 1263 cpu_pmu->num_events = armv7_read_num_pmnc_events();
1264 return 0;
1265} 1265}
1266 1266
1267static struct arm_pmu *__devinit armv7_a9_pmu_init(void) 1267static int __devinit armv7_a9_pmu_init(struct arm_pmu *cpu_pmu)
1268{ 1268{
1269 armv7pmu.name = "ARMv7 Cortex-A9"; 1269 armv7pmu_init(cpu_pmu);
1270 armv7pmu.map_event = armv7_a9_map_event; 1270 cpu_pmu->name = "ARMv7 Cortex-A9";
1271 armv7pmu.num_events = armv7_read_num_pmnc_events(); 1271 cpu_pmu->map_event = armv7_a9_map_event;
1272 return &armv7pmu; 1272 cpu_pmu->num_events = armv7_read_num_pmnc_events();
1273 return 0;
1273} 1274}
1274 1275
1275static struct arm_pmu *__devinit armv7_a5_pmu_init(void) 1276static int __devinit armv7_a5_pmu_init(struct arm_pmu *cpu_pmu)
1276{ 1277{
1277 armv7pmu.name = "ARMv7 Cortex-A5"; 1278 armv7pmu_init(cpu_pmu);
1278 armv7pmu.map_event = armv7_a5_map_event; 1279 cpu_pmu->name = "ARMv7 Cortex-A5";
1279 armv7pmu.num_events = armv7_read_num_pmnc_events(); 1280 cpu_pmu->map_event = armv7_a5_map_event;
1280 return &armv7pmu; 1281 cpu_pmu->num_events = armv7_read_num_pmnc_events();
1282 return 0;
1281} 1283}
1282 1284
1283static struct arm_pmu *__devinit armv7_a15_pmu_init(void) 1285static int __devinit armv7_a15_pmu_init(struct arm_pmu *cpu_pmu)
1284{ 1286{
1285 armv7pmu.name = "ARMv7 Cortex-A15"; 1287 armv7pmu_init(cpu_pmu);
1286 armv7pmu.map_event = armv7_a15_map_event; 1288 cpu_pmu->name = "ARMv7 Cortex-A15";
1287 armv7pmu.num_events = armv7_read_num_pmnc_events(); 1289 cpu_pmu->map_event = armv7_a15_map_event;
1288 armv7pmu.set_event_filter = armv7pmu_set_event_filter; 1290 cpu_pmu->num_events = armv7_read_num_pmnc_events();
1289 return &armv7pmu; 1291 cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
1292 return 0;
1290} 1293}
1291 1294
1292static struct arm_pmu *__devinit armv7_a7_pmu_init(void) 1295static int __devinit armv7_a7_pmu_init(struct arm_pmu *cpu_pmu)
1293{ 1296{
1294 armv7pmu.name = "ARMv7 Cortex-A7"; 1297 armv7pmu_init(cpu_pmu);
1295 armv7pmu.map_event = armv7_a7_map_event; 1298 cpu_pmu->name = "ARMv7 Cortex-A7";
1296 armv7pmu.num_events = armv7_read_num_pmnc_events(); 1299 cpu_pmu->map_event = armv7_a7_map_event;
1297 armv7pmu.set_event_filter = armv7pmu_set_event_filter; 1300 cpu_pmu->num_events = armv7_read_num_pmnc_events();
1298 return &armv7pmu; 1301 cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
1302 return 0;
1299} 1303}
1300#else 1304#else
1301static struct arm_pmu *__devinit armv7_a8_pmu_init(void) 1305static inline int armv7_a8_pmu_init(struct arm_pmu *cpu_pmu)
1302{ 1306{
1303 return NULL; 1307 return -ENODEV;
1304} 1308}
1305 1309
1306static struct arm_pmu *__devinit armv7_a9_pmu_init(void) 1310static inline int armv7_a9_pmu_init(struct arm_pmu *cpu_pmu)
1307{ 1311{
1308 return NULL; 1312 return -ENODEV;
1309} 1313}
1310 1314
1311static struct arm_pmu *__devinit armv7_a5_pmu_init(void) 1315static inline int armv7_a5_pmu_init(struct arm_pmu *cpu_pmu)
1312{ 1316{
1313 return NULL; 1317 return -ENODEV;
1314} 1318}
1315 1319
1316static struct arm_pmu *__devinit armv7_a15_pmu_init(void) 1320static inline int armv7_a15_pmu_init(struct arm_pmu *cpu_pmu)
1317{ 1321{
1318 return NULL; 1322 return -ENODEV;
1319} 1323}
1320 1324
1321static struct arm_pmu *__devinit armv7_a7_pmu_init(void) 1325static inline int armv7_a7_pmu_init(struct arm_pmu *cpu_pmu)
1322{ 1326{
1323 return NULL; 1327 return -ENODEV;
1324} 1328}
1325#endif /* CONFIG_CPU_V7 */ 1329#endif /* CONFIG_CPU_V7 */