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authorLinus Torvalds <torvalds@linux-foundation.org>2014-09-30 22:52:08 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-09-30 22:52:08 -0400
commitaad7fb916a10f1065ad23de0c80a4a04bcba8437 (patch)
tree9e091817ac2fff165c945be2d1c28b11aec344cd /arch/arm/include
parentfe82dcec644244676d55a1384c958d5f67979adb (diff)
parentad684dce87fac52738649e62b4afa25081b52a28 (diff)
Merge branch 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm
Pull ARM fixes from Russell King: "Some further ARM fixes: - another build fix for the kprobes test code - a fix for no kuser helpers for the set_tls code, which oopsed on noMMU hardware - a fix for alignment handler with neon opcodes being misinterpreted - turning off the hardware access support, which is not implemented - a build fix for the v7 coherency exiting code, which can be built in non-v7 environments (but still only executed on v7 CPUs)" * 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: ARM: 8179/1: kprobes-test: Fix compile error "bad immediate value for offset" ARM: 8178/1: fix set_tls for !CONFIG_KUSER_HELPERS ARM: 8177/1: cacheflush: Fix v7_exit_coherency_flush exynos build breakage on ARMv6 ARM: 8165/1: alignment: don't break misaligned NEON load/store ARM: 8164/1: mm: clear SCTLR.HA instead of setting it for LPAE
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/cacheflush.h1
-rw-r--r--arch/arm/include/asm/tls.h2
2 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 79ecb4f34ffb..10e78d00a0bb 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -466,6 +466,7 @@ static inline void __sync_cache_range_r(volatile void *p, size_t size)
466 */ 466 */
467#define v7_exit_coherency_flush(level) \ 467#define v7_exit_coherency_flush(level) \
468 asm volatile( \ 468 asm volatile( \
469 ".arch armv7-a \n\t" \
469 "stmfd sp!, {fp, ip} \n\t" \ 470 "stmfd sp!, {fp, ip} \n\t" \
470 "mrc p15, 0, r0, c1, c0, 0 @ get SCTLR \n\t" \ 471 "mrc p15, 0, r0, c1, c0, 0 @ get SCTLR \n\t" \
471 "bic r0, r0, #"__stringify(CR_C)" \n\t" \ 472 "bic r0, r0, #"__stringify(CR_C)" \n\t" \
diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
index 36172adda9d0..5f833f7adba1 100644
--- a/arch/arm/include/asm/tls.h
+++ b/arch/arm/include/asm/tls.h
@@ -81,6 +81,7 @@ static inline void set_tls(unsigned long val)
81 asm("mcr p15, 0, %0, c13, c0, 3" 81 asm("mcr p15, 0, %0, c13, c0, 3"
82 : : "r" (val)); 82 : : "r" (val));
83 } else { 83 } else {
84#ifdef CONFIG_KUSER_HELPERS
84 /* 85 /*
85 * User space must never try to access this 86 * User space must never try to access this
86 * directly. Expect your app to break 87 * directly. Expect your app to break
@@ -89,6 +90,7 @@ static inline void set_tls(unsigned long val)
89 * entry-armv.S for details) 90 * entry-armv.S for details)
90 */ 91 */
91 *((unsigned int *)0xffff0ff0) = val; 92 *((unsigned int *)0xffff0ff0) = val;
93#endif
92 } 94 }
93 95
94 } 96 }