diff options
author | Cyril Chemparathy <cyril@ti.com> | 2012-07-21 15:55:04 -0400 |
---|---|---|
committer | Will Deacon <will.deacon@arm.com> | 2013-05-30 11:02:15 -0400 |
commit | 4756dcbfd37819a8359d3c69a22be2ee41666d0f (patch) | |
tree | a9c172f6940e607b9c0c9a3bd7393bf0cc03e940 /arch/arm/include | |
parent | a7fbc0d62a4d46e642af889e7288fede5078bc46 (diff) |
ARM: LPAE: accomodate >32-bit addresses for page table base
This patch redefines the early boot time use of the R4 register to steal a few
low order bits (ARCH_PGD_SHIFT bits) on LPAE systems. This allows for up to
38-bit physical addresses.
Signed-off-by: Cyril Chemparathy <cyril@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Subash Patel <subash.rp@samsung.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm/include')
-rw-r--r-- | arch/arm/include/asm/memory.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 57870ab313c5..e506088a7678 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h | |||
@@ -18,6 +18,8 @@ | |||
18 | #include <linux/types.h> | 18 | #include <linux/types.h> |
19 | #include <linux/sizes.h> | 19 | #include <linux/sizes.h> |
20 | 20 | ||
21 | #include <asm/cache.h> | ||
22 | |||
21 | #ifdef CONFIG_NEED_MACH_MEMORY_H | 23 | #ifdef CONFIG_NEED_MACH_MEMORY_H |
22 | #include <mach/memory.h> | 24 | #include <mach/memory.h> |
23 | #endif | 25 | #endif |
@@ -141,6 +143,20 @@ | |||
141 | #define page_to_phys(page) (__pfn_to_phys(page_to_pfn(page))) | 143 | #define page_to_phys(page) (__pfn_to_phys(page_to_pfn(page))) |
142 | #define phys_to_page(phys) (pfn_to_page(__phys_to_pfn(phys))) | 144 | #define phys_to_page(phys) (pfn_to_page(__phys_to_pfn(phys))) |
143 | 145 | ||
146 | /* | ||
147 | * Minimum guaranted alignment in pgd_alloc(). The page table pointers passed | ||
148 | * around in head.S and proc-*.S are shifted by this amount, in order to | ||
149 | * leave spare high bits for systems with physical address extension. This | ||
150 | * does not fully accomodate the 40-bit addressing capability of ARM LPAE, but | ||
151 | * gives us about 38-bits or so. | ||
152 | */ | ||
153 | #ifdef CONFIG_ARM_LPAE | ||
154 | #define ARCH_PGD_SHIFT L1_CACHE_SHIFT | ||
155 | #else | ||
156 | #define ARCH_PGD_SHIFT 0 | ||
157 | #endif | ||
158 | #define ARCH_PGD_MASK ((1 << ARCH_PGD_SHIFT) - 1) | ||
159 | |||
144 | #ifndef __ASSEMBLY__ | 160 | #ifndef __ASSEMBLY__ |
145 | 161 | ||
146 | /* | 162 | /* |