aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/include
diff options
context:
space:
mode:
authorWill Deacon <will.deacon@arm.com>2012-08-24 10:18:45 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2012-08-25 04:22:32 -0400
commit195bbcac2e5c12f7fb99cdcc492c3000c5537f4a (patch)
tree0ceb437685819d049b60cbf6096ed5be1149b97c /arch/arm/include
parente91d5d916f50ad2cf2394aba89d32833adce4303 (diff)
ARM: 7500/1: io: avoid writeback addressing modes for __raw_ accessors
Data aborts taken to hyp mode do not provide a valid instruction syndrome field in the HSR if the faulting instruction is a memory access using a writeback addressing mode. For hypervisors emulating MMIO accesses to virtual peripherals, taking such an exception requires disassembling the faulting instruction in order to determine the behaviour of the access. Since this requires manually walking the two stages of translation, the world must be stopped to prevent races against page aging in the guest, where the first-stage translation is invalidated after the hypervisor has translated to an IPA and the physical page is reused for something else. This patch avoids taking this heavy performance penalty when running Linux as a guest by ensuring that our I/O accessors do not make use of writeback addressing modes. Cc: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/io.h67
1 files changed, 61 insertions, 6 deletions
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 815c669fec0a..09c4628efbe7 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -47,13 +47,68 @@ extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
47extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen); 47extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
48extern void __raw_readsl(const void __iomem *addr, void *data, int longlen); 48extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
49 49
50#define __raw_writeb(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigned char __force *)(a) = (v))) 50#if __LINUX_ARM_ARCH__ < 6
51#define __raw_writew(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v))) 51/*
52#define __raw_writel(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigned int __force *)(a) = (v))) 52 * Half-word accesses are problematic with RiscPC due to limitations of
53 * the bus. Rather than special-case the machine, just let the compiler
54 * generate the access for CPUs prior to ARMv6.
55 */
56#define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
57#define __raw_writew(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)))
58#else
59/*
60 * When running under a hypervisor, we want to avoid I/O accesses with
61 * writeback addressing modes as these incur a significant performance
62 * overhead (the address generation must be emulated in software).
63 */
64static inline void __raw_writew(u16 val, volatile void __iomem *addr)
65{
66 asm volatile("strh %1, %0"
67 : "+Qo" (*(volatile u16 __force *)addr)
68 : "r" (val));
69}
70
71static inline u16 __raw_readw(const volatile void __iomem *addr)
72{
73 u16 val;
74 asm volatile("ldrh %1, %0"
75 : "+Qo" (*(volatile u16 __force *)addr),
76 "=r" (val));
77 return val;
78}
79#endif
53 80
54#define __raw_readb(a) (__chk_io_ptr(a), *(volatile unsigned char __force *)(a)) 81static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
55#define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a)) 82{
56#define __raw_readl(a) (__chk_io_ptr(a), *(volatile unsigned int __force *)(a)) 83 asm volatile("strb %1, %0"
84 : "+Qo" (*(volatile u8 __force *)addr)
85 : "r" (val));
86}
87
88static inline void __raw_writel(u32 val, volatile void __iomem *addr)
89{
90 asm volatile("str %1, %0"
91 : "+Qo" (*(volatile u32 __force *)addr)
92 : "r" (val));
93}
94
95static inline u8 __raw_readb(const volatile void __iomem *addr)
96{
97 u8 val;
98 asm volatile("ldrb %1, %0"
99 : "+Qo" (*(volatile u8 __force *)addr),
100 "=r" (val));
101 return val;
102}
103
104static inline u32 __raw_readl(const volatile void __iomem *addr)
105{
106 u32 val;
107 asm volatile("ldr %1, %0"
108 : "+Qo" (*(volatile u32 __force *)addr),
109 "=r" (val));
110 return val;
111}
57 112
58/* 113/*
59 * Architecture ioremap implementation. 114 * Architecture ioremap implementation.