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author | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-12-05 05:35:33 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-12-05 05:35:33 -0500 |
commit | 0719dc341389882cc834ed18fc9b7fc6006b2b85 (patch) | |
tree | 794480ac62c07ea8cc4e69c2cb3d2b83bb7f36b7 /arch/arm/include | |
parent | e28edb723e64200554194da17617ee6e82de6690 (diff) | |
parent | 677f4f64e4b2336682f0e15c69b206ade6f6b131 (diff) |
Merge branch 'devel-stable' into devel
Diffstat (limited to 'arch/arm/include')
-rw-r--r-- | arch/arm/include/asm/hardware/cache-tauros2.h | 11 | ||||
-rw-r--r-- | arch/arm/include/asm/hardware/iop3xx.h | 18 |
2 files changed, 28 insertions, 1 deletions
diff --git a/arch/arm/include/asm/hardware/cache-tauros2.h b/arch/arm/include/asm/hardware/cache-tauros2.h new file mode 100644 index 000000000000..538f17ca905b --- /dev/null +++ b/arch/arm/include/asm/hardware/cache-tauros2.h | |||
@@ -0,0 +1,11 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/hardware/cache-tauros2.h | ||
3 | * | ||
4 | * Copyright (C) 2008 Marvell Semiconductor | ||
5 | * | ||
6 | * This file is licensed under the terms of the GNU General Public | ||
7 | * License version 2. This program is licensed "as is" without any | ||
8 | * warranty of any kind, whether express or implied. | ||
9 | */ | ||
10 | |||
11 | extern void __init tauros2_init(void); | ||
diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h index 8d60ad267e3a..5daea2961d48 100644 --- a/arch/arm/include/asm/hardware/iop3xx.h +++ b/arch/arm/include/asm/hardware/iop3xx.h | |||
@@ -234,7 +234,13 @@ extern int iop3xx_get_init_atu(void); | |||
234 | void iop3xx_map_io(void); | 234 | void iop3xx_map_io(void); |
235 | void iop_init_cp6_handler(void); | 235 | void iop_init_cp6_handler(void); |
236 | void iop_init_time(unsigned long tickrate); | 236 | void iop_init_time(unsigned long tickrate); |
237 | unsigned long iop_gettimeoffset(void); | 237 | |
238 | static inline u32 read_tmr0(void) | ||
239 | { | ||
240 | u32 val; | ||
241 | asm volatile("mrc p6, 0, %0, c0, c1, 0" : "=r" (val)); | ||
242 | return val; | ||
243 | } | ||
238 | 244 | ||
239 | static inline void write_tmr0(u32 val) | 245 | static inline void write_tmr0(u32 val) |
240 | { | 246 | { |
@@ -253,6 +259,11 @@ static inline u32 read_tcr0(void) | |||
253 | return val; | 259 | return val; |
254 | } | 260 | } |
255 | 261 | ||
262 | static inline void write_tcr0(u32 val) | ||
263 | { | ||
264 | asm volatile("mcr p6, 0, %0, c2, c1, 0" : : "r" (val)); | ||
265 | } | ||
266 | |||
256 | static inline u32 read_tcr1(void) | 267 | static inline u32 read_tcr1(void) |
257 | { | 268 | { |
258 | u32 val; | 269 | u32 val; |
@@ -260,6 +271,11 @@ static inline u32 read_tcr1(void) | |||
260 | return val; | 271 | return val; |
261 | } | 272 | } |
262 | 273 | ||
274 | static inline void write_tcr1(u32 val) | ||
275 | { | ||
276 | asm volatile("mcr p6, 0, %0, c3, c1, 0" : : "r" (val)); | ||
277 | } | ||
278 | |||
263 | static inline void write_trr0(u32 val) | 279 | static inline void write_trr0(u32 val) |
264 | { | 280 | { |
265 | asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val)); | 281 | asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val)); |