From a91549a8f27e63e0e537fe1c20d4845581de894f Mon Sep 17 00:00:00 2001 From: Mikael Pettersson Date: Thu, 29 Oct 2009 11:46:54 -0700 Subject: iop: clocksource support This updates the IOP platform to expose the free-running timer 1 as a clocksource object. This timer is now also properly initialised, which requires a new write_tcr1() function from the mach-specific code. Apart from the explicit initialisation, there is no functional change in how timer 1 is programmed. Tested on n2100, compile-tested for all plat-iop machines. Signed-off-by: Mikael Pettersson Signed-off-by: Dan Williams --- arch/arm/include/asm/hardware/iop3xx.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h index 8d60ad267e3a..643b7b95b25b 100644 --- a/arch/arm/include/asm/hardware/iop3xx.h +++ b/arch/arm/include/asm/hardware/iop3xx.h @@ -260,6 +260,11 @@ static inline u32 read_tcr1(void) return val; } +static inline void write_tcr1(u32 val) +{ + asm volatile("mcr p6, 0, %0, c3, c1, 0" : : "r" (val)); +} + static inline void write_trr0(u32 val) { asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val)); -- cgit v1.2.2 From 469d30448dad13600cdd246024f9db8e80614c45 Mon Sep 17 00:00:00 2001 From: Mikael Pettersson Date: Thu, 29 Oct 2009 11:46:54 -0700 Subject: iop: clockevent support This updates the IOP platform to expose the interrupting timer 0 as a clockevent object. The timer interrupt handler is changed to call the clockevent ->event_handler() instead of timer_tick(), and ->set_next_event() and ->set_mode() operations are added to allow the mode of the timer to be updated (required for ONESHOT/NOHZ mode). Timer 0 must now be properly initialised, which requires a new write_tcr0() function from the mach-specific code. The mode of timer 0 must be read at the start of ->set_mode(), which requires a new read_tmr0() function from the mach- specific code. Initial setup of timer 0 is also rewritten to be more robust. Tested on n2100, compile-tested for all plat-iop machines. Signed-off-by: Mikael Pettersson Signed-off-by: Dan Williams --- arch/arm/include/asm/hardware/iop3xx.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h index 643b7b95b25b..34601b952045 100644 --- a/arch/arm/include/asm/hardware/iop3xx.h +++ b/arch/arm/include/asm/hardware/iop3xx.h @@ -236,6 +236,13 @@ void iop_init_cp6_handler(void); void iop_init_time(unsigned long tickrate); unsigned long iop_gettimeoffset(void); +static inline u32 read_tmr0(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c0, c1, 0" : "=r" (val)); + return val; +} + static inline void write_tmr0(u32 val) { asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (val)); @@ -253,6 +260,11 @@ static inline u32 read_tcr0(void) return val; } +static inline void write_tcr0(u32 val) +{ + asm volatile("mcr p6, 0, %0, c2, c1, 0" : : "r" (val)); +} + static inline u32 read_tcr1(void) { u32 val; -- cgit v1.2.2 From 980f2296b5a8dfe589f023fd34229dcfdcf280fa Mon Sep 17 00:00:00 2001 From: Mikael Pettersson Date: Thu, 29 Oct 2009 11:46:55 -0700 Subject: iop: enable generic time This updates the IOP platform to use the kernel's generic time framework. With clockevent support in place, this reduces to selecting GENERIC_TIME and removing the platform's private timer ->offset() operation (iop_gettimeoffset). Tested on n2100, compile-tested for all plat-iop machines. Signed-off-by: Mikael Pettersson Signed-off-by: Dan Williams --- arch/arm/include/asm/hardware/iop3xx.h | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h index 34601b952045..5daea2961d48 100644 --- a/arch/arm/include/asm/hardware/iop3xx.h +++ b/arch/arm/include/asm/hardware/iop3xx.h @@ -234,7 +234,6 @@ extern int iop3xx_get_init_atu(void); void iop3xx_map_io(void); void iop_init_cp6_handler(void); void iop_init_time(unsigned long tickrate); -unsigned long iop_gettimeoffset(void); static inline u32 read_tmr0(void) { -- cgit v1.2.2 From 573a652fb0da50a1ff3fca2c67afd81138fd06d2 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Tue, 24 Nov 2009 19:33:52 +0200 Subject: ARM: Add Tauros2 L2 cache controller support Support for the Tauros2 L2 cache controller as used with the PJ1 and PJ4 CPUs. Signed-off-by: Lennert Buytenhek Signed-off-by: Saeed Bishara Signed-off-by: Nicolas Pitre --- arch/arm/include/asm/hardware/cache-tauros2.h | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 arch/arm/include/asm/hardware/cache-tauros2.h (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/hardware/cache-tauros2.h b/arch/arm/include/asm/hardware/cache-tauros2.h new file mode 100644 index 000000000000..538f17ca905b --- /dev/null +++ b/arch/arm/include/asm/hardware/cache-tauros2.h @@ -0,0 +1,11 @@ +/* + * arch/arm/include/asm/hardware/cache-tauros2.h + * + * Copyright (C) 2008 Marvell Semiconductor + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +extern void __init tauros2_init(void); -- cgit v1.2.2