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authorLinus Torvalds <torvalds@linux-foundation.org>2013-02-21 18:27:22 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2013-02-21 18:27:22 -0500
commitbab588fcfb6335c767d811a8955979f5440328e0 (patch)
tree2a862ddf47a82be885a8e7945a17cc3ff7a658b9 /arch/arm/include/debug
parent3298a3511f1e73255a8dc023efd909e569eea037 (diff)
parent9cb0d1babfcb1b4ac248c09425f7d5de1e771133 (diff)
Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC-specific updates from Arnd Bergmann: "This is a larger set of new functionality for the existing SoC families, including: - vt8500 gains support for new CPU cores, notably the Cortex-A9 based wm8850 - prima2 gains support for the "marco" SoC family, its SMP based cousin - tegra gains support for the new Tegra4 (Tegra114) family - socfpga now supports a newer version of the hardware including SMP - i.mx31 and bcm2835 are now using DT probing for their clocks - lots of updates for sh-mobile - OMAP updates for clocks, power management and USB - i.mx6q and tegra now support cpuidle - kirkwood now supports PCIe hot plugging - tegra clock support is updated - tegra USB PHY probing gets implemented diffently" * tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (148 commits) ARM: prima2: remove duplicate v7_invalidate_l1 ARM: shmobile: r8a7779: Correct TMU clock support again ARM: prima2: fix __init section for cpu hotplug ARM: OMAP: Consolidate OMAP USB-HS platform data (part 3/3) ARM: OMAP: Consolidate OMAP USB-HS platform data (part 1/3) arm: socfpga: Add SMP support for actual socfpga harware arm: Add v7_invalidate_l1 to cache-v7.S arm: socfpga: Add entries to enable make dtbs socfpga arm: socfpga: Add new device tree source for actual socfpga HW ARM: tegra: sort Kconfig selects for Tegra114 ARM: tegra: enable ARCH_REQUIRE_GPIOLIB for Tegra114 ARM: tegra: Fix build error w/ ARCH_TEGRA_114_SOC w/o ARCH_TEGRA_3x_SOC ARM: tegra: Fix build error for gic update ARM: tegra: remove empty tegra_smp_init_cpus() ARM: shmobile: Register ARM architected timer ARM: MARCO: fix the build issue due to gic-vic-to-irqchip move ARM: shmobile: r8a7779: Correct TMU clock support ARM: mxs_defconfig: Select CONFIG_DEVTMPFS_MOUNT ARM: mxs: decrease mxs_clockevent_device.min_delta_ns to 2 clock cycles ARM: mxs: use apbx bus clock to drive the timers on timrotv2 ...
Diffstat (limited to 'arch/arm/include/debug')
-rw-r--r--arch/arm/include/debug/imx-uart.h88
-rw-r--r--arch/arm/include/debug/imx.S29
2 files changed, 89 insertions, 28 deletions
diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h
new file mode 100644
index 000000000000..91d38e38a0b4
--- /dev/null
+++ b/arch/arm/include/debug/imx-uart.h
@@ -0,0 +1,88 @@
1/*
2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __DEBUG_IMX_UART_H
10#define __DEBUG_IMX_UART_H
11
12#define IMX1_UART1_BASE_ADDR 0x00206000
13#define IMX1_UART2_BASE_ADDR 0x00207000
14#define IMX1_UART_BASE_ADDR(n) IMX1_UART##n##_BASE_ADDR
15#define IMX1_UART_BASE(n) IMX1_UART_BASE_ADDR(n)
16
17#define IMX21_UART1_BASE_ADDR 0x1000a000
18#define IMX21_UART2_BASE_ADDR 0x1000b000
19#define IMX21_UART3_BASE_ADDR 0x1000c000
20#define IMX21_UART4_BASE_ADDR 0x1000d000
21#define IMX21_UART_BASE_ADDR(n) IMX21_UART##n##_BASE_ADDR
22#define IMX21_UART_BASE(n) IMX21_UART_BASE_ADDR(n)
23
24#define IMX25_UART1_BASE_ADDR 0x43f90000
25#define IMX25_UART2_BASE_ADDR 0x43f94000
26#define IMX25_UART3_BASE_ADDR 0x5000c000
27#define IMX25_UART4_BASE_ADDR 0x50008000
28#define IMX25_UART5_BASE_ADDR 0x5002c000
29#define IMX25_UART_BASE_ADDR(n) IMX25_UART##n##_BASE_ADDR
30#define IMX25_UART_BASE(n) IMX25_UART_BASE_ADDR(n)
31
32#define IMX31_UART1_BASE_ADDR 0x43f90000
33#define IMX31_UART2_BASE_ADDR 0x43f94000
34#define IMX31_UART3_BASE_ADDR 0x5000c000
35#define IMX31_UART4_BASE_ADDR 0x43fb0000
36#define IMX31_UART5_BASE_ADDR 0x43fb4000
37#define IMX31_UART_BASE_ADDR(n) IMX31_UART##n##_BASE_ADDR
38#define IMX31_UART_BASE(n) IMX31_UART_BASE_ADDR(n)
39
40#define IMX35_UART1_BASE_ADDR 0x43f90000
41#define IMX35_UART2_BASE_ADDR 0x43f94000
42#define IMX35_UART3_BASE_ADDR 0x5000c000
43#define IMX35_UART_BASE_ADDR(n) IMX35_UART##n##_BASE_ADDR
44#define IMX35_UART_BASE(n) IMX35_UART_BASE_ADDR(n)
45
46#define IMX51_UART1_BASE_ADDR 0x73fbc000
47#define IMX51_UART2_BASE_ADDR 0x73fc0000
48#define IMX51_UART3_BASE_ADDR 0x7000c000
49#define IMX51_UART_BASE_ADDR(n) IMX51_UART##n##_BASE_ADDR
50#define IMX51_UART_BASE(n) IMX51_UART_BASE_ADDR(n)
51
52#define IMX53_UART1_BASE_ADDR 0x53fbc000
53#define IMX53_UART2_BASE_ADDR 0x53fc0000
54#define IMX53_UART3_BASE_ADDR 0x5000c000
55#define IMX53_UART4_BASE_ADDR 0x53ff0000
56#define IMX53_UART5_BASE_ADDR 0x63f90000
57#define IMX53_UART_BASE_ADDR(n) IMX53_UART##n##_BASE_ADDR
58#define IMX53_UART_BASE(n) IMX53_UART_BASE_ADDR(n)
59
60#define IMX6Q_UART1_BASE_ADDR 0x02020000
61#define IMX6Q_UART2_BASE_ADDR 0x021e8000
62#define IMX6Q_UART3_BASE_ADDR 0x021ec000
63#define IMX6Q_UART4_BASE_ADDR 0x021f0000
64#define IMX6Q_UART5_BASE_ADDR 0x021f4000
65#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
66#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n)
67
68#define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT)
69
70#ifdef CONFIG_DEBUG_IMX1_UART
71#define UART_PADDR IMX_DEBUG_UART_BASE(IMX1)
72#elif defined(CONFIG_DEBUG_IMX21_IMX27_UART)
73#define UART_PADDR IMX_DEBUG_UART_BASE(IMX21)
74#elif defined(CONFIG_DEBUG_IMX25_UART)
75#define UART_PADDR IMX_DEBUG_UART_BASE(IMX25)
76#elif defined(CONFIG_DEBUG_IMX31_UART)
77#define UART_PADDR IMX_DEBUG_UART_BASE(IMX31)
78#elif defined(CONFIG_DEBUG_IMX35_UART)
79#define UART_PADDR IMX_DEBUG_UART_BASE(IMX35)
80#elif defined(CONFIG_DEBUG_IMX51_UART)
81#define UART_PADDR IMX_DEBUG_UART_BASE(IMX51)
82#elif defined(CONFIG_DEBUG_IMX53_UART)
83#define UART_PADDR IMX_DEBUG_UART_BASE(IMX53)
84#elif defined(CONFIG_DEBUG_IMX6Q_UART)
85#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q)
86#endif
87
88#endif /* __DEBUG_IMX_UART_H */
diff --git a/arch/arm/include/debug/imx.S b/arch/arm/include/debug/imx.S
index c6f294cf18f0..619d8cc1ac12 100644
--- a/arch/arm/include/debug/imx.S
+++ b/arch/arm/include/debug/imx.S
@@ -10,35 +10,8 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 * 11 *
12 */ 12 */
13#define IMX6Q_UART1_BASE_ADDR 0x02020000
14#define IMX6Q_UART2_BASE_ADDR 0x021e8000
15#define IMX6Q_UART3_BASE_ADDR 0x021ec000
16#define IMX6Q_UART4_BASE_ADDR 0x021f0000
17#define IMX6Q_UART5_BASE_ADDR 0x021f4000
18 13
19/* 14#include "imx-uart.h"
20 * IMX6Q_UART_BASE_ADDR is put in the middle to force the expansion
21 * of IMX6Q_UART##n##_BASE_ADDR.
22 */
23#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
24#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n)
25#define IMX6Q_DEBUG_UART_BASE IMX6Q_UART_BASE(CONFIG_DEBUG_IMX6Q_UART_PORT)
26
27#ifdef CONFIG_DEBUG_IMX1_UART
28#define UART_PADDR 0x00206000
29#elif defined (CONFIG_DEBUG_IMX25_UART)
30#define UART_PADDR 0x43f90000
31#elif defined (CONFIG_DEBUG_IMX21_IMX27_UART)
32#define UART_PADDR 0x1000a000
33#elif defined (CONFIG_DEBUG_IMX31_IMX35_UART)
34#define UART_PADDR 0x43f90000
35#elif defined (CONFIG_DEBUG_IMX51_UART)
36#define UART_PADDR 0x73fbc000
37#elif defined (CONFIG_DEBUG_IMX53_UART)
38#define UART_PADDR 0x53fbc000
39#elif defined (CONFIG_DEBUG_IMX6Q_UART)
40#define UART_PADDR IMX6Q_DEBUG_UART_BASE
41#endif
42 15
43/* 16/*
44 * FIXME: This is a copy of IMX_IO_P2V in hardware.h, and needs to 17 * FIXME: This is a copy of IMX_IO_P2V in hardware.h, and needs to